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https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-19 02:52:53 +02:00
Move helper classes into anonymous namespaces.
No functionality change intended. llvm-svn: 311288
This commit is contained in:
parent
e0313d3bd2
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b795ef1cb5
@ -4031,6 +4031,7 @@ void llvm::WriteIndexToFile(
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Out.write((char *)&Buffer.front(), Buffer.size());
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}
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namespace {
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/// Class to manage the bitcode writing for a thin link bitcode file.
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class ThinLinkBitcodeWriter : public ModuleBitcodeWriterBase {
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/// ModHash is for use in ThinLTO incremental build, generated while writing
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@ -4051,6 +4052,7 @@ public:
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private:
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void writeSimplifiedModuleInfo();
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};
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} // namespace
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// This function writes a simpilified module info for thin link bitcode file.
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// It only contains the source file name along with the name(the offset and
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@ -1656,6 +1656,7 @@ static bool despeculateCountZeros(IntrinsicInst *CountZeros,
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return true;
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}
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namespace {
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// This class provides helper functions to expand a memcmp library call into an
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// inline expansion.
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class MemCmpExpansion {
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@ -1703,6 +1704,7 @@ public:
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unsigned NumLoadsPerBlock, const DataLayout &DL);
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Value *getMemCmpExpansion(uint64_t Size);
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};
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} // namespace
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MemCmpExpansion::ResultBlock::ResultBlock()
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: BB(nullptr), PhiSrc1(nullptr), PhiSrc2(nullptr) {}
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@ -7015,6 +7015,7 @@ static bool createVirtualRegs(SmallVector<unsigned, 4> &Regs, unsigned NumRegs,
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return true;
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}
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namespace {
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class ExtraFlags {
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unsigned Flags = 0;
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@ -7048,6 +7049,7 @@ public:
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unsigned get() const { return Flags; }
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};
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} // namespace
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/// visitInlineAsm - Handle a call to an InlineAsm object.
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///
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@ -1287,10 +1287,10 @@ static void propagateSwiftErrorVRegs(FunctionLoweringInfo *FuncInfo) {
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}
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}
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void preassignSwiftErrorRegs(const TargetLowering *TLI,
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FunctionLoweringInfo *FuncInfo,
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BasicBlock::const_iterator Begin,
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BasicBlock::const_iterator End) {
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static void preassignSwiftErrorRegs(const TargetLowering *TLI,
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FunctionLoweringInfo *FuncInfo,
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BasicBlock::const_iterator Begin,
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BasicBlock::const_iterator End) {
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if (!TLI->supportSwiftError() || FuncInfo->SwiftErrorVals.empty())
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return;
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@ -927,7 +927,6 @@ namespace {
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struct DWARFSectionMap final : public DWARFSection {
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RelocAddrMap Relocs;
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};
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} // namespace
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class DWARFObjInMemory final : public DWARFObject {
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bool IsLittleEndian;
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@ -1279,6 +1278,7 @@ public:
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F(P.second);
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}
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};
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} // namespace
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std::unique_ptr<DWARFContext>
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DWARFContext::create(const object::ObjectFile &Obj, const LoadedObjectInfo *L,
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@ -169,7 +169,7 @@ Error GSIStreamBuilder::finalizeMsfLayout() {
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return Error::success();
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}
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bool comparePubSymByAddrAndName(const CVSymbol *LS, const CVSymbol *RS) {
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static bool comparePubSymByAddrAndName(const CVSymbol *LS, const CVSymbol *RS) {
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assert(LS->kind() == SymbolKind::S_PUB32);
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assert(RS->kind() == SymbolKind::S_PUB32);
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@ -60,6 +60,7 @@ static cl::opt<bool> PrintOnly("safepoint-ir-verifier-print-only",
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static void Verify(const Function &F, const DominatorTree &DT);
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namespace {
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struct SafepointIRVerifier : public FunctionPass {
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static char ID; // Pass identification, replacement for typeid
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DominatorTree DT;
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@ -79,6 +80,7 @@ struct SafepointIRVerifier : public FunctionPass {
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StringRef getPassName() const override { return "safepoint verifier"; }
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};
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} // namespace
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void llvm::verifySafepointIR(Function &F) {
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SafepointIRVerifier pass;
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@ -62,8 +62,8 @@ static void ZeroFillBytes(raw_ostream &OS, size_t Size) {
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OS.write(reinterpret_cast<char *>(FillData.data()), Size);
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}
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void writeInitialLength(const DWARFYAML::InitialLength &Length, raw_ostream &OS,
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bool IsLittleEndian) {
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static void writeInitialLength(const DWARFYAML::InitialLength &Length,
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raw_ostream &OS, bool IsLittleEndian) {
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writeInteger((uint32_t)Length.TotalLength, OS, IsLittleEndian);
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if (Length.isDWARF64())
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writeInteger((uint64_t)Length.TotalLength64, OS, IsLittleEndian);
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@ -131,6 +131,7 @@ void DWARFYAML::EmitPubSection(raw_ostream &OS,
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}
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}
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namespace {
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/// \brief An extension of the DWARFYAML::ConstVisitor which writes compile
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/// units and DIEs to a stream.
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class DumpVisitor : public DWARFYAML::ConstVisitor {
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@ -195,6 +196,7 @@ public:
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DumpVisitor(const DWARFYAML::Data &DI, raw_ostream &Out)
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: DWARFYAML::ConstVisitor(DI), OS(Out) {}
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};
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} // namespace
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void DWARFYAML::EmitDebugInfo(raw_ostream &OS, const DWARFYAML::Data &DI) {
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DumpVisitor Visitor(DI, OS);
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@ -34,11 +34,11 @@ void DWARFYAML::VisitorImpl<T>::onVariableSizeValue(uint64_t U, unsigned Size) {
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}
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}
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unsigned getOffsetSize(const DWARFYAML::Unit &Unit) {
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static unsigned getOffsetSize(const DWARFYAML::Unit &Unit) {
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return Unit.Length.isDWARF64() ? 8 : 4;
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}
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unsigned getRefSize(const DWARFYAML::Unit &Unit) {
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static unsigned getRefSize(const DWARFYAML::Unit &Unit) {
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if (Unit.Version == 2)
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return Unit.AddrSize;
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return getOffsetSize(Unit);
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@ -50,6 +50,7 @@ using namespace llvm;
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AArch64CallLowering::AArch64CallLowering(const AArch64TargetLowering &TLI)
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: CallLowering(&TLI) {}
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namespace {
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struct IncomingArgHandler : public CallLowering::ValueHandler {
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IncomingArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
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CCAssignFn *AssignFn)
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@ -167,6 +168,7 @@ struct OutgoingArgHandler : public CallLowering::ValueHandler {
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CCAssignFn *AssignFnVarArg;
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uint64_t StackSize;
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};
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} // namespace
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void AArch64CallLowering::splitToValueTypes(
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const ArgInfo &OrigArg, SmallVectorImpl<ArgInfo> &SplitArgs,
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@ -516,10 +516,12 @@ bool AMDGPULibFunc::parseName(const StringRef& fullName) {
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///////////////////////////////////////////////////////////////////////////////
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// Itanium Demangling
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namespace {
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struct ItaniumParamParser {
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AMDGPULibFunc::Param Prev;
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bool parseItaniumParam(StringRef& param, AMDGPULibFunc::Param &res);
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};
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} // namespace
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bool ItaniumParamParser::parseItaniumParam(StringRef& param,
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AMDGPULibFunc::Param &res) {
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@ -689,7 +691,7 @@ static const char *getItaniumTypeName(AMDGPULibFunc::EType T) {
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return nullptr;
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}
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namespace {
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// Itanium mangling ABI says:
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// "5.1.8. Compression
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// ... Each non-terminal in the grammar for which <substitution> appears on the
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@ -784,6 +786,7 @@ public:
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if (Ptr.ArgType) Str.push_back(Ptr);
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}
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};
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} // namespace
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std::string AMDGPULibFunc::mangleNameItanium() const {
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SmallString<128> Buf;
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@ -8782,7 +8782,8 @@ static bool matchVectorShuffleAsBlend(SDValue V1, SDValue V2,
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return true;
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}
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uint64_t scaleVectorShuffleBlendMask(uint64_t BlendMask, int Size, int Scale) {
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static uint64_t scaleVectorShuffleBlendMask(uint64_t BlendMask, int Size,
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int Scale) {
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uint64_t ScaledMask = 0;
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for (int i = 0; i != Size; ++i)
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if (BlendMask & (1ull << i))
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@ -167,7 +167,7 @@ X86InstructionSelector::getRegClass(LLT Ty, unsigned Reg,
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return getRegClass(Ty, RegBank);
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}
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unsigned getSubRegIndex(const TargetRegisterClass *RC) {
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static unsigned getSubRegIndex(const TargetRegisterClass *RC) {
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unsigned SubIdx = X86::NoSubRegister;
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if (RC == &X86::GR32RegClass) {
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SubIdx = X86::sub_32bit;
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@ -180,7 +180,7 @@ unsigned getSubRegIndex(const TargetRegisterClass *RC) {
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return SubIdx;
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}
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const TargetRegisterClass *getRegClassFromGRPhysReg(unsigned Reg) {
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static const TargetRegisterClass *getRegClassFromGRPhysReg(unsigned Reg) {
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assert(TargetRegisterInfo::isPhysicalRegister(Reg));
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if (X86::GR64RegClass.contains(Reg))
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return &X86::GR64RegClass;
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@ -403,8 +403,9 @@ unsigned X86InstructionSelector::getLoadStoreOp(LLT &Ty, const RegisterBank &RB,
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}
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// Fill in an address from the given instruction.
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void X86SelectAddress(const MachineInstr &I, const MachineRegisterInfo &MRI,
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X86AddressMode &AM) {
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static void X86SelectAddress(const MachineInstr &I,
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const MachineRegisterInfo &MRI,
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X86AddressMode &AM) {
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assert(I.getOperand(0).isReg() && "unsupported opperand.");
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assert(MRI.getType(I.getOperand(0).getReg()).isPointer() &&
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@ -148,6 +148,7 @@ PHIExpression::~PHIExpression() = default;
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}
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}
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namespace {
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// Tarjan's SCC finding algorithm with Nuutila's improvements
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// SCCIterator is actually fairly complex for the simple thing we want.
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// It also wants to hand us SCC's that are unrelated to the phi node we ask
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@ -380,6 +381,7 @@ private:
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// This is used so we can detect store equivalence changes properly.
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int StoreCount = 0;
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};
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} // namespace
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namespace llvm {
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struct ExactEqualsExpression {
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@ -21,6 +21,7 @@ using namespace llvm;
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using namespace llvm::xray;
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using llvm::yaml::Input;
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namespace {
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using XRayRecordStorage =
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std::aligned_storage<sizeof(XRayRecord), alignof(XRayRecord)>::type;
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@ -134,7 +135,7 @@ struct FDRState {
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uint64_t CurrentBufferConsumed;
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};
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Twine fdrStateToTwine(const FDRState::Token &state) {
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const char *fdrStateToTwine(const FDRState::Token &state) {
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switch (state) {
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case FDRState::Token::NEW_BUFFER_RECORD_OR_EOF:
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return "NEW_BUFFER_RECORD_OR_EOF";
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@ -484,6 +485,7 @@ Error loadYAMLLog(StringRef Data, XRayFileHeader &FileHeader,
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});
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return Error::success();
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}
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} // namespace
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Expected<Trace> llvm::xray::loadTraceFile(StringRef Filename, bool Sort) {
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int Fd;
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