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AMDGPU: Fix some more incorrect check lines

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This commit is contained in:
Jay Foad 2020-02-26 09:46:07 +00:00
parent f5f9572e91
commit b7d809934c
12 changed files with 17 additions and 17 deletions
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4
test/CodeGen/AMDGPU/bitcast-v4f16-v4i16.ll
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@ -3,7 +3,7 @@
; creating v4i16->v4f16 and v4f16->v4i16 bitcasts in the selection DAG is rather
; difficult, so this test has to throw in some llvm.amdgcn.wqm to get them
; LABEL: {{^}}test_to_i16:
; CHECK-LABEL: {{^}}test_to_i16:
; CHECK: s_endpgm
define amdgpu_ps void @test_to_i16(<4 x i32> inreg, <4 x half> inreg) #0 {
%a_tmp = call <4 x half> @llvm.amdgcn.wqm.v4f16(<4 x half> %1)
@ -15,7 +15,7 @@ define amdgpu_ps void @test_to_i16(<4 x i32> inreg, <4 x half> inreg) #0 {
ret void
}
; LABEL: {{^}}test_to_half:
; CHECK-LABEL: {{^}}test_to_half:
; CHECK: s_endpgm
define amdgpu_ps void @test_to_half(<4 x i32> inreg, <4 x i16> inreg) #0 {
%a_tmp = call <4 x i16> @llvm.amdgcn.wqm.v4i16(<4 x i16> %1)

2
test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir
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@ -164,7 +164,7 @@ body: |
---
# GCN-LABEL: name: s_fold_shl_imm_regimm_32{{$}}
# GC1: %13 = V_MOV_B32_e32 4096, implicit $exec
# GCN: %13:vgpr_32 = V_MOV_B32_e32 4096, implicit $exec
# GCN: BUFFER_STORE_DWORD_OFFSET killed %13,
name: s_fold_shl_imm_regimm_32

2
test/CodeGen/AMDGPU/flat-load-clustering.mir
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@ -1,6 +1,6 @@
# RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -run-pass machine-scheduler -o - %s | FileCheck -check-prefix=GCN %s
# CGN-LABEL: name: flat_load_clustering
# GCN-LABEL: name: flat_load_clustering
# GCN: FLAT_LOAD_DWORD
# GCN-NEXT: FLAT_LOAD_DWORD
--- |

4
test/CodeGen/AMDGPU/gfx10-vop-literal.ll
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@ -1,7 +1,7 @@
; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX10 %s
; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9 %s
; GNC-LABEL: {{^}}test_add_lit:
; GCN-LABEL: {{^}}test_add_lit:
; GFX10: v_add_co_u32_e64 v{{[0-9]+}}, vcc_lo, 0x80992bff, v{{[0-9]+}}
; GFX10: v_add_co_ci_u32_e32 v{{[0-9]+}}, vcc_lo, 0xe7, v{{[0-9]+}}, vcc_lo
; GFX9: v_mov_b32_e32 [[C2:v[0-9]+]], 0xe7
@ -16,7 +16,7 @@ define amdgpu_kernel void @test_add_lit(i64 addrspace(1)* %p) {
ret void
}
; GNC-LABEL: {{^}}test_cndmask_lit:
; GCN-LABEL: {{^}}test_cndmask_lit:
; GFX10: v_cndmask_b32_e32 v{{[0-9]+}}, 0x3039, v{{[0-9]+}}, vcc_lo
; GFX9: v_mov_b32_e32 [[C:v[0-9]+]], 0x3039
; GFX9: v_cndmask_b32_e32 v{{[0-9]+}}, [[C]], v{{[0-9]+}}, vcc

2
test/CodeGen/AMDGPU/global-saddr.ll
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@ -87,7 +87,7 @@ entry:
; GFX9: global_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, off{{$}}
; GFX9: global_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, off offset:16{{$}}
; GFX9-NEXT: s_waitcnt
; NGFX9-NOT: global_load_dword
; GFX9-NOT: global_load_dword
define amdgpu_cs void @_amdgpu_cs_main(i64 inreg %arg) {
bb:

2
test/CodeGen/AMDGPU/global_atomics_i64.ll
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@ -413,7 +413,7 @@ entry:
; GCN-LABEL: {{^}}atomic_umax_i64_addr64_offset:
; CI: buffer_atomic_umax_x2 v{{\[[0-9]+:[0-9]+\]}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:32{{$}}
; VI: flat_atomic_umax_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
; FX9: global_atomic_umax_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} offset:32{{$}}
; GFX9: global_atomic_umax_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}}, off offset:32{{$}}
define amdgpu_kernel void @atomic_umax_i64_addr64_offset(i64 addrspace(1)* %out, i64 %in, i64 %index) {
entry:
%ptr = getelementptr i64, i64 addrspace(1)* %out, i64 %index

2
test/CodeGen/AMDGPU/kernel-args.ll
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@ -773,7 +773,7 @@ define amdgpu_kernel void @i1_arg(i1 addrspace(1)* %out, i1 %x) nounwind {
; HSA-GFX9: kernarg_segment_alignment = 4
; GCN: s_load_dword
; SGCN: buffer_store_dword
; GCN: {{buffer|flat|global}}_store_dword
define amdgpu_kernel void @i1_arg_zext_i32(i32 addrspace(1)* %out, i1 %x) nounwind {
%ext = zext i1 %x to i32
store i32 %ext, i32 addrspace(1)* %out, align 4

4
test/CodeGen/AMDGPU/lds-bounds.ll
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@ -64,7 +64,7 @@ entry:
; GCN-LABEL: {{^}}store_global_var_idx_case1:
; SI: ds_write_b32
; SI: ds_write_b32
; NONSI: ds_write2_b32
; NOSI: ds_write2_b32
define amdgpu_cs void @store_global_var_idx_case1(i32 %idx) #0 {
entry:
%ptr.a = getelementptr [512 x i32], [512 x i32] addrspace(3)* @compute_lds, i32 0, i32 %idx
@ -79,7 +79,7 @@ entry:
; GCN-LABEL: {{^}}load_global_var_idx_case1:
; SI: ds_read_b32
; SI: ds_read_b32
; NONSI: ds_read2_b32
; NOSI: ds_read2_b32
define amdgpu_cs <2 x float> @load_global_var_idx_case1(i32 %idx) #0 {
entry:
%ptr.a = getelementptr [512 x i32], [512 x i32] addrspace(3)* @compute_lds, i32 0, i32 %idx

2
test/CodeGen/AMDGPU/simplify-libcalls.ll
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@ -787,6 +787,6 @@ entry:
; GCN-PRELINK: declare float @_Z4cbrtf(float) local_unnamed_addr #[[$NOUNWIND_READONLY]]
; GCN-PRELINK: declare float @_Z11native_sqrtf(float) local_unnamed_addr #[[$NOUNWIND_READONLY]]
; CGN-PRELINK: attributes #[[$NOUNWIND]] = { nounwind }
; GCN-PRELINK: attributes #[[$NOUNWIND]] = { nounwind }
; GCN-PRELINK: attributes #[[$NOUNWIND_READONLY]] = { nounwind readonly }
attributes #0 = { nounwind }

2
test/CodeGen/AMDGPU/v_cndmask.ll
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@ -309,7 +309,7 @@ define amdgpu_kernel void @fcmp_k0_vgprX_select_k1_vgprZ_v4f32(<4 x float> addrs
; GCN: load_dword
; GCN: load_ubyte
; GCN-DAG: v_cmp_gt_i32_e32 vcc, 0, v
; DCN-DAG: v_and_b32_e32 v{{[0-9]+}}, 1,
; GCN-DAG: v_and_b32_e32 v{{[0-9]+}}, 1,
; GCN-DAG: v_cmp_eq_u32_e64 s{{\[[0-9]+:[0-9]+\]}}, 1, v
; GCN-DAG: s_or_b64 s{{\[[0-9]+:[0-9]+\]}}, vcc, s{{\[[0-9]+:[0-9]+\]}}
; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, s

4
test/CodeGen/AMDGPU/waitcnt-preexisting.mir
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@ -2,8 +2,8 @@
# GCN-LABEL: name: test{{$}}
# GCN: S_WAITCNT -16257
# GGN: DS_READ2_B32
# GGN: DS_READ2_B32
# GCN: DS_READ2_B32
# GCN: DS_READ2_B32
# GCN: S_WAITCNT 383{{$}}
# GCN-NEXT: $vgpr1 = V_ADD_U32_e32 1, killed $vgpr1, implicit $exec
# GCN-NEXT: $vgpr1 = V_MAX_U32_e32 killed $vgpr0, killed $vgpr1, implicit $exec

4
test/CodeGen/AMDGPU/wave32.ll
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@ -476,8 +476,8 @@ exit:
}
; GCN-LABEL: {{^}}fdiv_f32:
; GFC1032: v_div_scale_f32 v{{[0-9]+}}, vcc_lo, s{{[0-9]+}}, v{{[0-9]+}}, s{{[0-9]+}}
; GFC1064: v_div_scale_f32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v{{[0-9]+}}, s{{[0-9]+}}
; GFX1032: v_div_scale_f32 v{{[0-9]+}}, vcc_lo, s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}
; GFX1064: v_div_scale_f32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}
; GCN: v_rcp_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
; GCN-NOT: vcc
; GCN: v_div_fmas_f32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}