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Generalize the PassConfig API and remove addFinalizeRegAlloc().
The target hooks are getting out of hand. What does it mean to run before or after regalloc anyway? Allowing either Pass* or AnalysisID pass identification should make it much easier for targets to use the substitutePass and insertPass APIs, and create less need for badly named target hooks. llvm-svn: 179140
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@ -35,6 +35,46 @@ namespace llvm {
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class PassConfigImpl;
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/// Discriminated union of Pass ID types.
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///
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/// The PassConfig API prefers dealing with IDs because they are safer and more
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/// efficient. IDs decouple configuration from instantiation. This way, when a
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/// pass is overriden, it isn't unnecessarily instantiated. It is also unsafe to
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/// refer to a Pass pointer after adding it to a pass manager, which deletes
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/// redundant pass instances.
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///
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/// However, it is convient to directly instantiate target passes with
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/// non-default ctors. These often don't have a registered PassInfo. Rather than
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/// force all target passes to implement the pass registry boilerplate, allow
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/// the PassConfig API to handle either type.
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///
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/// AnalysisID is sadly char*, so PointerIntPair won't work.
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class IdentifyingPassPtr {
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void *P;
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bool IsInstance;
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public:
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IdentifyingPassPtr(): P(0), IsInstance(false) {}
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IdentifyingPassPtr(AnalysisID IDPtr): P((void*)IDPtr), IsInstance(false) {}
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IdentifyingPassPtr(Pass *InstancePtr)
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: P((void*)InstancePtr), IsInstance(true) {}
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bool isValid() const { return P; }
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bool isInstance() const { return IsInstance; }
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AnalysisID getID() const {
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assert(!IsInstance && "Not a Pass ID");
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return (AnalysisID)P;
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}
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Pass *getInstance() const {
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assert(IsInstance && "Not a Pass Instance");
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return (Pass *)P;
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}
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};
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template <> struct isPodLike<IdentifyingPassPtr> {
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static const bool value = true;
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};
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/// Target-Independent Code Generator Pass Configuration Options.
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///
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/// This is an ImmutablePass solely for the purpose of exposing CodeGen options
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@ -117,20 +157,22 @@ public:
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/// Allow the target to override a specific pass without overriding the pass
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/// pipeline. When passes are added to the standard pipeline at the
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/// point where StandardID is expected, add TargetID in its place.
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void substitutePass(AnalysisID StandardID, AnalysisID TargetID);
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void substitutePass(AnalysisID StandardID, IdentifyingPassPtr TargetID);
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/// Insert InsertedPassID pass after TargetPassID pass.
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void insertPass(AnalysisID TargetPassID, AnalysisID InsertedPassID);
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void insertPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID);
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/// Allow the target to enable a specific standard pass by default.
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void enablePass(AnalysisID PassID) { substitutePass(PassID, PassID); }
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/// Allow the target to disable a specific standard pass by default.
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void disablePass(AnalysisID PassID) { substitutePass(PassID, 0); }
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void disablePass(AnalysisID PassID) {
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substitutePass(PassID, IdentifyingPassPtr());
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}
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/// Return the pass substituted for StandardID by the target.
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/// If no substitution exists, return StandardID.
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AnalysisID getPassSubstitution(AnalysisID StandardID) const;
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IdentifyingPassPtr getPassSubstitution(AnalysisID StandardID) const;
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/// Return true if the optimized regalloc pipeline is enabled.
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bool getOptimizeRegAlloc() const;
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@ -222,17 +264,6 @@ protected:
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return false;
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}
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/// addFinalizeRegAlloc - This method may be implemented by targets that want
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/// to run passes within the regalloc pipeline, immediately after the register
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/// allocation pass itself. These passes run as soon as virtual regisiters
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/// have been rewritten to physical registers but before and other postRA
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/// optimization happens. Targets that have marked instructions for bundling
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/// must have finalized those bundles by the time these passes have run,
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/// because subsequent passes are not guaranteed to be bundle-aware.
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virtual bool addFinalizeRegAlloc() {
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return false;
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}
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/// addPostRegAlloc - This method may be implemented by targets that want to
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/// run passes after register allocation pass pipeline but before
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/// prolog-epilog insertion. This should return true if -print-machineinstrs
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@ -93,9 +93,10 @@ static cl::opt<bool> EarlyLiveIntervals("early-live-intervals", cl::Hidden,
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/// simple binary flags that either suppress the pass or do nothing.
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/// i.e. -disable-mypass=false has no effect.
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/// These should be converted to boolOrDefault in order to use applyOverride.
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static AnalysisID applyDisable(AnalysisID PassID, bool Override) {
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static IdentifyingPassPtr applyDisable(IdentifyingPassPtr PassID,
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bool Override) {
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if (Override)
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return 0;
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return IdentifyingPassPtr();
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return PassID;
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}
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@ -103,19 +104,20 @@ static AnalysisID applyDisable(AnalysisID PassID, bool Override) {
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/// flags with ternary conditions. TargetID is passed through by default. The
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/// pass is suppressed when the option is false. When the option is true, the
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/// StandardID is selected if the target provides no default.
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static AnalysisID applyOverride(AnalysisID TargetID, cl::boolOrDefault Override,
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AnalysisID StandardID) {
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static IdentifyingPassPtr applyOverride(IdentifyingPassPtr TargetID,
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cl::boolOrDefault Override,
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AnalysisID StandardID) {
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switch (Override) {
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case cl::BOU_UNSET:
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return TargetID;
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case cl::BOU_TRUE:
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if (TargetID)
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if (TargetID.isValid())
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return TargetID;
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if (StandardID == 0)
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report_fatal_error("Target cannot enable pass");
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return StandardID;
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case cl::BOU_FALSE:
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return 0;
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return IdentifyingPassPtr();
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}
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llvm_unreachable("Invalid command line option state");
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}
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@ -132,7 +134,8 @@ static AnalysisID applyOverride(AnalysisID TargetID, cl::boolOrDefault Override,
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/// StandardID may be a pseudo ID. In that case TargetID is the name of the real
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/// pass to run. This allows multiple options to control a single pass depending
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/// on where in the pipeline that pass is added.
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static AnalysisID overridePass(AnalysisID StandardID, AnalysisID TargetID) {
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static IdentifyingPassPtr overridePass(AnalysisID StandardID,
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IdentifyingPassPtr TargetID) {
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if (StandardID == &PostRASchedulerID)
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return applyDisable(TargetID, DisablePostRA);
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@ -200,11 +203,11 @@ public:
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// user interface. For example, a target may disable a standard pass by
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// default by substituting a pass ID of zero, and the user may still enable
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// that standard pass with an explicit command line option.
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DenseMap<AnalysisID,AnalysisID> TargetPasses;
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DenseMap<AnalysisID,IdentifyingPassPtr> TargetPasses;
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/// Store the pairs of <AnalysisID, AnalysisID> of which the second pass
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/// is inserted after each instance of the first one.
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SmallVector<std::pair<AnalysisID, AnalysisID>, 4> InsertedPasses;
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SmallVector<std::pair<AnalysisID, IdentifyingPassPtr>, 4> InsertedPasses;
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};
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} // namespace llvm
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@ -239,9 +242,13 @@ TargetPassConfig::TargetPassConfig(TargetMachine *tm, PassManagerBase &pm)
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/// Insert InsertedPassID pass after TargetPassID.
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void TargetPassConfig::insertPass(AnalysisID TargetPassID,
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AnalysisID InsertedPassID) {
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assert(TargetPassID != InsertedPassID && "Insert a pass after itself!");
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std::pair<AnalysisID, AnalysisID> P(TargetPassID, InsertedPassID);
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IdentifyingPassPtr InsertedPassID) {
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assert((!InsertedPassID.isInstance() &&
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TargetPassID != InsertedPassID.getID()) ||
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(InsertedPassID.isInstance() &&
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TargetPassID != InsertedPassID.getInstance()->getPassID()) &&
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"Insert a pass after itself!");
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std::pair<AnalysisID, IdentifyingPassPtr> P(TargetPassID, InsertedPassID);
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Impl->InsertedPasses.push_back(P);
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}
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@ -265,12 +272,12 @@ void TargetPassConfig::setOpt(bool &Opt, bool Val) {
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}
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void TargetPassConfig::substitutePass(AnalysisID StandardID,
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AnalysisID TargetID) {
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IdentifyingPassPtr TargetID) {
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Impl->TargetPasses[StandardID] = TargetID;
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}
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AnalysisID TargetPassConfig::getPassSubstitution(AnalysisID ID) const {
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DenseMap<AnalysisID, AnalysisID>::const_iterator
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IdentifyingPassPtr TargetPassConfig::getPassSubstitution(AnalysisID ID) const {
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DenseMap<AnalysisID, IdentifyingPassPtr>::const_iterator
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I = Impl->TargetPasses.find(ID);
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if (I == Impl->TargetPasses.end())
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return ID;
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@ -303,24 +310,39 @@ void TargetPassConfig::addPass(Pass *P) {
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/// Add a CodeGen pass at this point in the pipeline after checking for target
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/// and command line overrides.
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///
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/// addPass cannot return a pointer to the pass instance because is internal the
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/// PassManager and the instance we create here may already be freed.
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AnalysisID TargetPassConfig::addPass(AnalysisID PassID) {
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AnalysisID TargetID = getPassSubstitution(PassID);
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AnalysisID FinalID = overridePass(PassID, TargetID);
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if (FinalID == 0)
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return FinalID;
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IdentifyingPassPtr TargetID = getPassSubstitution(PassID);
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IdentifyingPassPtr FinalPtr = overridePass(PassID, TargetID);
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if (!FinalPtr.isValid())
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return 0;
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Pass *P;
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if (FinalPtr.isInstance())
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P = FinalPtr.getInstance();
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else {
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P = Pass::createPass(FinalPtr.getID());
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if (!P)
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llvm_unreachable("Pass ID not registered");
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}
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AnalysisID FinalID = P->getPassID();
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addPass(P); // Ends the lifetime of P.
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Pass *P = Pass::createPass(FinalID);
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if (!P)
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llvm_unreachable("Pass ID not registered");
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addPass(P);
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// Add the passes after the pass P if there is any.
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for (SmallVector<std::pair<AnalysisID, AnalysisID>, 4>::iterator
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for (SmallVector<std::pair<AnalysisID, IdentifyingPassPtr>, 4>::iterator
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I = Impl->InsertedPasses.begin(), E = Impl->InsertedPasses.end();
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I != E; ++I) {
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if ((*I).first == PassID) {
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assert((*I).second && "Illegal Pass ID!");
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Pass *NP = Pass::createPass((*I).second);
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assert(NP && "Pass ID not registered");
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assert((*I).second.isValid() && "Illegal Pass ID!");
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Pass *NP;
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if ((*I).second.isInstance())
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NP = (*I).second.getInstance();
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else {
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NP = Pass::createPass((*I).second.getID());
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assert(NP && "Pass ID not registered");
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}
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addPass(NP);
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}
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}
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@ -687,14 +709,6 @@ void TargetPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
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addPass(&VirtRegRewriterID);
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printAndVerify("After Virtual Register Rewriter");
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// FinalizeRegAlloc is convenient until MachineInstrBundles is more mature,
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// but eventually, all users of it should probably be moved to addPostRA and
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// it can go away. Currently, it's the intended place for targets to run
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// FinalizeMachineBundles, because passes other than MachineScheduling an
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// RegAlloc itself may not be aware of bundles.
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if (addFinalizeRegAlloc())
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printAndVerify("After RegAlloc finalization");
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// Perform stack slot coloring and post-ra machine LICM.
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//
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// FIXME: Re-enable coloring with register when it's capable of adding
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