diff --git a/lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp b/lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp index f67258843a0..1cbd23b1a48 100644 --- a/lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp +++ b/lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp @@ -42,33 +42,35 @@ std::string FuncName(unsigned AccessSize, bool IsWrite) { } class X86AddressSanitizer : public X86AsmInstrumentation { -public: + public: X86AddressSanitizer(const MCSubtargetInfo &STI) : X86AsmInstrumentation(STI), RepPrefix(false) {} virtual ~X86AddressSanitizer() {} // X86AsmInstrumentation implementation: - virtual void InstrumentAndEmitInstruction( - const MCInst &Inst, OperandVector &Operands, MCContext &Ctx, - const MCInstrInfo &MII, MCStreamer &Out) override { + virtual void InstrumentAndEmitInstruction(const MCInst &Inst, + OperandVector &Operands, + MCContext &Ctx, + const MCInstrInfo &MII, + MCStreamer &Out) override { InstrumentMOVS(Inst, Operands, Ctx, MII, Out); - if (RepPrefix) - EmitInstruction(Out, MCInstBuilder(X86::REP_PREFIX)); + if (RepPrefix) EmitInstruction(Out, MCInstBuilder(X86::REP_PREFIX)); InstrumentMOV(Inst, Operands, Ctx, MII, Out); RepPrefix = (Inst.getOpcode() == X86::REP_PREFIX); - if (!RepPrefix) - EmitInstruction(Out, Inst); + if (!RepPrefix) EmitInstruction(Out, Inst); } // Should be implemented differently in x86_32 and x86_64 subclasses. - virtual void InstrumentMemOperandSmallImpl( - X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx, - MCStreamer &Out) = 0; - virtual void InstrumentMemOperandLargeImpl( - X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx, - MCStreamer &Out) = 0; + virtual void InstrumentMemOperandSmallImpl(X86Operand &Op, + unsigned AccessSize, bool IsWrite, + MCContext &Ctx, + MCStreamer &Out) = 0; + virtual void InstrumentMemOperandLargeImpl(X86Operand &Op, + unsigned AccessSize, bool IsWrite, + MCContext &Ctx, + MCStreamer &Out) = 0; virtual void InstrumentMOVSImpl(unsigned AccessSize, MCContext &Ctx, MCStreamer &Out) = 0; @@ -83,14 +85,15 @@ public: void EmitLabel(MCStreamer &Out, MCSymbol *Label) { Out.EmitLabel(Label); } -protected: + protected: // True when previous instruction was actually REP prefix. bool RepPrefix; }; -void X86AddressSanitizer::InstrumentMemOperand( - MCParsedAsmOperand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx, - MCStreamer &Out) { +void X86AddressSanitizer::InstrumentMemOperand(MCParsedAsmOperand &Op, + unsigned AccessSize, + bool IsWrite, MCContext &Ctx, + MCStreamer &Out) { assert(Op.isMem() && "Op should be a memory operand."); assert((AccessSize & (AccessSize - 1)) == 0 && AccessSize <= 16 && "AccessSize should be a power of two, less or equal than 16."); @@ -107,9 +110,10 @@ void X86AddressSanitizer::InstrumentMemOperand( InstrumentMemOperandLargeImpl(MemOp, AccessSize, IsWrite, Ctx, Out); } -void X86AddressSanitizer::InstrumentMOVSBase( - unsigned DstReg, unsigned SrcReg, unsigned CntReg, unsigned AccessSize, - MCContext &Ctx, MCStreamer &Out) { +void X86AddressSanitizer::InstrumentMOVSBase(unsigned DstReg, unsigned SrcReg, + unsigned CntReg, + unsigned AccessSize, + MCContext &Ctx, MCStreamer &Out) { // FIXME: check whole ranges [DstReg .. DstReg + AccessSize * (CntReg - 1)] // and [SrcReg .. SrcReg + AccessSize * (CntReg - 1)]. @@ -149,92 +153,95 @@ void X86AddressSanitizer::InstrumentMOVSBase( } } -void X86AddressSanitizer::InstrumentMOVS( - const MCInst &Inst, OperandVector &Operands, MCContext &Ctx, - const MCInstrInfo &MII, MCStreamer &Out) { +void X86AddressSanitizer::InstrumentMOVS(const MCInst &Inst, + OperandVector &Operands, + MCContext &Ctx, const MCInstrInfo &MII, + MCStreamer &Out) { // Access size in bytes. unsigned AccessSize = 0; switch (Inst.getOpcode()) { - case X86::MOVSB: - AccessSize = 1; - break; - case X86::MOVSW: - AccessSize = 2; - break; - case X86::MOVSL: - AccessSize = 4; - break; - case X86::MOVSQ: - AccessSize = 8; - break; - default: - return; + case X86::MOVSB: + AccessSize = 1; + break; + case X86::MOVSW: + AccessSize = 2; + break; + case X86::MOVSL: + AccessSize = 4; + break; + case X86::MOVSQ: + AccessSize = 8; + break; + default: + return; } InstrumentMOVSImpl(AccessSize, Ctx, Out); } -void X86AddressSanitizer::InstrumentMOV( - const MCInst &Inst, OperandVector &Operands, MCContext &Ctx, - const MCInstrInfo &MII, MCStreamer &Out) { +void X86AddressSanitizer::InstrumentMOV(const MCInst &Inst, + OperandVector &Operands, MCContext &Ctx, + const MCInstrInfo &MII, + MCStreamer &Out) { // Access size in bytes. unsigned AccessSize = 0; switch (Inst.getOpcode()) { - case X86::MOV8mi: - case X86::MOV8mr: - case X86::MOV8rm: - AccessSize = 1; - break; - case X86::MOV16mi: - case X86::MOV16mr: - case X86::MOV16rm: - AccessSize = 2; - break; - case X86::MOV32mi: - case X86::MOV32mr: - case X86::MOV32rm: - AccessSize = 4; - break; - case X86::MOV64mi32: - case X86::MOV64mr: - case X86::MOV64rm: - AccessSize = 8; - break; - case X86::MOVAPDmr: - case X86::MOVAPSmr: - case X86::MOVAPDrm: - case X86::MOVAPSrm: - AccessSize = 16; - break; - default: - return; + case X86::MOV8mi: + case X86::MOV8mr: + case X86::MOV8rm: + AccessSize = 1; + break; + case X86::MOV16mi: + case X86::MOV16mr: + case X86::MOV16rm: + AccessSize = 2; + break; + case X86::MOV32mi: + case X86::MOV32mr: + case X86::MOV32rm: + AccessSize = 4; + break; + case X86::MOV64mi32: + case X86::MOV64mr: + case X86::MOV64rm: + AccessSize = 8; + break; + case X86::MOVAPDmr: + case X86::MOVAPSmr: + case X86::MOVAPDrm: + case X86::MOVAPSrm: + AccessSize = 16; + break; + default: + return; } const bool IsWrite = MII.get(Inst.getOpcode()).mayStore(); for (unsigned Ix = 0; Ix < Operands.size(); ++Ix) { assert(Operands[Ix]); MCParsedAsmOperand &Op = *Operands[Ix]; - if (Op.isMem()) - InstrumentMemOperand(Op, AccessSize, IsWrite, Ctx, Out); + if (Op.isMem()) InstrumentMemOperand(Op, AccessSize, IsWrite, Ctx, Out); } } class X86AddressSanitizer32 : public X86AddressSanitizer { -public: + public: static const long kShadowOffset = 0x20000000; X86AddressSanitizer32(const MCSubtargetInfo &STI) : X86AddressSanitizer(STI) {} virtual ~X86AddressSanitizer32() {} - virtual void InstrumentMemOperandSmallImpl( - X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx, - MCStreamer &Out) override; - virtual void InstrumentMemOperandLargeImpl( - X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx, - MCStreamer &Out) override; + virtual void InstrumentMemOperandSmallImpl(X86Operand &Op, + unsigned AccessSize, bool IsWrite, + MCContext &Ctx, + MCStreamer &Out) override; + virtual void InstrumentMemOperandLargeImpl(X86Operand &Op, + unsigned AccessSize, bool IsWrite, + MCContext &Ctx, + MCStreamer &Out) override; virtual void InstrumentMOVSImpl(unsigned AccessSize, MCContext &Ctx, MCStreamer &Out) override; @@ -244,8 +251,10 @@ public: EmitInstruction(Out, MCInstBuilder(X86::CLD)); EmitInstruction(Out, MCInstBuilder(X86::MMX_EMMS)); - EmitInstruction(Out, MCInstBuilder(X86::AND64ri8).addReg(X86::ESP) - .addReg(X86::ESP).addImm(-16)); + EmitInstruction(Out, MCInstBuilder(X86::AND64ri8) + .addReg(X86::ESP) + .addReg(X86::ESP) + .addImm(-16)); EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(AddressReg)); const std::string &Fn = FuncName(AccessSize, IsWrite); @@ -256,9 +265,11 @@ public: } }; -void X86AddressSanitizer32::InstrumentMemOperandSmallImpl( - X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx, - MCStreamer &Out) { +void X86AddressSanitizer32::InstrumentMemOperandSmallImpl(X86Operand &Op, + unsigned AccessSize, + bool IsWrite, + MCContext &Ctx, + MCStreamer &Out) { EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(X86::EAX)); EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(X86::ECX)); EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(X86::EDX)); @@ -274,8 +285,9 @@ void X86AddressSanitizer32::InstrumentMemOperandSmallImpl( EmitInstruction( Out, MCInstBuilder(X86::MOV32rr).addReg(X86::ECX).addReg(X86::EAX)); - EmitInstruction(Out, MCInstBuilder(X86::SHR32ri).addReg(X86::ECX) - .addReg(X86::ECX).addImm(3)); + EmitInstruction( + Out, + MCInstBuilder(X86::SHR32ri).addReg(X86::ECX).addReg(X86::ECX).addImm(3)); { MCInst Inst; @@ -296,31 +308,34 @@ void X86AddressSanitizer32::InstrumentMemOperandSmallImpl( EmitInstruction( Out, MCInstBuilder(X86::MOV32rr).addReg(X86::EDX).addReg(X86::EAX)); - EmitInstruction(Out, MCInstBuilder(X86::AND32ri).addReg(X86::EDX) - .addReg(X86::EDX).addImm(7)); + EmitInstruction( + Out, + MCInstBuilder(X86::AND32ri).addReg(X86::EDX).addReg(X86::EDX).addImm(7)); switch (AccessSize) { - case 1: - break; - case 2: { - MCInst Inst; - Inst.setOpcode(X86::LEA32r); - Inst.addOperand(MCOperand::CreateReg(X86::EDX)); + case 1: + break; + case 2: { + MCInst Inst; + Inst.setOpcode(X86::LEA32r); + Inst.addOperand(MCOperand::CreateReg(X86::EDX)); - const MCExpr *Disp = MCConstantExpr::Create(1, Ctx); - std::unique_ptr Op( - X86Operand::CreateMem(0, Disp, X86::EDX, 0, 1, SMLoc(), SMLoc())); - Op->addMemOperands(Inst, 5); - EmitInstruction(Out, Inst); - break; - } - case 4: - EmitInstruction(Out, MCInstBuilder(X86::ADD32ri8).addReg(X86::EDX) - .addReg(X86::EDX).addImm(3)); - break; - default: - assert(false && "Incorrect access size"); - break; + const MCExpr *Disp = MCConstantExpr::Create(1, Ctx); + std::unique_ptr Op( + X86Operand::CreateMem(0, Disp, X86::EDX, 0, 1, SMLoc(), SMLoc())); + Op->addMemOperands(Inst, 5); + EmitInstruction(Out, Inst); + break; + } + case 4: + EmitInstruction(Out, MCInstBuilder(X86::ADD32ri8) + .addReg(X86::EDX) + .addReg(X86::EDX) + .addImm(3)); + break; + default: + assert(false && "Incorrect access size"); + break; } EmitInstruction( @@ -338,9 +353,11 @@ void X86AddressSanitizer32::InstrumentMemOperandSmallImpl( EmitInstruction(Out, MCInstBuilder(X86::POP32r).addReg(X86::EAX)); } -void X86AddressSanitizer32::InstrumentMemOperandLargeImpl( - X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx, - MCStreamer &Out) { +void X86AddressSanitizer32::InstrumentMemOperandLargeImpl(X86Operand &Op, + unsigned AccessSize, + bool IsWrite, + MCContext &Ctx, + MCStreamer &Out) { EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(X86::EAX)); EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(X86::ECX)); EmitInstruction(Out, MCInstBuilder(X86::PUSHF32)); @@ -354,8 +371,9 @@ void X86AddressSanitizer32::InstrumentMemOperandLargeImpl( } EmitInstruction( Out, MCInstBuilder(X86::MOV32rr).addReg(X86::ECX).addReg(X86::EAX)); - EmitInstruction(Out, MCInstBuilder(X86::SHR32ri).addReg(X86::ECX) - .addReg(X86::ECX).addImm(3)); + EmitInstruction( + Out, + MCInstBuilder(X86::SHR32ri).addReg(X86::ECX).addReg(X86::ECX).addImm(3)); { MCInst Inst; switch (AccessSize) { @@ -388,8 +406,9 @@ void X86AddressSanitizer32::InstrumentMemOperandLargeImpl( EmitInstruction(Out, MCInstBuilder(X86::POP32r).addReg(X86::EAX)); } -void X86AddressSanitizer32::InstrumentMOVSImpl( - unsigned AccessSize, MCContext &Ctx, MCStreamer &Out) { +void X86AddressSanitizer32::InstrumentMOVSImpl(unsigned AccessSize, + MCContext &Ctx, + MCStreamer &Out) { EmitInstruction(Out, MCInstBuilder(X86::PUSHF32)); // No need to test when ECX is equals to zero. @@ -408,23 +427,25 @@ void X86AddressSanitizer32::InstrumentMOVSImpl( } class X86AddressSanitizer64 : public X86AddressSanitizer { -public: + public: static const long kShadowOffset = 0x7fff8000; X86AddressSanitizer64(const MCSubtargetInfo &STI) : X86AddressSanitizer(STI) {} virtual ~X86AddressSanitizer64() {} - virtual void InstrumentMemOperandSmallImpl( - X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx, - MCStreamer &Out) override; - virtual void InstrumentMemOperandLargeImpl( - X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx, - MCStreamer &Out) override; + virtual void InstrumentMemOperandSmallImpl(X86Operand &Op, + unsigned AccessSize, bool IsWrite, + MCContext &Ctx, + MCStreamer &Out) override; + virtual void InstrumentMemOperandLargeImpl(X86Operand &Op, + unsigned AccessSize, bool IsWrite, + MCContext &Ctx, + MCStreamer &Out) override; virtual void InstrumentMOVSImpl(unsigned AccessSize, MCContext &Ctx, MCStreamer &Out) override; -private: + private: void EmitAdjustRSP(MCContext &Ctx, MCStreamer &Out, long Offset) { MCInst Inst; Inst.setOpcode(X86::LEA64r); @@ -442,8 +463,10 @@ private: EmitInstruction(Out, MCInstBuilder(X86::CLD)); EmitInstruction(Out, MCInstBuilder(X86::MMX_EMMS)); - EmitInstruction(Out, MCInstBuilder(X86::AND64ri8).addReg(X86::RSP) - .addReg(X86::RSP).addImm(-16)); + EmitInstruction(Out, MCInstBuilder(X86::AND64ri8) + .addReg(X86::RSP) + .addReg(X86::RSP) + .addImm(-16)); const std::string &Fn = FuncName(AccessSize, IsWrite); MCSymbol *FnSym = Ctx.GetOrCreateSymbol(StringRef(Fn)); @@ -453,9 +476,11 @@ private: } }; -void X86AddressSanitizer64::InstrumentMemOperandSmallImpl( - X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx, - MCStreamer &Out) { +void X86AddressSanitizer64::InstrumentMemOperandSmallImpl(X86Operand &Op, + unsigned AccessSize, + bool IsWrite, + MCContext &Ctx, + MCStreamer &Out) { EmitAdjustRSP(Ctx, Out, -128); EmitInstruction(Out, MCInstBuilder(X86::PUSH64r).addReg(X86::RAX)); EmitInstruction(Out, MCInstBuilder(X86::PUSH64r).addReg(X86::RCX)); @@ -470,8 +495,9 @@ void X86AddressSanitizer64::InstrumentMemOperandSmallImpl( } EmitInstruction( Out, MCInstBuilder(X86::MOV64rr).addReg(X86::RAX).addReg(X86::RDI)); - EmitInstruction(Out, MCInstBuilder(X86::SHR64ri).addReg(X86::RAX) - .addReg(X86::RAX).addImm(3)); + EmitInstruction( + Out, + MCInstBuilder(X86::SHR64ri).addReg(X86::RAX).addReg(X86::RAX).addImm(3)); { MCInst Inst; Inst.setOpcode(X86::MOV8rm); @@ -491,31 +517,34 @@ void X86AddressSanitizer64::InstrumentMemOperandSmallImpl( EmitInstruction( Out, MCInstBuilder(X86::MOV32rr).addReg(X86::ECX).addReg(X86::EDI)); - EmitInstruction(Out, MCInstBuilder(X86::AND32ri).addReg(X86::ECX) - .addReg(X86::ECX).addImm(7)); + EmitInstruction( + Out, + MCInstBuilder(X86::AND32ri).addReg(X86::ECX).addReg(X86::ECX).addImm(7)); switch (AccessSize) { - case 1: - break; - case 2: { - MCInst Inst; - Inst.setOpcode(X86::LEA32r); - Inst.addOperand(MCOperand::CreateReg(X86::ECX)); + case 1: + break; + case 2: { + MCInst Inst; + Inst.setOpcode(X86::LEA32r); + Inst.addOperand(MCOperand::CreateReg(X86::ECX)); - const MCExpr *Disp = MCConstantExpr::Create(1, Ctx); - std::unique_ptr Op( - X86Operand::CreateMem(0, Disp, X86::ECX, 0, 1, SMLoc(), SMLoc())); - Op->addMemOperands(Inst, 5); - EmitInstruction(Out, Inst); - break; - } - case 4: - EmitInstruction(Out, MCInstBuilder(X86::ADD32ri8).addReg(X86::ECX) - .addReg(X86::ECX).addImm(3)); - break; - default: - assert(false && "Incorrect access size"); - break; + const MCExpr *Disp = MCConstantExpr::Create(1, Ctx); + std::unique_ptr Op( + X86Operand::CreateMem(0, Disp, X86::ECX, 0, 1, SMLoc(), SMLoc())); + Op->addMemOperands(Inst, 5); + EmitInstruction(Out, Inst); + break; + } + case 4: + EmitInstruction(Out, MCInstBuilder(X86::ADD32ri8) + .addReg(X86::ECX) + .addReg(X86::ECX) + .addImm(3)); + break; + default: + assert(false && "Incorrect access size"); + break; } EmitInstruction( @@ -534,9 +563,11 @@ void X86AddressSanitizer64::InstrumentMemOperandSmallImpl( EmitAdjustRSP(Ctx, Out, 128); } -void X86AddressSanitizer64::InstrumentMemOperandLargeImpl( - X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx, - MCStreamer &Out) { +void X86AddressSanitizer64::InstrumentMemOperandLargeImpl(X86Operand &Op, + unsigned AccessSize, + bool IsWrite, + MCContext &Ctx, + MCStreamer &Out) { EmitAdjustRSP(Ctx, Out, -128); EmitInstruction(Out, MCInstBuilder(X86::PUSH64r).addReg(X86::RAX)); EmitInstruction(Out, MCInstBuilder(X86::PUSHF64)); @@ -548,20 +579,21 @@ void X86AddressSanitizer64::InstrumentMemOperandLargeImpl( Op.addMemOperands(Inst, 5); EmitInstruction(Out, Inst); } - EmitInstruction(Out, MCInstBuilder(X86::SHR64ri).addReg(X86::RAX) - .addReg(X86::RAX).addImm(3)); + EmitInstruction( + Out, + MCInstBuilder(X86::SHR64ri).addReg(X86::RAX).addReg(X86::RAX).addImm(3)); { MCInst Inst; switch (AccessSize) { - case 8: - Inst.setOpcode(X86::CMP8mi); - break; - case 16: - Inst.setOpcode(X86::CMP16mi); - break; - default: - assert(false && "Incorrect access size"); - break; + case 8: + Inst.setOpcode(X86::CMP8mi); + break; + case 16: + Inst.setOpcode(X86::CMP16mi); + break; + default: + assert(false && "Incorrect access size"); + break; } const MCExpr *Disp = MCConstantExpr::Create(kShadowOffset, Ctx); std::unique_ptr Op( @@ -583,8 +615,9 @@ void X86AddressSanitizer64::InstrumentMemOperandLargeImpl( EmitAdjustRSP(Ctx, Out, 128); } -void X86AddressSanitizer64::InstrumentMOVSImpl( - unsigned AccessSize, MCContext &Ctx, MCStreamer &Out) { +void X86AddressSanitizer64::InstrumentMOVSImpl(unsigned AccessSize, + MCContext &Ctx, + MCStreamer &Out) { EmitInstruction(Out, MCInstBuilder(X86::PUSHF64)); // No need to test when RCX is equals to zero. @@ -602,7 +635,7 @@ void X86AddressSanitizer64::InstrumentMOVSImpl( EmitInstruction(Out, MCInstBuilder(X86::POPF64)); } -} // End anonymous namespace +} // End anonymous namespace X86AsmInstrumentation::X86AsmInstrumentation(const MCSubtargetInfo &STI) : STI(STI) {} @@ -620,9 +653,9 @@ void X86AsmInstrumentation::EmitInstruction(MCStreamer &Out, Out.EmitInstruction(Inst, STI); } -X86AsmInstrumentation * -CreateX86AsmInstrumentation(const MCTargetOptions &MCOptions, - const MCContext &Ctx, const MCSubtargetInfo &STI) { +X86AsmInstrumentation *CreateX86AsmInstrumentation( + const MCTargetOptions &MCOptions, const MCContext &Ctx, + const MCSubtargetInfo &STI) { Triple T(STI.getTargetTriple()); const bool hasCompilerRTSupport = T.isOSLinux(); if (ClAsanInstrumentAssembly && hasCompilerRTSupport && @@ -635,4 +668,4 @@ CreateX86AsmInstrumentation(const MCTargetOptions &MCOptions, return new X86AsmInstrumentation(STI); } -} // End llvm namespace +} // End llvm namespace diff --git a/lib/Target/X86/AsmParser/X86AsmInstrumentation.h b/lib/Target/X86/AsmParser/X86AsmInstrumentation.h index 82c4956ee1b..2c3d05d1d41 100644 --- a/lib/Target/X86/AsmParser/X86AsmInstrumentation.h +++ b/lib/Target/X86/AsmParser/X86AsmInstrumentation.h @@ -26,12 +26,12 @@ class MCTargetOptions; class X86AsmInstrumentation; -X86AsmInstrumentation * -CreateX86AsmInstrumentation(const MCTargetOptions &MCOptions, - const MCContext &Ctx, const MCSubtargetInfo &STI); +X86AsmInstrumentation *CreateX86AsmInstrumentation( + const MCTargetOptions &MCOptions, const MCContext &Ctx, + const MCSubtargetInfo &STI); class X86AsmInstrumentation { -public: + public: virtual ~X86AsmInstrumentation(); // Tries to instrument and emit instruction. @@ -40,10 +40,10 @@ public: SmallVectorImpl> &Operands, MCContext &Ctx, const MCInstrInfo &MII, MCStreamer &Out); -protected: - friend X86AsmInstrumentation * - CreateX86AsmInstrumentation(const MCTargetOptions &MCOptions, - const MCContext &Ctx, const MCSubtargetInfo &STI); + protected: + friend X86AsmInstrumentation *CreateX86AsmInstrumentation( + const MCTargetOptions &MCOptions, const MCContext &Ctx, + const MCSubtargetInfo &STI); X86AsmInstrumentation(const MCSubtargetInfo &STI); @@ -52,6 +52,6 @@ protected: const MCSubtargetInfo &STI; }; -} // End llvm namespace +} // End llvm namespace #endif