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[NFC] fix trivial typos in comments and error message

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"is is" -> "is", "are are" -> "are"

llvm-svn: 329546
This commit is contained in:
Hiroshi Inoue 2018-04-09 04:37:53 +00:00
parent 3153e6c6d9
commit b7fe5786cc
7 changed files with 7 additions and 7 deletions
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2
lib/DebugInfo/PDB/GenericError.cpp
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@ -30,7 +30,7 @@ public:
return "Type server PDB was not found.";
case generic_error_code::dia_sdk_not_present:
return "LLVM was not compiled with support for DIA. This usually means "
"that you are are not using MSVC, or your Visual Studio "
"that you are not using MSVC, or your Visual Studio "
"installation "
"is corrupt.";
case generic_error_code::invalid_path:

2
lib/Support/APInt.cpp
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@ -922,7 +922,7 @@ void APInt::ashrSlowCase(unsigned ShiftAmt) {
// Save the original sign bit for later.
bool Negative = isNegative();
// WordShift is the inter-part shift; BitShift is is intra-part shift.
// WordShift is the inter-part shift; BitShift is intra-part shift.
unsigned WordShift = ShiftAmt / APINT_BITS_PER_WORD;
unsigned BitShift = ShiftAmt % APINT_BITS_PER_WORD;

2
lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
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@ -4514,7 +4514,7 @@ AArch64AsmParser::classifySymbolRef(const MCExpr *Expr,
BE->getOpcode() != MCBinaryExpr::Sub)
return false;
// See if the addend is is a constant, otherwise there's more going
// See if the addend is a constant, otherwise there's more going
// on here than we can deal with.
auto AddendExpr = dyn_cast<MCConstantExpr>(BE->getRHS());
if (!AddendExpr)

2
lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
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@ -239,7 +239,7 @@ const char *ARMAsmBackend::reasonForFixupRelaxation(const MCFixup &Fixup,
}
case ARM::fixup_arm_thumb_cb: {
// If we have a Thumb CBZ or CBNZ instruction and its target is the next
// instruction it is is actually out of range for the instruction.
// instruction it is actually out of range for the instruction.
// It will be changed to a NOP.
int64_t Offset = (Value & ~1);
if (Offset == 2)

2
lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
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@ -1520,7 +1520,7 @@ unsigned ARMMCCodeEmitter::
getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
// 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the
// 10 bits. lower 5 bits are the lsb of the mask, high five bits are the
// msb of the mask.
const MCOperand &MO = MI.getOperand(Op);
uint32_t v = ~MO.getImm();

2
lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
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@ -953,7 +953,7 @@ bool RISCVAsmParser::classifySymbolRef(const MCExpr *Expr,
isa<MCSymbolRefExpr>(BE->getRHS()))
return true;
// See if the addend is is a constant, otherwise there's more going
// See if the addend is a constant, otherwise there's more going
// on here than we can deal with.
auto AddendExpr = dyn_cast<MCConstantExpr>(BE->getRHS());
if (!AddendExpr)

2
lib/Transforms/Scalar/NewGVN.cpp
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@ -2207,7 +2207,7 @@ Value *NewGVN::getNextValueLeader(CongruenceClass *CC) const {
//
// - I must be moving to NewClass from OldClass
// - The StoreCount of OldClass and NewClass is expected to have been updated
// for I already if it is is a store.
// for I already if it is a store.
// - The OldClass memory leader has not been updated yet if I was the leader.
void NewGVN::moveMemoryToNewCongruenceClass(Instruction *I,
MemoryAccess *InstMA,