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[mips] Add support for branch-likely pseudo-instructions
Differential Revision: http://reviews.llvm.org/D10537 llvm-svn: 247697
This commit is contained in:
Zoran Jovanovic
parent
3f6dcea99f
commit
b80aba8e8d
@ -1817,6 +1817,14 @@ bool MipsAsmParser::needsExpansion(MCInst &Inst) {
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case Mips::BLEU:
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case Mips::BGEU:
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case Mips::BGTU:
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case Mips::BLTL:
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case Mips::BLEL:
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case Mips::BGEL:
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case Mips::BGTL:
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case Mips::BLTUL:
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case Mips::BLEUL:
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case Mips::BGEUL:
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case Mips::BGTUL:
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case Mips::SDivMacro:
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case Mips::UDivMacro:
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case Mips::DSDivMacro:
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@ -1876,6 +1884,14 @@ bool MipsAsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc,
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case Mips::BLEU:
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case Mips::BGEU:
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case Mips::BGTU:
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case Mips::BLTL:
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case Mips::BLEL:
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case Mips::BGEL:
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case Mips::BGTL:
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case Mips::BLTUL:
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case Mips::BLEUL:
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case Mips::BGEUL:
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case Mips::BGTUL:
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return expandCondBranches(Inst, IDLoc, Instructions);
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case Mips::SDivMacro:
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return expandDiv(Inst, IDLoc, Instructions, false, true);
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@ -2568,38 +2584,50 @@ bool MipsAsmParser::expandCondBranches(MCInst &Inst, SMLoc IDLoc,
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const MCExpr *OffsetExpr = Inst.getOperand(2).getExpr();
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unsigned ZeroSrcOpcode, ZeroTrgOpcode;
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bool ReverseOrderSLT, IsUnsigned, AcceptsEquality;
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bool ReverseOrderSLT, IsUnsigned, IsLikely, AcceptsEquality;
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switch (PseudoOpcode) {
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case Mips::BLT:
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case Mips::BLTU:
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case Mips::BLTL:
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case Mips::BLTUL:
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AcceptsEquality = false;
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ReverseOrderSLT = false;
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IsUnsigned = (PseudoOpcode == Mips::BLTU);
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IsUnsigned = ((PseudoOpcode == Mips::BLTU) || (PseudoOpcode == Mips::BLTUL));
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IsLikely = ((PseudoOpcode == Mips::BLTL) || (PseudoOpcode == Mips::BLTUL));
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ZeroSrcOpcode = Mips::BGTZ;
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ZeroTrgOpcode = Mips::BLTZ;
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break;
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case Mips::BLE:
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case Mips::BLEU:
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case Mips::BLEL:
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case Mips::BLEUL:
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AcceptsEquality = true;
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ReverseOrderSLT = true;
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IsUnsigned = (PseudoOpcode == Mips::BLEU);
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IsUnsigned = ((PseudoOpcode == Mips::BLEU) || (PseudoOpcode == Mips::BLEUL));
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IsLikely = ((PseudoOpcode == Mips::BLEL) || (PseudoOpcode == Mips::BLEUL));
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ZeroSrcOpcode = Mips::BGEZ;
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ZeroTrgOpcode = Mips::BLEZ;
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break;
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case Mips::BGE:
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case Mips::BGEU:
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case Mips::BGEL:
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case Mips::BGEUL:
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AcceptsEquality = true;
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ReverseOrderSLT = false;
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IsUnsigned = (PseudoOpcode == Mips::BGEU);
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IsUnsigned = ((PseudoOpcode == Mips::BGEU) || (PseudoOpcode == Mips::BGEUL));
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IsLikely = ((PseudoOpcode == Mips::BGEL) || (PseudoOpcode == Mips::BGEUL));
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ZeroSrcOpcode = Mips::BLEZ;
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ZeroTrgOpcode = Mips::BGEZ;
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break;
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case Mips::BGT:
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case Mips::BGTU:
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case Mips::BGTL:
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case Mips::BGTUL:
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AcceptsEquality = false;
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ReverseOrderSLT = true;
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IsUnsigned = (PseudoOpcode == Mips::BGTU);
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IsUnsigned = ((PseudoOpcode == Mips::BGTU) || (PseudoOpcode == Mips::BGTUL));
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IsLikely = ((PseudoOpcode == Mips::BGTL) || (PseudoOpcode == Mips::BGTUL));
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ZeroSrcOpcode = Mips::BLTZ;
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ZeroTrgOpcode = Mips::BGTZ;
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break;
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@ -2752,7 +2780,10 @@ bool MipsAsmParser::expandCondBranches(MCInst &Inst, SMLoc IDLoc,
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SetInst.addOperand(MCOperand::createReg(ReverseOrderSLT ? SrcReg : TrgReg));
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Instructions.push_back(SetInst);
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BranchInst.setOpcode(AcceptsEquality ? Mips::BEQ : Mips::BNE);
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if (!IsLikely)
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BranchInst.setOpcode(AcceptsEquality ? Mips::BEQ : Mips::BNE);
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else
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BranchInst.setOpcode(AcceptsEquality ? Mips::BEQL : Mips::BNEL);
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BranchInst.addOperand(MCOperand::createReg(ATRegNum));
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BranchInst.addOperand(MCOperand::createReg(Mips::ZERO));
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BranchInst.addOperand(MCOperand::createExpr(OffsetExpr));
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@ -899,5 +899,6 @@ def SRL16_MMR6 : StdMMR6Rel, SRL16_MMR6_DESC, SRL16_MMR6_ENC,
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def : MipsInstAlias<"ei", (EI_MMR6 ZERO), 1>, ISA_MICROMIPS32R6;
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def : MipsInstAlias<"nop", (SLL_MMR6 ZERO, ZERO, 0), 1>, ISA_MICROMIPS32R6;
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def B_MMR6_Pseudo : MipsAsmPseudoInst<(outs), (ins brtarget_mm:$offset),
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!strconcat("b", "\t$offset")>,
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MicroMipsR6Inst16;
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!strconcat("b", "\t$offset")> {
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string DecoderNamespace = "MicroMipsR6";
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}
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@ -132,7 +132,7 @@ class PseudoSE<dag outs, dag ins, list<dag> pattern,
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// These are aliases that require C++ handling to convert to the target
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// instruction, while InstAliases can be handled directly by tblgen.
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class MipsAsmPseudoInst<dag outs, dag ins, string asmstr>:
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MipsInst<outs, ins, asmstr, [], IIPseudo, Pseudo> {
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MipsInst<outs, ins, asmstr, [], IIPseudo, Pseudo>, PredicateControl {
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let isPseudo = 1;
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let Pattern = [];
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}
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@ -1757,24 +1757,38 @@ def BLTU : CondBranchPseudo<"bltu">;
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def BLEU : CondBranchPseudo<"bleu">;
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def BGEU : CondBranchPseudo<"bgeu">;
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def BGTU : CondBranchPseudo<"bgtu">;
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def BLTL : CondBranchPseudo<"bltl">, ISA_MIPS2_NOT_32R6_64R6;
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def BLEL : CondBranchPseudo<"blel">, ISA_MIPS2_NOT_32R6_64R6;
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def BGEL : CondBranchPseudo<"bgel">, ISA_MIPS2_NOT_32R6_64R6;
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def BGTL : CondBranchPseudo<"bgtl">, ISA_MIPS2_NOT_32R6_64R6;
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def BLTUL: CondBranchPseudo<"bltul">, ISA_MIPS2_NOT_32R6_64R6;
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def BLEUL: CondBranchPseudo<"bleul">, ISA_MIPS2_NOT_32R6_64R6;
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def BGEUL: CondBranchPseudo<"bgeul">, ISA_MIPS2_NOT_32R6_64R6;
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def BGTUL: CondBranchPseudo<"bgtul">, ISA_MIPS2_NOT_32R6_64R6;
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// FIXME: Predicates are removed because instructions are matched regardless of
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// predicates, because PredicateControl was not in the hierarchy. This was
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// done to emit more precise error message from expansion function.
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// Once the tablegen-erated errors are made better, this needs to be fixed and
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// predicates needs to be restored.
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def SDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
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"div\t$rs, $rt">, ISA_MIPS1_NOT_32R6_64R6;
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"div\t$rs, $rt">; //, ISA_MIPS1_NOT_32R6_64R6;
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def UDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
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"divu\t$rs, $rt">, ISA_MIPS1_NOT_32R6_64R6;
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"divu\t$rs, $rt">; //, ISA_MIPS1_NOT_32R6_64R6;
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def DSDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
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"ddiv\t$rs, $rt">, ISA_MIPS64_NOT_64R6;
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"ddiv\t$rs, $rt">; //, ISA_MIPS64_NOT_64R6;
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def DUDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
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"ddivu\t$rs, $rt">, ISA_MIPS64_NOT_64R6;
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"ddivu\t$rs, $rt">; //, ISA_MIPS64_NOT_64R6;
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def Ulhu : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr),
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"ulhu\t$rt, $addr">, ISA_MIPS1_NOT_32R6_64R6;
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"ulhu\t$rt, $addr">; //, ISA_MIPS1_NOT_32R6_64R6;
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def Ulw : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr),
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"ulw\t$rt, $addr">, ISA_MIPS1_NOT_32R6_64R6;
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"ulw\t$rt, $addr">; //, ISA_MIPS1_NOT_32R6_64R6;
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//===----------------------------------------------------------------------===//
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// Arbitrary patterns that map to one or more instructions
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@ -19,3 +19,20 @@ local_label:
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# CHECK: :[[@LINE-1]]:3: error: pseudo-instruction requires $at, which is not available
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bgtu $7, $8, local_label
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# CHECK: :[[@LINE-1]]:3: error: pseudo-instruction requires $at, which is not available
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bltl $7, $8, local_label
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# CHECK: :[[@LINE-1]]:3: error: pseudo-instruction requires $at, which is not available
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bltul $7, $8, local_label
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# CHECK: :[[@LINE-1]]:3: error: pseudo-instruction requires $at, which is not available
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blel $7, $8, local_label
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# CHECK: :[[@LINE-1]]:3: error: pseudo-instruction requires $at, which is not available
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bleul $7, $8, local_label
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# CHECK: :[[@LINE-1]]:3: error: pseudo-instruction requires $at, which is not available
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bgel $7, $8, local_label
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# CHECK: :[[@LINE-1]]:3: error: pseudo-instruction requires $at, which is not available
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bgeul $7, $8, local_label
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# CHECK: :[[@LINE-1]]:3: error: pseudo-instruction requires $at, which is not available
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bgtl $7, $8, local_label
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# CHECK: :[[@LINE-1]]:3: error: pseudo-instruction requires $at, which is not available
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bgtul $7, $8, local_label
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# CHECK: :[[@LINE-1]]:3: error: pseudo-instruction requires $at, which is not available
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@ -187,3 +187,183 @@ local_label:
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# CHECK: bnez $zero, local_label # encoding: [0x14,0x00,A,A]
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# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16
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# CHECK: nop
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bltl $7,$8,local_label
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# CHECK: slt $1, $7, $8 # encoding: [0x00,0xe8,0x08,0x2a]
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# CHECK: bnel $1, $zero, local_label # encoding: [0x54,0x20,A,A]
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# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16
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# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
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bltl $7,$8,global_label
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# CHECK: slt $1, $7, $8 # encoding: [0x00,0xe8,0x08,0x2a]
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# CHECK: bnel $1, $zero, global_label # encoding: [0x54,0x20,A,A]
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# CHECK: # fixup A - offset: 0, value: global_label-4, kind: fixup_Mips_PC16
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# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
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bltl $7,$0,local_label
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# CHECK: bltz $7, local_label # encoding: [0x04,0xe0,A,A]
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# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16
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# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
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bltl $0,$8,local_label
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# CHECK: bgtz $8, local_label # encoding: [0x1d,0x00,A,A]
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# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16
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# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
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bltl $0,$0,local_label
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# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
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blel $7,$8,local_label
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# CHECK: slt $1, $8, $7 # encoding: [0x01,0x07,0x08,0x2a]
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# CHECK: beql $1, $zero, local_label # encoding: [0x50,0x20,A,A]
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# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16
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# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
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blel $7,$8,global_label
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# CHECK: slt $1, $8, $7 # encoding: [0x01,0x07,0x08,0x2a]
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# CHECK: beql $1, $zero, global_label # encoding: [0x50,0x20,A,A]
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# CHECK: # fixup A - offset: 0, value: global_label-4, kind: fixup_Mips_PC16
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# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
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blel $7,$0,local_label
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# CHECK: blez $7, local_label # encoding: [0x18,0xe0,A,A]
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# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16
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# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
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blel $0,$8,local_label
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# CHECK: bgez $8, local_label # encoding: [0x05,0x01,A,A]
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# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16
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# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
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blel $0,$0,local_label
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# WARNING: :[[@LINE-1]]:3: warning: branch is always taken
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# CHECK: b local_label # encoding: [0x10,0x00,A,A]
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# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16
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# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
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bgel $7,$8,local_label
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# CHECK: slt $1, $7, $8 # encoding: [0x00,0xe8,0x08,0x2a]
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# CHECK: beql $1, $zero, local_label # encoding: [0x50,0x20,A,A]
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# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16
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# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
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bgel $7,$8,global_label
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# CHECK: slt $1, $7, $8 # encoding: [0x00,0xe8,0x08,0x2a]
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# CHECK: beql $1, $zero, global_label # encoding: [0x50,0x20,A,A]
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# CHECK: # fixup A - offset: 0, value: global_label-4, kind: fixup_Mips_PC16
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# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
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bgel $7,$0,local_label
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# CHECK: bgez $7, local_label # encoding: [0x04,0xe1,A,A]
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# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16
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# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
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bgel $0,$8,local_label
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# CHECK: blez $8, local_label # encoding: [0x19,0x00,A,A]
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# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16
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# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
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bgel $0,$0,local_label
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# WARNING: :[[@LINE-1]]:3: warning: branch is always taken
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# CHECK: b local_label # encoding: [0x10,0x00,A,A]
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# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16
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# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
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bgtl $7,$8,local_label
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# CHECK: slt $1, $8, $7 # encoding: [0x01,0x07,0x08,0x2a]
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# CHECK: bnel $1, $zero, local_label # encoding: [0x54,0x20,A,A]
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# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16
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# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
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bgtl $7,$8,global_label
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# CHECK: slt $1, $8, $7 # encoding: [0x01,0x07,0x08,0x2a]
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# CHECK: bnel $1, $zero, global_label # encoding: [0x54,0x20,A,A]
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# CHECK: # fixup A - offset: 0, value: global_label-4, kind: fixup_Mips_PC16
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# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
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bgtl $7,$0,local_label
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# CHECK: bgtz $7, local_label # encoding: [0x1c,0xe0,A,A]
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# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16
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# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
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bgtl $0,$8,local_label
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# CHECK: bltz $8, local_label # encoding: [0x05,0x00,A,A]
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# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16
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# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
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bgtl $0,$0,local_label
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# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
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bltul $7,$8,local_label
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# CHECK: sltu $1, $7, $8 # encoding: [0x00,0xe8,0x08,0x2b]
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# CHECK: bnel $1, $zero, local_label # encoding: [0x54,0x20,A,A]
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# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16
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# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
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bltul $7,$8,global_label
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# CHECK: sltu $1, $7, $8 # encoding: [0x00,0xe8,0x08,0x2b]
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# CHECK: bnel $1, $zero, global_label # encoding: [0x54,0x20,A,A]
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# CHECK: # fixup A - offset: 0, value: global_label-4, kind: fixup_Mips_PC16
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# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
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bltul $7,$0,local_label
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# CHECK: bnez $7, local_label # encoding: [0x14,0xe0,A,A]
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# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16
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# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
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bltul $0,$8,local_label
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# CHECK: bnez $8, local_label # encoding: [0x15,0x00,A,A]
|
||||
# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16
|
||||
# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
|
||||
bltul $0,$0,local_label
|
||||
# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
|
||||
|
||||
bleul $7,$8,local_label
|
||||
# CHECK: sltu $1, $8, $7 # encoding: [0x01,0x07,0x08,0x2b]
|
||||
# CHECK: beql $1, $zero, local_label # encoding: [0x50,0x20,A,A]
|
||||
# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16
|
||||
# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
|
||||
bleul $7,$8,global_label
|
||||
# CHECK: sltu $1, $8, $7 # encoding: [0x01,0x07,0x08,0x2b]
|
||||
# CHECK: beql $1, $zero, global_label # encoding: [0x50,0x20,A,A]
|
||||
# CHECK: # fixup A - offset: 0, value: global_label-4, kind: fixup_Mips_PC16
|
||||
# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
|
||||
bleul $7,$0,local_label
|
||||
# CHECK: beqz $7, local_label # encoding: [0x10,0xe0,A,A]
|
||||
# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16
|
||||
# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
|
||||
bleul $0,$8,local_label
|
||||
# CHECK: beqz $8, local_label # encoding: [0x11,0x00,A,A]
|
||||
# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16
|
||||
# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
|
||||
bleul $0,$0,local_label
|
||||
# WARNING: :[[@LINE-1]]:3: warning: branch is always taken
|
||||
# CHECK: b local_label # encoding: [0x10,0x00,A,A]
|
||||
# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16
|
||||
# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
|
||||
|
||||
bgeul $7,$8,local_label
|
||||
# CHECK: sltu $1, $7, $8 # encoding: [0x00,0xe8,0x08,0x2b]
|
||||
# CHECK: beql $1, $zero, local_label # encoding: [0x50,0x20,A,A]
|
||||
# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16
|
||||
# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
|
||||
bgeul $7,$8,global_label
|
||||
# CHECK: sltu $1, $7, $8 # encoding: [0x00,0xe8,0x08,0x2b]
|
||||
# CHECK: beql $1, $zero, global_label # encoding: [0x50,0x20,A,A]
|
||||
# CHECK: # fixup A - offset: 0, value: global_label-4, kind: fixup_Mips_PC16
|
||||
# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
|
||||
bgeul $7,$0,local_label
|
||||
# CHECK: beqz $7, local_label # encoding: [0x10,0xe0,A,A]
|
||||
# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16
|
||||
# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
|
||||
bgeul $0,$8,local_label
|
||||
# CHECK: beqz $8, local_label # encoding: [0x11,0x00,A,A]
|
||||
# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16
|
||||
# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
|
||||
bgeul $0,$0,local_label
|
||||
# WARNING: :[[@LINE-1]]:3: warning: branch is always taken
|
||||
# CHECK: b local_label # encoding: [0x10,0x00,A,A]
|
||||
# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16
|
||||
# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
|
||||
|
||||
bgtul $7,$8,local_label
|
||||
# CHECK: sltu $1, $8, $7 # encoding: [0x01,0x07,0x08,0x2b]
|
||||
# CHECK: bnel $1, $zero, local_label # encoding: [0x54,0x20,A,A]
|
||||
# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16
|
||||
# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
|
||||
bgtul $7,$8,global_label
|
||||
# CHECK: sltu $1, $8, $7 # encoding: [0x01,0x07,0x08,0x2b]
|
||||
# CHECK: bnel $1, $zero, global_label # encoding: [0x54,0x20,A,A]
|
||||
# CHECK: # fixup A - offset: 0, value: global_label-4, kind: fixup_Mips_PC16
|
||||
# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
|
||||
bgtul $7,$0,local_label
|
||||
# CHECK: bnez $7, local_label # encoding: [0x14,0xe0,A,A]
|
||||
# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16
|
||||
# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
|
||||
bgtul $0,$8,local_label
|
||||
# CHECK: bnez $8, local_label # encoding: [0x15,0x00,A,A]
|
||||
# CHECK: # fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16
|
||||
# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
|
||||
bgtul $0,$0,local_label
|
||||
# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
|
||||
|
||||
@ -2,17 +2,27 @@
|
||||
# the assembler (e.g. invalid set of operands or operand's restrictions not met).
|
||||
|
||||
# RUN: not llvm-mc %s -triple=mips-unknown-linux -mcpu=mips32r6 2>%t1
|
||||
# RUN: FileCheck %s < %t1 -check-prefix=ASM
|
||||
# RUN: FileCheck %s < %t1
|
||||
|
||||
.text
|
||||
local_label:
|
||||
.set noreorder
|
||||
.set noat
|
||||
jalr.hb $31 # ASM: :[[@LINE]]:9: error: source and destination must be different
|
||||
jalr.hb $31, $31 # ASM: :[[@LINE]]:9: error: source and destination must be different
|
||||
ldc2 $8,-21181($at) # ASM: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
sdc2 $20,23157($s2) # ASM: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
swc2 $25,24880($s0) # ASM: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
jalr.hb $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different
|
||||
jalr.hb $31, $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different
|
||||
ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
sdc2 $20,23157($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
swc2 $25,24880($s0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
break 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
break 1024, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
break 7, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
break 1024, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
// FIXME: Following tests are temporarely disabled, until "PredicateControl not in hierarchy" problem is resolved
|
||||
bltl $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
bltul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
blel $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
bleul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
bgel $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
bgeul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
bgtl $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
bgtul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
|
||||
@ -2,15 +2,25 @@
|
||||
# the assembler (e.g. invalid set of operands or operand's restrictions not met).
|
||||
|
||||
# RUN: not llvm-mc %s -triple=mips64-unknown-linux -mcpu=mips64r6 2>%t1
|
||||
# RUN: FileCheck %s < %t1 -check-prefix=ASM
|
||||
# RUN: FileCheck %s < %t1
|
||||
|
||||
.text
|
||||
local_label:
|
||||
.set noreorder
|
||||
.set noat
|
||||
jalr.hb $31 # ASM: :[[@LINE]]:9: error: source and destination must be different
|
||||
jalr.hb $31, $31 # ASM: :[[@LINE]]:9: error: source and destination must be different
|
||||
ldc2 $8,-21181($at) # ASM: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
jalr.hb $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different
|
||||
jalr.hb $31, $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different
|
||||
ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
break 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
break 1024, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
break 7, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
break 1024, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
// FIXME: Following tests are temporarely disabled, until "PredicateControl not in hierarchy" problem is resolved
|
||||
bltl $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
bltul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
blel $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
bleul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
bgel $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
bgeul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
bgtl $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
bgtul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
|
||||
Loading…
Reference in New Issue
Block a user