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Annotate shifts and rotates with SchedRW lists.

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llvm-svn: 177935
This commit is contained in:
Jakob Stoklund Olesen 2013-03-25 23:07:32 +00:00
parent 0b530854c0
commit b81c63e1a2
1 changed files with 37 additions and 17 deletions
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54
lib/Target/X86/X86InstrShiftRotate.td
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@ -15,7 +15,7 @@
let Defs = [EFLAGS] in { let Defs = [EFLAGS] in {
let Constraints = "$src1 = $dst" in { let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
let Uses = [CL] in { let Uses = [CL] in {
def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1), def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1),
"shl{b}\t{%cl, $dst|$dst, CL}", "shl{b}\t{%cl, $dst|$dst, CL}",
@ -62,9 +62,10 @@ def SHL64r1 : RI<0xD1, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
"shl{q}\t$dst", [], IIC_SR>; "shl{q}\t$dst", [], IIC_SR>;
} // hasSideEffects = 0 } // hasSideEffects = 0
} // isConvertibleToThreeAddress = 1 } // isConvertibleToThreeAddress = 1
} // Constraints = "$src = $dst" } // Constraints = "$src = $dst", SchedRW
let SchedRW = [WriteShiftLd, WriteRMW] in {
// FIXME: Why do we need an explicit "Uses = [CL]" when the instr has a pattern // FIXME: Why do we need an explicit "Uses = [CL]" when the instr has a pattern
// using CL? // using CL?
let Uses = [CL] in { let Uses = [CL] in {
@ -118,8 +119,9 @@ def SHL64m1 : RI<0xD1, MRM4m, (outs), (ins i64mem:$dst),
"shl{q}\t$dst", "shl{q}\t$dst",
[(store (shl (loadi64 addr:$dst), (i8 1)), addr:$dst)], [(store (shl (loadi64 addr:$dst), (i8 1)), addr:$dst)],
IIC_SR>; IIC_SR>;
} // SchedRW
let Constraints = "$src1 = $dst" in { let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
let Uses = [CL] in { let Uses = [CL] in {
def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src1), def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src1),
"shr{b}\t{%cl, $dst|$dst, CL}", "shr{b}\t{%cl, $dst|$dst, CL}",
@ -163,9 +165,10 @@ def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
def SHR64r1 : RI<0xD1, MRM5r, (outs GR64:$dst), (ins GR64:$src1), def SHR64r1 : RI<0xD1, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
"shr{q}\t$dst", "shr{q}\t$dst",
[(set GR64:$dst, (srl GR64:$src1, (i8 1)))], IIC_SR>; [(set GR64:$dst, (srl GR64:$src1, (i8 1)))], IIC_SR>;
} // Constraints = "$src = $dst" } // Constraints = "$src = $dst", SchedRW
let SchedRW = [WriteShiftLd, WriteRMW] in {
let Uses = [CL] in { let Uses = [CL] in {
def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst), def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
"shr{b}\t{%cl, $dst|$dst, CL}", "shr{b}\t{%cl, $dst|$dst, CL}",
@ -216,8 +219,9 @@ def SHR64m1 : RI<0xD1, MRM5m, (outs), (ins i64mem:$dst),
"shr{q}\t$dst", "shr{q}\t$dst",
[(store (srl (loadi64 addr:$dst), (i8 1)), addr:$dst)], [(store (srl (loadi64 addr:$dst), (i8 1)), addr:$dst)],
IIC_SR>; IIC_SR>;
} // SchedRW
let Constraints = "$src1 = $dst" in { let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
let Uses = [CL] in { let Uses = [CL] in {
def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1), def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
"sar{b}\t{%cl, $dst|$dst, CL}", "sar{b}\t{%cl, $dst|$dst, CL}",
@ -273,9 +277,10 @@ def SAR64r1 : RI<0xD1, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
"sar{q}\t$dst", "sar{q}\t$dst",
[(set GR64:$dst, (sra GR64:$src1, (i8 1)))], [(set GR64:$dst, (sra GR64:$src1, (i8 1)))],
IIC_SR>; IIC_SR>;
} // Constraints = "$src = $dst" } // Constraints = "$src = $dst", SchedRW
let SchedRW = [WriteShiftLd, WriteRMW] in {
let Uses = [CL] in { let Uses = [CL] in {
def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst), def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
"sar{b}\t{%cl, $dst|$dst, CL}", "sar{b}\t{%cl, $dst|$dst, CL}",
@ -330,13 +335,14 @@ def SAR64m1 : RI<0xD1, MRM7m, (outs), (ins i64mem:$dst),
"sar{q}\t$dst", "sar{q}\t$dst",
[(store (sra (loadi64 addr:$dst), (i8 1)), addr:$dst)], [(store (sra (loadi64 addr:$dst), (i8 1)), addr:$dst)],
IIC_SR>; IIC_SR>;
} // SchedRW
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Rotate instructions // Rotate instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
let hasSideEffects = 0 in { let hasSideEffects = 0 in {
let Constraints = "$src1 = $dst" in { let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
def RCL8r1 : I<0xD0, MRM2r, (outs GR8:$dst), (ins GR8:$src1), def RCL8r1 : I<0xD0, MRM2r, (outs GR8:$dst), (ins GR8:$src1),
"rcl{b}\t$dst", [], IIC_SR>; "rcl{b}\t$dst", [], IIC_SR>;
def RCL8ri : Ii8<0xC0, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$cnt), def RCL8ri : Ii8<0xC0, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$cnt),
@ -405,6 +411,7 @@ def RCR64rCL : RI<0xD3, MRM3r, (outs GR64:$dst), (ins GR64:$src1),
} // Constraints = "$src = $dst" } // Constraints = "$src = $dst"
let SchedRW = [WriteShiftLd, WriteRMW] in {
def RCL8m1 : I<0xD0, MRM2m, (outs), (ins i8mem:$dst), def RCL8m1 : I<0xD0, MRM2m, (outs), (ins i8mem:$dst),
"rcl{b}\t$dst", [], IIC_SR>; "rcl{b}\t$dst", [], IIC_SR>;
def RCL8mi : Ii8<0xC0, MRM2m, (outs), (ins i8mem:$dst, i8imm:$cnt), def RCL8mi : Ii8<0xC0, MRM2m, (outs), (ins i8mem:$dst, i8imm:$cnt),
@ -458,9 +465,10 @@ def RCR32mCL : I<0xD3, MRM3m, (outs), (ins i32mem:$dst),
def RCR64mCL : RI<0xD3, MRM3m, (outs), (ins i64mem:$dst), def RCR64mCL : RI<0xD3, MRM3m, (outs), (ins i64mem:$dst),
"rcr{q}\t{%cl, $dst|$dst, CL}", [], IIC_SR>; "rcr{q}\t{%cl, $dst|$dst, CL}", [], IIC_SR>;
} }
} // SchedRW
} // hasSideEffects = 0 } // hasSideEffects = 0
let Constraints = "$src1 = $dst" in { let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
// FIXME: provide shorter instructions when imm8 == 1 // FIXME: provide shorter instructions when imm8 == 1
let Uses = [CL] in { let Uses = [CL] in {
def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1), def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
@ -512,8 +520,9 @@ def ROL64r1 : RI<0xD1, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
"rol{q}\t$dst", "rol{q}\t$dst",
[(set GR64:$dst, (rotl GR64:$src1, (i8 1)))], [(set GR64:$dst, (rotl GR64:$src1, (i8 1)))],
IIC_SR>; IIC_SR>;
} // Constraints = "$src = $dst" } // Constraints = "$src = $dst", SchedRW
let SchedRW = [WriteShiftLd, WriteRMW] in {
let Uses = [CL] in { let Uses = [CL] in {
def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst), def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
"rol{b}\t{%cl, $dst|$dst, CL}", "rol{b}\t{%cl, $dst|$dst, CL}",
@ -568,8 +577,9 @@ def ROL64m1 : RI<0xD1, MRM0m, (outs), (ins i64mem:$dst),
"rol{q}\t$dst", "rol{q}\t$dst",
[(store (rotl (loadi64 addr:$dst), (i8 1)), addr:$dst)], [(store (rotl (loadi64 addr:$dst), (i8 1)), addr:$dst)],
IIC_SR>; IIC_SR>;
} // SchedRW
let Constraints = "$src1 = $dst" in { let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
let Uses = [CL] in { let Uses = [CL] in {
def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1), def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
"ror{b}\t{%cl, $dst|$dst, CL}", "ror{b}\t{%cl, $dst|$dst, CL}",
@ -620,8 +630,9 @@ def ROR64r1 : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
"ror{q}\t$dst", "ror{q}\t$dst",
[(set GR64:$dst, (rotr GR64:$src1, (i8 1)))], [(set GR64:$dst, (rotr GR64:$src1, (i8 1)))],
IIC_SR>; IIC_SR>;
} // Constraints = "$src = $dst" } // Constraints = "$src = $dst", SchedRW
let SchedRW = [WriteShiftLd, WriteRMW] in {
let Uses = [CL] in { let Uses = [CL] in {
def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst), def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
"ror{b}\t{%cl, $dst|$dst, CL}", "ror{b}\t{%cl, $dst|$dst, CL}",
@ -676,13 +687,14 @@ def ROR64m1 : RI<0xD1, MRM1m, (outs), (ins i64mem:$dst),
"ror{q}\t$dst", "ror{q}\t$dst",
[(store (rotr (loadi64 addr:$dst), (i8 1)), addr:$dst)], [(store (rotr (loadi64 addr:$dst), (i8 1)), addr:$dst)],
IIC_SR>; IIC_SR>;
} // SchedRW
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Double shift instructions (generalizations of rotate) // Double shift instructions (generalizations of rotate)
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
let Constraints = "$src1 = $dst" in { let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
let Uses = [CL] in { let Uses = [CL] in {
def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst), def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst),
@ -765,8 +777,9 @@ def SHRD64rri8 : RIi8<0xAC, MRMDestReg,
(i8 imm:$src3)))], IIC_SHD64_REG_IM>, (i8 imm:$src3)))], IIC_SHD64_REG_IM>,
TB; TB;
} }
} // Constraints = "$src = $dst" } // Constraints = "$src = $dst", SchedRW
let SchedRW = [WriteShiftLd, WriteRMW] in {
let Uses = [CL] in { let Uses = [CL] in {
def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
"shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}", "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
@ -840,6 +853,7 @@ def SHRD64mri8 : RIi8<0xAC, MRMDestMem,
(i8 imm:$src3)), addr:$dst)], (i8 imm:$src3)), addr:$dst)],
IIC_SHD64_MEM_IM>, IIC_SHD64_MEM_IM>,
TB; TB;
} // SchedRW
} // Defs = [EFLAGS] } // Defs = [EFLAGS]
@ -857,12 +871,12 @@ multiclass bmi_rotate<string asm, RegisterClass RC, X86MemOperand x86memop> {
let neverHasSideEffects = 1 in { let neverHasSideEffects = 1 in {
def ri : Ii8<0xF0, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, i8imm:$src2), def ri : Ii8<0xF0, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, i8imm:$src2),
!strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
[]>, TAXD, VEX; []>, TAXD, VEX, Sched<[WriteShift]>;
let mayLoad = 1 in let mayLoad = 1 in
def mi : Ii8<0xF0, MRMSrcMem, (outs RC:$dst), def mi : Ii8<0xF0, MRMSrcMem, (outs RC:$dst),
(ins x86memop:$src1, i8imm:$src2), (ins x86memop:$src1, i8imm:$src2),
!strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
[]>, TAXD, VEX; []>, TAXD, VEX, Sched<[WriteShiftLd]>;
} }
} }
@ -870,11 +884,17 @@ multiclass bmi_shift<string asm, RegisterClass RC, X86MemOperand x86memop> {
let neverHasSideEffects = 1 in { let neverHasSideEffects = 1 in {
def rr : I<0xF7, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2), def rr : I<0xF7, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
!strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
VEX_4VOp3; VEX_4VOp3, Sched<[WriteShift]>;
let mayLoad = 1 in let mayLoad = 1 in
def rm : I<0xF7, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1, RC:$src2), def rm : I<0xF7, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1, RC:$src2),
!strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
VEX_4VOp3; VEX_4VOp3,
Sched<[WriteShiftLd,
// x86memop:$src1
ReadDefault, ReadDefault, ReadDefault, ReadDefault,
ReadDefault,
// RC:$src1
ReadAfterLd]>;
} }
} }