From b85740bf76204ff05cf1809aa0d88769c5df7a9f Mon Sep 17 00:00:00 2001
From: Anton Korobeynikov <asl@math.spbu.ru>
Date: Sun, 3 May 2009 12:59:16 +0000
Subject: [PATCH] Fix register names, fix register allocation order, handle
 frame pointer.

llvm-svn: 70701
---
 lib/Target/MSP430/MSP430RegisterInfo.cpp |  2 ++
 lib/Target/MSP430/MSP430RegisterInfo.td  | 30 +++++++++++++++---------
 2 files changed, 21 insertions(+), 11 deletions(-)

diff --git a/lib/Target/MSP430/MSP430RegisterInfo.cpp b/lib/Target/MSP430/MSP430RegisterInfo.cpp
index e69f9bc9c14..1b9fc67db6d 100644
--- a/lib/Target/MSP430/MSP430RegisterInfo.cpp
+++ b/lib/Target/MSP430/MSP430RegisterInfo.cpp
@@ -15,6 +15,8 @@
 
 #include "MSP430.h"
 #include "MSP430RegisterInfo.h"
+#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/Target/TargetMachine.h"
 #include "llvm/ADT/BitVector.h"
 
 using namespace llvm;
diff --git a/lib/Target/MSP430/MSP430RegisterInfo.td b/lib/Target/MSP430/MSP430RegisterInfo.td
index 2793fdc7db9..27a9842cfa2 100644
--- a/lib/Target/MSP430/MSP430RegisterInfo.td
+++ b/lib/Target/MSP430/MSP430RegisterInfo.td
@@ -20,11 +20,11 @@ class MSP430Reg<bits<4> num, string n> : Register<n> {
 //  Registers
 //===----------------------------------------------------------------------===//
 
-def PC  : MSP430Reg<0,  "PC">;
-def SP  : MSP430Reg<1,  "SP">;
-def SR  : MSP430Reg<2,  "SR">;
-def CG  : MSP430Reg<3,  "CG">;
-def R4  : MSP430Reg<4,  "R4">;
+def PC  : MSP430Reg<0,  "R0">;
+def SP  : MSP430Reg<1,  "R1">;
+def SR  : MSP430Reg<2,  "R2">;
+def CG  : MSP430Reg<3,  "R3">;
+def FP  : MSP430Reg<4,  "R4">;
 def R5  : MSP430Reg<5,  "R5">;
 def R6  : MSP430Reg<6,  "R6">;
 def R7  : MSP430Reg<7,  "R7">;
@@ -38,10 +38,12 @@ def R14 : MSP430Reg<14, "R14">;
 def R15 : MSP430Reg<15, "R15">;
 
 def MSP430Regs : RegisterClass<"MSP430", [i16], 16,
-  // Volatile registers
-  [R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15,
-  // Volatile, but not allocable
-  PC, SP, SR, CG]>
+   // Volatile registers
+  [R12, R13, R14, R15, R11, R10, R9, R8, R7, R6, R5,
+   // Frame pointer, sometimes allocable
+   FP,
+   // Volatile, but not allocable
+   PC, SP, SR, CG]>
 {
   let MethodProtos = [{
     iterator allocation_order_end(const MachineFunction &MF) const;
@@ -49,8 +51,14 @@ def MSP430Regs : RegisterClass<"MSP430", [i16], 16,
   let MethodBodies = [{
     MSP430RegsClass::iterator
     MSP430RegsClass::allocation_order_end(const MachineFunction &MF) const {
-      // The last 4 registers on the list above are reserved
-      return end()-4;
+      const TargetMachine &TM = MF.getTarget();
+      const TargetRegisterInfo *RI = TM.getRegisterInfo();
+      // Depending on whether the function uses frame pointer or not, last 5 or 4
+      // registers on the list above are reserved
+      if (RI->hasFP(MF))
+        return end()-5;
+      else
+        return end()-4;
     }
   }];
 }