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Fix an obvious bug in isMoveInstr. It needs to return sub-register indices.
llvm-svn: 103157
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parent
f25111f27f
commit
b877797172
@ -540,8 +540,6 @@ bool
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ARMBaseInstrInfo::isMoveInstr(const MachineInstr &MI,
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ARMBaseInstrInfo::isMoveInstr(const MachineInstr &MI,
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unsigned &SrcReg, unsigned &DstReg,
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unsigned &SrcReg, unsigned &DstReg,
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unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
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unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
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SrcSubIdx = DstSubIdx = 0; // No sub-registers.
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switch (MI.getOpcode()) {
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switch (MI.getOpcode()) {
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default: break;
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default: break;
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case ARM::VMOVS:
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case ARM::VMOVS:
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@ -551,6 +549,8 @@ ARMBaseInstrInfo::isMoveInstr(const MachineInstr &MI,
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case ARM::VMOVQQ : {
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case ARM::VMOVQQ : {
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SrcReg = MI.getOperand(1).getReg();
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SrcReg = MI.getOperand(1).getReg();
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DstReg = MI.getOperand(0).getReg();
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DstReg = MI.getOperand(0).getReg();
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SrcSubIdx = MI.getOperand(1).getSubReg();
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DstSubIdx = MI.getOperand(0).getSubReg();
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return true;
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return true;
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}
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}
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case ARM::MOVr:
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case ARM::MOVr:
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@ -565,6 +565,8 @@ ARMBaseInstrInfo::isMoveInstr(const MachineInstr &MI,
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"Invalid ARM MOV instruction");
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"Invalid ARM MOV instruction");
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SrcReg = MI.getOperand(1).getReg();
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SrcReg = MI.getOperand(1).getReg();
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DstReg = MI.getOperand(0).getReg();
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DstReg = MI.getOperand(0).getReg();
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SrcSubIdx = MI.getOperand(1).getSubReg();
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DstSubIdx = MI.getOperand(0).getSubReg();
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return true;
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return true;
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}
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}
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}
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}
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