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[CodeGen][X86] Remove some unused check-prefixes and regenerate tests.

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This commit is contained in:
Wang, Pengfei 2020-11-17 10:17:07 +08:00
parent 334e9d743f
commit b88a7192bd
8 changed files with 79 additions and 89 deletions
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6
test/CodeGen/X86/GlobalISel/legalize-sub-v128.mir
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@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+sse2 -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=SSE2
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+sse2 -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL
--- |
define void @test_sub_v16i8() {
@ -39,6 +39,7 @@ body: |
; ALL: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
; ALL: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
; ALL: [[SUB:%[0-9]+]]:_(<16 x s8>) = G_SUB [[DEF]], [[DEF1]]
; ALL: $xmm0 = COPY [[SUB]](<16 x s8>)
; ALL: RET 0
%0(<16 x s8>) = IMPLICIT_DEF
%1(<16 x s8>) = IMPLICIT_DEF
@ -64,6 +65,7 @@ body: |
; ALL: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
; ALL: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
; ALL: [[SUB:%[0-9]+]]:_(<8 x s16>) = G_SUB [[DEF]], [[DEF1]]
; ALL: $xmm0 = COPY [[SUB]](<8 x s16>)
; ALL: RET 0
%0(<8 x s16>) = IMPLICIT_DEF
%1(<8 x s16>) = IMPLICIT_DEF
@ -89,6 +91,7 @@ body: |
; ALL: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
; ALL: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
; ALL: [[SUB:%[0-9]+]]:_(<4 x s32>) = G_SUB [[DEF]], [[DEF1]]
; ALL: $xmm0 = COPY [[SUB]](<4 x s32>)
; ALL: RET 0
%0(<4 x s32>) = IMPLICIT_DEF
%1(<4 x s32>) = IMPLICIT_DEF
@ -114,6 +117,7 @@ body: |
; ALL: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
; ALL: [[DEF1:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
; ALL: [[SUB:%[0-9]+]]:_(<2 x s64>) = G_SUB [[DEF]], [[DEF1]]
; ALL: $xmm0 = COPY [[SUB]](<2 x s64>)
; ALL: RET 0
%0(<2 x s64>) = IMPLICIT_DEF
%1(<2 x s64>) = IMPLICIT_DEF

6
test/CodeGen/X86/GlobalISel/legalize-sub-v256.mir
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@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx2 -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX2
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx2 -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL
# TODO: add tests for additional configuration after the legalization supported
--- |
define void @test_sub_v32i8() {
@ -40,6 +40,7 @@ body: |
; ALL: [[DEF:%[0-9]+]]:_(<32 x s8>) = IMPLICIT_DEF
; ALL: [[DEF1:%[0-9]+]]:_(<32 x s8>) = IMPLICIT_DEF
; ALL: [[SUB:%[0-9]+]]:_(<32 x s8>) = G_SUB [[DEF]], [[DEF1]]
; ALL: $ymm0 = COPY [[SUB]](<32 x s8>)
; ALL: RET 0
%0(<32 x s8>) = IMPLICIT_DEF
%1(<32 x s8>) = IMPLICIT_DEF
@ -65,6 +66,7 @@ body: |
; ALL: [[DEF:%[0-9]+]]:_(<16 x s16>) = IMPLICIT_DEF
; ALL: [[DEF1:%[0-9]+]]:_(<16 x s16>) = IMPLICIT_DEF
; ALL: [[SUB:%[0-9]+]]:_(<16 x s16>) = G_SUB [[DEF]], [[DEF1]]
; ALL: $ymm0 = COPY [[SUB]](<16 x s16>)
; ALL: RET 0
%0(<16 x s16>) = IMPLICIT_DEF
%1(<16 x s16>) = IMPLICIT_DEF
@ -90,6 +92,7 @@ body: |
; ALL: [[DEF:%[0-9]+]]:_(<8 x s32>) = IMPLICIT_DEF
; ALL: [[DEF1:%[0-9]+]]:_(<8 x s32>) = IMPLICIT_DEF
; ALL: [[SUB:%[0-9]+]]:_(<8 x s32>) = G_SUB [[DEF]], [[DEF1]]
; ALL: $ymm0 = COPY [[SUB]](<8 x s32>)
; ALL: RET 0
%0(<8 x s32>) = IMPLICIT_DEF
%1(<8 x s32>) = IMPLICIT_DEF
@ -115,6 +118,7 @@ body: |
; ALL: [[DEF:%[0-9]+]]:_(<4 x s64>) = IMPLICIT_DEF
; ALL: [[DEF1:%[0-9]+]]:_(<4 x s64>) = IMPLICIT_DEF
; ALL: [[SUB:%[0-9]+]]:_(<4 x s64>) = G_SUB [[DEF]], [[DEF1]]
; ALL: $ymm0 = COPY [[SUB]](<4 x s64>)
; ALL: RET 0
%0(<4 x s64>) = IMPLICIT_DEF
%1(<4 x s64>) = IMPLICIT_DEF

6
test/CodeGen/X86/GlobalISel/legalize-sub-v512.mir
View File

@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f,+avx512bw -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX512BW
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f,+avx512bw -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL
# TODO: add tests for additional configuration after the legalization supported
--- |
define void @test_sub_v64i8() {
@ -40,6 +40,7 @@ body: |
; ALL: [[DEF:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF
; ALL: [[DEF1:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF
; ALL: [[SUB:%[0-9]+]]:_(<64 x s8>) = G_SUB [[DEF]], [[DEF1]]
; ALL: $zmm0 = COPY [[SUB]](<64 x s8>)
; ALL: RET 0
%0(<64 x s8>) = IMPLICIT_DEF
%1(<64 x s8>) = IMPLICIT_DEF
@ -65,6 +66,7 @@ body: |
; ALL: [[DEF:%[0-9]+]]:_(<32 x s16>) = IMPLICIT_DEF
; ALL: [[DEF1:%[0-9]+]]:_(<32 x s16>) = IMPLICIT_DEF
; ALL: [[SUB:%[0-9]+]]:_(<32 x s16>) = G_SUB [[DEF]], [[DEF1]]
; ALL: $zmm0 = COPY [[SUB]](<32 x s16>)
; ALL: RET 0
%0(<32 x s16>) = IMPLICIT_DEF
%1(<32 x s16>) = IMPLICIT_DEF
@ -90,6 +92,7 @@ body: |
; ALL: [[DEF:%[0-9]+]]:_(<16 x s32>) = IMPLICIT_DEF
; ALL: [[DEF1:%[0-9]+]]:_(<16 x s32>) = IMPLICIT_DEF
; ALL: [[SUB:%[0-9]+]]:_(<16 x s32>) = G_SUB [[DEF]], [[DEF1]]
; ALL: $zmm0 = COPY [[SUB]](<16 x s32>)
; ALL: RET 0
%0(<16 x s32>) = IMPLICIT_DEF
%1(<16 x s32>) = IMPLICIT_DEF
@ -115,6 +118,7 @@ body: |
; ALL: [[DEF:%[0-9]+]]:_(<8 x s64>) = IMPLICIT_DEF
; ALL: [[DEF1:%[0-9]+]]:_(<8 x s64>) = IMPLICIT_DEF
; ALL: [[SUB:%[0-9]+]]:_(<8 x s64>) = G_SUB [[DEF]], [[DEF1]]
; ALL: $zmm0 = COPY [[SUB]](<8 x s64>)
; ALL: RET 0
%0(<8 x s64>) = IMPLICIT_DEF
%1(<8 x s64>) = IMPLICIT_DEF

20
test/CodeGen/X86/fast-isel-nontemporal.ll
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@ -1,12 +1,12 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown -mattr=+mmx,+sse2 -fast-isel -O0 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE2
; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown -mattr=+mmx,+sse4a -fast-isel -O0 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE4A
; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown -mattr=+mmx,+sse4.1 -fast-isel -O0 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE41
; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown -mattr=+mmx,+avx -fast-isel -O0 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1
; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown -mattr=+mmx,+avx2 -fast-isel -O0 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2
; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown -mattr=+mmx,+avx512vl -fast-isel -O0 | FileCheck %s --check-prefix=ALL --check-prefix=AVX512 --check-prefix=AVX512VL
; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown -mattr=+mmx,+avx512f -fast-isel -O0 | FileCheck %s --check-prefix=ALL --check-prefix=AVX512 --check-prefix=AVX512F
; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown -mattr=+mmx,+avx512bw -fast-isel -O0 | FileCheck %s --check-prefix=ALL --check-prefix=AVX512 --check-prefix=AVX512BW
; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown -mattr=+mmx,+sse2 -fast-isel -O0 | FileCheck %s --check-prefixes=ALL,SSE,SSE2
; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown -mattr=+mmx,+sse4a -fast-isel -O0 | FileCheck %s --check-prefixes=ALL,SSE,SSE4A
; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown -mattr=+mmx,+sse4.1 -fast-isel -O0 | FileCheck %s --check-prefixes=ALL,SSE,SSE41
; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown -mattr=+mmx,+avx -fast-isel -O0 | FileCheck %s --check-prefixes=ALL,AVX,AVX1
; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown -mattr=+mmx,+avx2 -fast-isel -O0 | FileCheck %s --check-prefixes=ALL,AVX,AVX2
; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown -mattr=+mmx,+avx512vl -fast-isel -O0 | FileCheck %s --check-prefixes=ALL,AVX512
; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown -mattr=+mmx,+avx512f -fast-isel -O0 | FileCheck %s --check-prefixes=ALL,AVX512
; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown -mattr=+mmx,+avx512bw -fast-isel -O0 | FileCheck %s --check-prefixes=ALL,AVX512
;
; Scalar Stores
@ -889,12 +889,12 @@ define void @test_nt64xi8(<64 x i8>* nocapture %ptr, <64 x i8> %X) {
; AVX-NEXT: vzeroupper
; AVX-NEXT: retq
;
; AVX512-LABEL: test_nt64xi8:
; AVX512: # %bb.0: # %entry
; AVX512-NEXT: vmovntdq %zmm0, (%rdi)
; AVX512-NEXT: vzeroupper
; AVX512-NEXT: retq
entry:
store <64 x i8> %X, <64 x i8>* %ptr, align 64, !nontemporal !1
ret void
@ -916,12 +916,12 @@ define void @test_nt32xi16(<32 x i16>* nocapture %ptr, <32 x i16> %X) {
; AVX-NEXT: vzeroupper
; AVX-NEXT: retq
;
; AVX512-LABEL: test_nt32xi16:
; AVX512: # %bb.0: # %entry
; AVX512-NEXT: vmovntdq %zmm0, (%rdi)
; AVX512-NEXT: vzeroupper
; AVX512-NEXT: retq
entry:
store <32 x i16> %X, <32 x i16>* %ptr, align 64, !nontemporal !1
ret void

8
test/CodeGen/X86/mmx-fold-zero.ll
View File

@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+mmx,+sse2 | FileCheck %s --check-prefixes=CHECK,X86
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+mmx,+sse2 | FileCheck %s --check-prefixes=CHECK,X64
; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+mmx,+sse2 | FileCheck %s --check-prefix=X86
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+mmx,+sse2 | FileCheck %s --check-prefix=X64
define double @mmx_zero(double, double, double, double) nounwind {
; X86-LABEL: mmx_zero:
@ -49,7 +49,7 @@ define double @mmx_zero(double, double, double, double) nounwind {
; X64: # %bb.0:
; X64-NEXT: movdq2q %xmm0, %mm0
; X64-NEXT: movdq2q %xmm1, %mm5
; X64-NEXT: movq %mm5, -{{[0-9]+}}(%rsp) # 8-byte Spill
; X64-NEXT: movq %mm5, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; X64-NEXT: movq %mm0, %mm3
; X64-NEXT: paddd %mm5, %mm3
; X64-NEXT: pxor %mm1, %mm1
@ -73,7 +73,7 @@ define double @mmx_zero(double, double, double, double) nounwind {
; X64-NEXT: paddw {{\.LCPI.*}}, %mm0
; X64-NEXT: paddw %mm1, %mm0
; X64-NEXT: pmuludq %mm7, %mm0
; X64-NEXT: pmuludq -{{[0-9]+}}(%rsp), %mm0 # 8-byte Folded Reload
; X64-NEXT: pmuludq {{[-0-9]+}}(%r{{[sb]}}p), %mm0 # 8-byte Folded Reload
; X64-NEXT: paddw %mm5, %mm0
; X64-NEXT: paddw %mm2, %mm0
; X64-NEXT: movq2dq %mm0, %xmm0

20
test/CodeGen/X86/oddsubvector.ll
View File

@ -2,10 +2,10 @@
; RUN: llc < %s -mtriple=x86_64-pc-linux -mattr=+sse2 | FileCheck %s --check-prefixes=SSE,SSE2
; RUN: llc < %s -mtriple=x86_64-pc-linux -mattr=+sse4.2 | FileCheck %s --check-prefixes=SSE,SSE42
; RUN: llc < %s -mtriple=x86_64-pc-linux -mattr=+avx | FileCheck %s --check-prefixes=AVX,AVX1
; RUN: llc < %s -mtriple=x86_64-pc-linux -mattr=+avx2 | FileCheck %s --check-prefixes=AVX,AVX2,AVX2-SLOW
; RUN: llc < %s -mtriple=x86_64-pc-linux -mattr=+avx2,+fast-variable-shuffle | FileCheck %s --check-prefixes=AVX,AVX2,AVX2-FAST
; RUN: llc < %s -mtriple=x86_64-pc-linux -mattr=+avx512f | FileCheck %s --check-prefixes=AVX512,AVX512-SLOW
; RUN: llc < %s -mtriple=x86_64-pc-linux -mattr=+avx512f,+fast-variable-shuffle | FileCheck %s --check-prefixes=AVX512,AVX512-FAST
; RUN: llc < %s -mtriple=x86_64-pc-linux -mattr=+avx2 | FileCheck %s --check-prefixes=AVX,AVX2
; RUN: llc < %s -mtriple=x86_64-pc-linux -mattr=+avx2,+fast-variable-shuffle | FileCheck %s --check-prefixes=AVX,AVX2
; RUN: llc < %s -mtriple=x86_64-pc-linux -mattr=+avx512f | FileCheck %s --check-prefix=AVX512
; RUN: llc < %s -mtriple=x86_64-pc-linux -mattr=+avx512f,+fast-variable-shuffle | FileCheck %s --check-prefix=AVX512
; RUN: llc < %s -mtriple=x86_64-pc-linux -mattr=+xop | FileCheck %s --check-prefixes=AVX,XOP
define void @insert_v7i8_v2i16_2(<7 x i8> *%a0, <2 x i16> *%a1) nounwind {
@ -162,7 +162,7 @@ define void @PR42833() {
; SSE2-NEXT: movdqa c+{{.*}}(%rip), %xmm1
; SSE2-NEXT: movdqa c+{{.*}}(%rip), %xmm0
; SSE2-NEXT: movd %xmm0, %eax
; SSE2-NEXT: addl b(%rip), %eax
; SSE2-NEXT: addl {{.*}}(%rip), %eax
; SSE2-NEXT: movd %eax, %xmm2
; SSE2-NEXT: movd %eax, %xmm3
; SSE2-NEXT: paddd %xmm0, %xmm3
@ -198,7 +198,7 @@ define void @PR42833() {
; SSE42-NEXT: movdqa c+{{.*}}(%rip), %xmm0
; SSE42-NEXT: movdqa c+{{.*}}(%rip), %xmm1
; SSE42-NEXT: movd %xmm1, %eax
; SSE42-NEXT: addl b(%rip), %eax
; SSE42-NEXT: addl {{.*}}(%rip), %eax
; SSE42-NEXT: movd %eax, %xmm2
; SSE42-NEXT: paddd %xmm1, %xmm2
; SSE42-NEXT: movdqa d+{{.*}}(%rip), %xmm3
@ -232,7 +232,7 @@ define void @PR42833() {
; AVX1: # %bb.0:
; AVX1-NEXT: vmovdqa c+{{.*}}(%rip), %xmm0
; AVX1-NEXT: vmovd %xmm0, %eax
; AVX1-NEXT: addl b(%rip), %eax
; AVX1-NEXT: addl {{.*}}(%rip), %eax
; AVX1-NEXT: vmovd %eax, %xmm1
; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm1
; AVX1-NEXT: vpaddd %xmm0, %xmm0, %xmm2
@ -265,7 +265,7 @@ define void @PR42833() {
;
; AVX2-LABEL: PR42833:
; AVX2: # %bb.0:
; AVX2-NEXT: movl b(%rip), %eax
; AVX2-NEXT: movl {{.*}}(%rip), %eax
; AVX2-NEXT: vmovdqu c+{{.*}}(%rip), %ymm0
; AVX2-NEXT: addl c+{{.*}}(%rip), %eax
; AVX2-NEXT: vmovd %eax, %xmm1
@ -288,7 +288,7 @@ define void @PR42833() {
;
; AVX512-LABEL: PR42833:
; AVX512: # %bb.0:
; AVX512-NEXT: movl b(%rip), %eax
; AVX512-NEXT: movl {{.*}}(%rip), %eax
; AVX512-NEXT: vmovdqu c+{{.*}}(%rip), %ymm0
; AVX512-NEXT: vmovdqu64 c+{{.*}}(%rip), %zmm1
; AVX512-NEXT: addl c+{{.*}}(%rip), %eax
@ -314,7 +314,7 @@ define void @PR42833() {
; XOP: # %bb.0:
; XOP-NEXT: vmovdqa c+{{.*}}(%rip), %xmm0
; XOP-NEXT: vmovd %xmm0, %eax
; XOP-NEXT: addl b(%rip), %eax
; XOP-NEXT: addl {{.*}}(%rip), %eax
; XOP-NEXT: vmovd %eax, %xmm1
; XOP-NEXT: vpaddd %xmm1, %xmm0, %xmm1
; XOP-NEXT: vpaddd %xmm0, %xmm0, %xmm2

28
test/CodeGen/X86/pr32368.ll
View File

@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=CHECK --check-prefix=SSE
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=CHECK --check-prefix=AVX1
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=CHECK --check-prefix=AVX2
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefix=CHECK --check-prefix=AVX512
; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=SSE
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX1
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX2
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefix=AVX512
define <4 x float> @PR32368_128(<4 x float>) {
; SSE-LABEL: PR32368_128:
@ -21,19 +21,19 @@ define <4 x float> @PR32368_128(<4 x float>) {
;
; AVX2-LABEL: PR32368_128:
; AVX2: # %bb.0:
; AVX2-NEXT: vbroadcastss {{.*}}(%rip), %xmm1
; AVX2-NEXT: vbroadcastss {{.*#+}} xmm1 = [4294967004,4294967004,4294967004,4294967004]
; AVX2-NEXT: vandps %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vaddps %xmm0, %xmm0, %xmm0
; AVX2-NEXT: vbroadcastss {{.*}}(%rip), %xmm1
; AVX2-NEXT: vbroadcastss {{.*#+}} xmm1 = [291,291,291,291]
; AVX2-NEXT: vandps %xmm1, %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512-LABEL: PR32368_128:
; AVX512: # %bb.0:
; AVX512-NEXT: vbroadcastss {{.*}}(%rip), %xmm1
; AVX512-NEXT: vbroadcastss {{.*#+}} xmm1 = [4294967004,4294967004,4294967004,4294967004]
; AVX512-NEXT: vandps %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vaddps %xmm0, %xmm0, %xmm0
; AVX512-NEXT: vbroadcastss {{.*}}(%rip), %xmm1
; AVX512-NEXT: vbroadcastss {{.*#+}} xmm1 = [291,291,291,291]
; AVX512-NEXT: vandps %xmm1, %xmm0, %xmm0
; AVX512-NEXT: retq
%2 = bitcast <4 x float> %0 to <4 x i32>
@ -68,19 +68,19 @@ define <8 x float> @PR32368_256(<8 x float>) {
;
; AVX2-LABEL: PR32368_256:
; AVX2: # %bb.0:
; AVX2-NEXT: vbroadcastss {{.*}}(%rip), %ymm1
; AVX2-NEXT: vbroadcastss {{.*#+}} ymm1 = [4294967004,4294967004,4294967004,4294967004,4294967004,4294967004,4294967004,4294967004]
; AVX2-NEXT: vandps %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vaddps %ymm0, %ymm0, %ymm0
; AVX2-NEXT: vbroadcastss {{.*}}(%rip), %ymm1
; AVX2-NEXT: vbroadcastss {{.*#+}} ymm1 = [291,291,291,291,291,291,291,291]
; AVX2-NEXT: vandps %ymm1, %ymm0, %ymm0
; AVX2-NEXT: retq
;
; AVX512-LABEL: PR32368_256:
; AVX512: # %bb.0:
; AVX512-NEXT: vbroadcastss {{.*}}(%rip), %ymm1
; AVX512-NEXT: vbroadcastss {{.*#+}} ymm1 = [4294967004,4294967004,4294967004,4294967004,4294967004,4294967004,4294967004,4294967004]
; AVX512-NEXT: vandps %ymm1, %ymm0, %ymm0
; AVX512-NEXT: vaddps %ymm0, %ymm0, %ymm0
; AVX512-NEXT: vbroadcastss {{.*}}(%rip), %ymm1
; AVX512-NEXT: vbroadcastss {{.*#+}} ymm1 = [291,291,291,291,291,291,291,291]
; AVX512-NEXT: vandps %ymm1, %ymm0, %ymm0
; AVX512-NEXT: retq
%2 = bitcast <8 x float> %0 to <8 x i32>
@ -126,12 +126,12 @@ define <16 x float> @PR32368_512(<16 x float>) {
;
; AVX2-LABEL: PR32368_512:
; AVX2: # %bb.0:
; AVX2-NEXT: vbroadcastss {{.*}}(%rip), %ymm2
; AVX2-NEXT: vbroadcastss {{.*#+}} ymm2 = [4294967004,4294967004,4294967004,4294967004,4294967004,4294967004,4294967004,4294967004]
; AVX2-NEXT: vandps %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vandps %ymm2, %ymm1, %ymm1
; AVX2-NEXT: vaddps %ymm1, %ymm1, %ymm1
; AVX2-NEXT: vaddps %ymm0, %ymm0, %ymm0
; AVX2-NEXT: vbroadcastss {{.*}}(%rip), %ymm2
; AVX2-NEXT: vbroadcastss {{.*#+}} ymm2 = [291,291,291,291,291,291,291,291]
; AVX2-NEXT: vandps %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vandps %ymm2, %ymm1, %ymm1
; AVX2-NEXT: retq

74
test/CodeGen/X86/testb-je-fusion.ll
View File

@ -1,13 +1,13 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-- -mattr=-macrofusion,-branchfusion -post-RA-scheduler=0 | FileCheck %s --check-prefix=NOFUSION_NOPOSTRA
; RUN: llc < %s -mtriple=x86_64-- -mattr=-macrofusion,+branchfusion -post-RA-scheduler=0 | FileCheck %s --check-prefix=BRANCHFUSION_NOPOSTRA --check-prefix=BRANCHFUSIONONLY_NOPOSTRA
; RUN: llc < %s -mtriple=x86_64-- -mattr=+macrofusion,-branchfusion -post-RA-scheduler=0 | FileCheck %s --check-prefix=BRANCHFUSION_NOPOSTRA --check-prefix=MACROFUSION_NOPOSTRA
; RUN: llc < %s -mtriple=x86_64-- -mattr=-macrofusion,+branchfusion -post-RA-scheduler=0 | FileCheck %s --check-prefixes=BRANCHFUSION_NOPOSTRA,BRANCHFUSIONONLY_NOPOSTRA
; RUN: llc < %s -mtriple=x86_64-- -mattr=+macrofusion,-branchfusion -post-RA-scheduler=0 | FileCheck %s --check-prefixes=BRANCHFUSION_NOPOSTRA,MACROFUSION_NOPOSTRA
; RUN: llc < %s -mtriple=x86_64-- -mattr=-macrofusion,-branchfusion -post-RA-scheduler=1 | FileCheck %s --check-prefix=NOFUSION_POSTRA
; RUN: llc < %s -mtriple=x86_64-- -mattr=-macrofusion,+branchfusion -post-RA-scheduler=1 | FileCheck %s --check-prefix=BRANCHFUSION_POSTRA --check-prefix=BRANCHFUSIONONLY_POSTRA
; RUN: llc < %s -mtriple=x86_64-- -mattr=+macrofusion,-branchfusion -post-RA-scheduler=1 | FileCheck %s --check-prefix=BRANCHFUSION_POSTRA --check-prefix=MACROFUSION_POSTRA
; RUN: llc < %s -mtriple=x86_64-- -mattr=-macrofusion,+branchfusion -post-RA-scheduler=1 | FileCheck %s --check-prefix=BRANCHFUSION_POSTRA
; RUN: llc < %s -mtriple=x86_64-- -mattr=+macrofusion,-branchfusion -post-RA-scheduler=1 | FileCheck %s --check-prefix=BRANCHFUSION_POSTRA
; RUN: llc < %s -mtriple=x86_64-- -mattr=-macrofusion,-branchfusion -enable-misched=0 -misched-postra=1 -enable-post-misched | FileCheck %s --check-prefix=NOFUSION_MISCHEDPOSTRA
; RUN: llc < %s -mtriple=x86_64-- -mattr=-macrofusion,+branchfusion -enable-misched=0 -misched-postra=1 -enable-post-misched | FileCheck %s --check-prefix=BRANCHFUSION_MISCHEDPOSTRA --check-prefix=BRANCHFUSIONONLY_MISCHEDPOSTRA
; RUN: llc < %s -mtriple=x86_64-- -mattr=+macrofusion,-branchfusion -enable-misched=0 -misched-postra=1 -enable-post-misched | FileCheck %s --check-prefix=BRANCHFUSION_MISCHEDPOSTRA --check-prefix=MACROFUSION_MISCHEDPOSTRA
; RUN: llc < %s -mtriple=x86_64-- -mattr=-macrofusion,+branchfusion -enable-misched=0 -misched-postra=1 -enable-post-misched | FileCheck %s --check-prefix=BRANCHFUSION_MISCHEDPOSTRA
; RUN: llc < %s -mtriple=x86_64-- -mattr=+macrofusion,-branchfusion -enable-misched=0 -misched-postra=1 -enable-post-misched | FileCheck %s --check-prefix=BRANCHFUSION_MISCHEDPOSTRA
@ -246,27 +246,16 @@ define i32 @macrofuse_alu_je(i32 %flags, i8* %p) nounwind {
; NOFUSION_MISCHEDPOSTRA-NEXT: .LBB2_2: # %if.end
; NOFUSION_MISCHEDPOSTRA-NEXT: retq
;
; BRANCHFUSIONONLY_MISCHEDPOSTRA-LABEL: macrofuse_alu_je:
; BRANCHFUSIONONLY_MISCHEDPOSTRA: # %bb.0: # %entry
; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT: movl %edi, %eax
; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT: movb $1, (%rsi)
; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT: addl $-512, %eax # imm = 0xFE00
; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT: je .LBB2_2
; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT: # %bb.1: # %if.then
; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT: movl $1, %eax
; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT: .LBB2_2: # %if.end
; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT: retq
;
; MACROFUSION_MISCHEDPOSTRA-LABEL: macrofuse_alu_je:
; MACROFUSION_MISCHEDPOSTRA: # %bb.0: # %entry
; MACROFUSION_MISCHEDPOSTRA-NEXT: movl %edi, %eax
; MACROFUSION_MISCHEDPOSTRA-NEXT: movb $1, (%rsi)
; MACROFUSION_MISCHEDPOSTRA-NEXT: addl $-512, %eax # imm = 0xFE00
; MACROFUSION_MISCHEDPOSTRA-NEXT: je .LBB2_2
; MACROFUSION_MISCHEDPOSTRA-NEXT: # %bb.1: # %if.then
; MACROFUSION_MISCHEDPOSTRA-NEXT: movl $1, %eax
; MACROFUSION_MISCHEDPOSTRA-NEXT: .LBB2_2: # %if.end
; MACROFUSION_MISCHEDPOSTRA-NEXT: retq
; BRANCHFUSION_MISCHEDPOSTRA-LABEL: macrofuse_alu_je:
; BRANCHFUSION_MISCHEDPOSTRA: # %bb.0: # %entry
; BRANCHFUSION_MISCHEDPOSTRA-NEXT: movl %edi, %eax
; BRANCHFUSION_MISCHEDPOSTRA-NEXT: movb $1, (%rsi)
; BRANCHFUSION_MISCHEDPOSTRA-NEXT: addl $-512, %eax # imm = 0xFE00
; BRANCHFUSION_MISCHEDPOSTRA-NEXT: je .LBB2_2
; BRANCHFUSION_MISCHEDPOSTRA-NEXT: # %bb.1: # %if.then
; BRANCHFUSION_MISCHEDPOSTRA-NEXT: movl $1, %eax
; BRANCHFUSION_MISCHEDPOSTRA-NEXT: .LBB2_2: # %if.end
; BRANCHFUSION_MISCHEDPOSTRA-NEXT: retq
entry:
%sub = sub i32 %flags, 512
%tobool = icmp eq i32 %sub, 0
@ -348,27 +337,16 @@ define i32 @macrofuse_dec_je(i32 %flags, i8* %p) nounwind {
; NOFUSION_MISCHEDPOSTRA-NEXT: .LBB3_2: # %if.end
; NOFUSION_MISCHEDPOSTRA-NEXT: retq
;
; BRANCHFUSIONONLY_MISCHEDPOSTRA-LABEL: macrofuse_dec_je:
; BRANCHFUSIONONLY_MISCHEDPOSTRA: # %bb.0: # %entry
; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT: movl %edi, %eax
; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT: movb $1, (%rsi)
; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT: decl %eax
; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT: je .LBB3_2
; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT: # %bb.1: # %if.then
; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT: movl $1, %eax
; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT: .LBB3_2: # %if.end
; BRANCHFUSIONONLY_MISCHEDPOSTRA-NEXT: retq
;
; MACROFUSION_MISCHEDPOSTRA-LABEL: macrofuse_dec_je:
; MACROFUSION_MISCHEDPOSTRA: # %bb.0: # %entry
; MACROFUSION_MISCHEDPOSTRA-NEXT: movl %edi, %eax
; MACROFUSION_MISCHEDPOSTRA-NEXT: movb $1, (%rsi)
; MACROFUSION_MISCHEDPOSTRA-NEXT: decl %eax
; MACROFUSION_MISCHEDPOSTRA-NEXT: je .LBB3_2
; MACROFUSION_MISCHEDPOSTRA-NEXT: # %bb.1: # %if.then
; MACROFUSION_MISCHEDPOSTRA-NEXT: movl $1, %eax
; MACROFUSION_MISCHEDPOSTRA-NEXT: .LBB3_2: # %if.end
; MACROFUSION_MISCHEDPOSTRA-NEXT: retq
; BRANCHFUSION_MISCHEDPOSTRA-LABEL: macrofuse_dec_je:
; BRANCHFUSION_MISCHEDPOSTRA: # %bb.0: # %entry
; BRANCHFUSION_MISCHEDPOSTRA-NEXT: movl %edi, %eax
; BRANCHFUSION_MISCHEDPOSTRA-NEXT: movb $1, (%rsi)
; BRANCHFUSION_MISCHEDPOSTRA-NEXT: decl %eax
; BRANCHFUSION_MISCHEDPOSTRA-NEXT: je .LBB3_2
; BRANCHFUSION_MISCHEDPOSTRA-NEXT: # %bb.1: # %if.then
; BRANCHFUSION_MISCHEDPOSTRA-NEXT: movl $1, %eax
; BRANCHFUSION_MISCHEDPOSTRA-NEXT: .LBB3_2: # %if.end
; BRANCHFUSION_MISCHEDPOSTRA-NEXT: retq
entry:
%sub = sub i32 %flags, 1
%tobool = icmp eq i32 %sub, 0