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https://github.com/RPCS3/llvm-mirror.git
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[MIPS GlobalISel] Select bitreverse
G_BITREVERSE is generated from llvm.bitreverse.<type> intrinsics, clang genrates these intrinsics from __builtin_bitreverse32 and __builtin_bitreverse64. Add lower and narrowscalar for G_BITREVERSE. Lower G_BITREVERSE on MIPS32. Differential Revision: https://reviews.llvm.org/D71363
This commit is contained in:
Petar Avramovic
parent
f13c6fefa7
commit
b897f9871d
@ -238,6 +238,7 @@ public:
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LegalizeResult lowerInsert(MachineInstr &MI);
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LegalizeResult lowerSADDO_SSUBO(MachineInstr &MI);
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LegalizeResult lowerBswap(MachineInstr &MI);
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LegalizeResult lowerBitreverse(MachineInstr &MI);
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private:
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MachineRegisterInfo &MRI;
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@ -1075,7 +1075,8 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
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MI.eraseFromParent();
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return Legalized;
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}
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case TargetOpcode::G_BSWAP: {
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case TargetOpcode::G_BSWAP:
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case TargetOpcode::G_BITREVERSE: {
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if (SizeOp0 % NarrowSize != 0)
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return UnableToLegalize;
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@ -2312,6 +2313,8 @@ LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
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return lowerInsert(MI);
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case G_BSWAP:
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return lowerBswap(MI);
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case G_BITREVERSE:
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return lowerBitreverse(MI);
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}
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}
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@ -4384,3 +4387,44 @@ LegalizerHelper::lowerBswap(MachineInstr &MI) {
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MI.eraseFromParent();
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return Legalized;
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}
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//{ (Src & Mask) >> N } | { (Src << N) & Mask }
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static MachineInstrBuilder SwapN(unsigned N, DstOp Dst, MachineIRBuilder &B,
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MachineInstrBuilder Src, APInt Mask) {
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const LLT Ty = Dst.getLLTTy(*B.getMRI());
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MachineInstrBuilder C_N = B.buildConstant(Ty, N);
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MachineInstrBuilder MaskLoNTo0 = B.buildConstant(Ty, Mask);
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return B.buildOr(Dst, B.buildLShr(Ty, B.buildAnd(Ty, Src, MaskLoNTo0), C_N),
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B.buildAnd(Ty, B.buildShl(Ty, Src, C_N), MaskLoNTo0));
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}
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LegalizerHelper::LegalizeResult
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LegalizerHelper::lowerBitreverse(MachineInstr &MI) {
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Register Dst = MI.getOperand(0).getReg();
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Register Src = MI.getOperand(1).getReg();
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const LLT Ty = MRI.getType(Src);
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unsigned Size = Ty.getSizeInBits();
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MachineInstrBuilder BSWAP =
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MIRBuilder.buildInstr(TargetOpcode::G_BSWAP, {Ty}, {Src});
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// swap high and low 4 bits in 8 bit blocks 7654|3210 -> 3210|7654
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// [(val & 0xF0F0F0F0) >> 4] | [(val & 0x0F0F0F0F) << 4]
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// -> [(val & 0xF0F0F0F0) >> 4] | [(val << 4) & 0xF0F0F0F0]
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MachineInstrBuilder Swap4 =
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SwapN(4, Ty, MIRBuilder, BSWAP, APInt::getSplat(Size, APInt(8, 0xF0)));
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// swap high and low 2 bits in 4 bit blocks 32|10 76|54 -> 10|32 54|76
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// [(val & 0xCCCCCCCC) >> 2] & [(val & 0x33333333) << 2]
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// -> [(val & 0xCCCCCCCC) >> 2] & [(val << 2) & 0xCCCCCCCC]
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MachineInstrBuilder Swap2 =
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SwapN(2, Ty, MIRBuilder, Swap4, APInt::getSplat(Size, APInt(8, 0xCC)));
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// swap high and low 1 bit in 2 bit blocks 1|0 3|2 5|4 7|6 -> 0|1 2|3 4|5 6|7
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// [(val & 0xAAAAAAAA) >> 1] & [(val & 0x55555555) << 1]
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// -> [(val & 0xAAAAAAAA) >> 1] & [(val << 1) & 0xAAAAAAAA]
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SwapN(1, Dst, MIRBuilder, Swap2, APInt::getSplat(Size, APInt(8, 0xAA)));
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MI.eraseFromParent();
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return Legalized;
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}
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@ -198,6 +198,10 @@ MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
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})
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.maxScalar(0, s32);
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getActionDefinitionsBuilder(G_BITREVERSE)
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.lowerFor({s32})
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.maxScalar(0, s32);
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// FP instructions
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getActionDefinitionsBuilder(G_FCONSTANT)
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.legalFor({s32, s64});
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@ -1,5 +1,5 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck %s
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# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck %s
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---
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name: bitreverse_s8
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@ -131,8 +131,11 @@ body: |
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liveins: $vgpr0_vgpr1
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; CHECK-LABEL: name: bitreverse_s64
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
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; CHECK: [[BITREVERSE:%[0-9]+]]:_(s64) = G_BITREVERSE [[COPY]]
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; CHECK: $vgpr0_vgpr1 = COPY [[BITREVERSE]](s64)
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; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
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; CHECK: [[BITREVERSE:%[0-9]+]]:_(s32) = G_BITREVERSE [[UV1]]
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; CHECK: [[BITREVERSE1:%[0-9]+]]:_(s32) = G_BITREVERSE [[UV]]
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; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[BITREVERSE]](s32), [[BITREVERSE1]](s32)
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; CHECK: $vgpr0_vgpr1 = COPY [[MV]](s64)
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%0:_(s64) = COPY $vgpr0_vgpr1
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%1:_(s64) = G_BITREVERSE %0
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$vgpr0_vgpr1 = COPY %1
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@ -147,9 +150,15 @@ body: |
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; CHECK-LABEL: name: bitreverse_v2s64
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; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
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; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
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; CHECK: [[BITREVERSE:%[0-9]+]]:_(s64) = G_BITREVERSE [[UV]]
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; CHECK: [[BITREVERSE1:%[0-9]+]]:_(s64) = G_BITREVERSE [[UV1]]
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[BITREVERSE]](s64), [[BITREVERSE1]](s64)
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; CHECK: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV]](s64)
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; CHECK: [[BITREVERSE:%[0-9]+]]:_(s32) = G_BITREVERSE [[UV3]]
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; CHECK: [[BITREVERSE1:%[0-9]+]]:_(s32) = G_BITREVERSE [[UV2]]
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; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[BITREVERSE]](s32), [[BITREVERSE1]](s32)
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; CHECK: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](s64)
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; CHECK: [[BITREVERSE2:%[0-9]+]]:_(s32) = G_BITREVERSE [[UV5]]
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; CHECK: [[BITREVERSE3:%[0-9]+]]:_(s32) = G_BITREVERSE [[UV4]]
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; CHECK: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[BITREVERSE2]](s32), [[BITREVERSE3]](s32)
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64)
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; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
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%0:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
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%1:_(<2 x s64>) = G_BITREVERSE %0
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215
test/CodeGen/Mips/GlobalISel/legalizer/bitreverse.mir
Normal file
215
test/CodeGen/Mips/GlobalISel/legalizer/bitreverse.mir
Normal file
@ -0,0 +1,215 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
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# RUN: llc -mtriple=mipsel-linux-gnu -run-pass=legalizer -mattr=+mips32r2 -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32R2
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--- |
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define void @bitreverse_i32() { entry: ret void }
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define void @bitreverse_i64() { entry: ret void }
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...
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---
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name: bitreverse_i32
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0
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; MIPS32-LABEL: name: bitreverse_i32
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; MIPS32: liveins: $a0
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; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
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; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
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; MIPS32: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
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; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]]
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; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65280
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; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
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; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
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; MIPS32: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C2]](s32)
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; MIPS32: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
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; MIPS32: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
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; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
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; MIPS32: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[AND1]]
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; MIPS32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
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; MIPS32: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 -252645136
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; MIPS32: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[OR2]], [[C3]](s32)
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; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SHL2]], [[C4]]
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; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[OR2]], [[C4]]
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; MIPS32: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[C3]](s32)
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; MIPS32: [[OR3:%[0-9]+]]:_(s32) = G_OR [[LSHR2]], [[AND2]]
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; MIPS32: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
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; MIPS32: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 -858993460
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; MIPS32: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[OR3]], [[C5]](s32)
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; MIPS32: [[AND4:%[0-9]+]]:_(s32) = G_AND [[SHL3]], [[C6]]
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; MIPS32: [[AND5:%[0-9]+]]:_(s32) = G_AND [[OR3]], [[C6]]
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; MIPS32: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[C5]](s32)
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; MIPS32: [[OR4:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[AND4]]
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; MIPS32: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
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; MIPS32: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1431655766
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; MIPS32: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[OR4]], [[C7]](s32)
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; MIPS32: [[AND6:%[0-9]+]]:_(s32) = G_AND [[SHL4]], [[C8]]
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; MIPS32: [[AND7:%[0-9]+]]:_(s32) = G_AND [[OR4]], [[C8]]
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; MIPS32: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[C7]](s32)
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; MIPS32: [[OR5:%[0-9]+]]:_(s32) = G_OR [[LSHR4]], [[AND6]]
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; MIPS32: $v0 = COPY [[OR5]](s32)
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; MIPS32: RetRA implicit $v0
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; MIPS32R2-LABEL: name: bitreverse_i32
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; MIPS32R2: liveins: $a0
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; MIPS32R2: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; MIPS32R2: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY]]
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; MIPS32R2: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
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; MIPS32R2: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -252645136
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; MIPS32R2: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[BSWAP]], [[C]](s32)
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; MIPS32R2: [[AND:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C1]]
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; MIPS32R2: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BSWAP]], [[C1]]
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; MIPS32R2: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[C]](s32)
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; MIPS32R2: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[AND]]
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; MIPS32R2: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
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; MIPS32R2: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -858993460
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; MIPS32R2: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[OR]], [[C2]](s32)
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; MIPS32R2: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SHL1]], [[C3]]
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; MIPS32R2: [[AND3:%[0-9]+]]:_(s32) = G_AND [[OR]], [[C3]]
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; MIPS32R2: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[C2]](s32)
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; MIPS32R2: [[OR1:%[0-9]+]]:_(s32) = G_OR [[LSHR1]], [[AND2]]
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; MIPS32R2: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
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; MIPS32R2: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1431655766
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; MIPS32R2: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[OR1]], [[C4]](s32)
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; MIPS32R2: [[AND4:%[0-9]+]]:_(s32) = G_AND [[SHL2]], [[C5]]
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; MIPS32R2: [[AND5:%[0-9]+]]:_(s32) = G_AND [[OR1]], [[C5]]
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; MIPS32R2: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[C4]](s32)
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; MIPS32R2: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR2]], [[AND4]]
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; MIPS32R2: $v0 = COPY [[OR2]](s32)
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; MIPS32R2: RetRA implicit $v0
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%0:_(s32) = COPY $a0
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%1:_(s32) = G_BITREVERSE %0
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$v0 = COPY %1(s32)
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RetRA implicit $v0
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...
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---
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name: bitreverse_i64
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1
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; MIPS32-LABEL: name: bitreverse_i64
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; MIPS32: liveins: $a0, $a1
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; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
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; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
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; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
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; MIPS32: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32)
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; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]]
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; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65280
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; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
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; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
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; MIPS32: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C2]](s32)
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; MIPS32: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
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; MIPS32: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
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; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
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; MIPS32: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[AND1]]
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; MIPS32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
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; MIPS32: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 -252645136
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; MIPS32: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[OR2]], [[C3]](s32)
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; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SHL2]], [[C4]]
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; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[OR2]], [[C4]]
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; MIPS32: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[C3]](s32)
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; MIPS32: [[OR3:%[0-9]+]]:_(s32) = G_OR [[LSHR2]], [[AND2]]
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; MIPS32: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
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; MIPS32: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 -858993460
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; MIPS32: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[OR3]], [[C5]](s32)
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; MIPS32: [[AND4:%[0-9]+]]:_(s32) = G_AND [[SHL3]], [[C6]]
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; MIPS32: [[AND5:%[0-9]+]]:_(s32) = G_AND [[OR3]], [[C6]]
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; MIPS32: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[C5]](s32)
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; MIPS32: [[OR4:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[AND4]]
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; MIPS32: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
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; MIPS32: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1431655766
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; MIPS32: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[OR4]], [[C7]](s32)
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; MIPS32: [[AND6:%[0-9]+]]:_(s32) = G_AND [[SHL4]], [[C8]]
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; MIPS32: [[AND7:%[0-9]+]]:_(s32) = G_AND [[OR4]], [[C8]]
|
||||
; MIPS32: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[C7]](s32)
|
||||
; MIPS32: [[OR5:%[0-9]+]]:_(s32) = G_OR [[LSHR4]], [[AND6]]
|
||||
; MIPS32: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
|
||||
; MIPS32: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
|
||||
; MIPS32: [[OR6:%[0-9]+]]:_(s32) = G_OR [[LSHR5]], [[SHL5]]
|
||||
; MIPS32: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
|
||||
; MIPS32: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C2]](s32)
|
||||
; MIPS32: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL6]]
|
||||
; MIPS32: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
|
||||
; MIPS32: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C1]]
|
||||
; MIPS32: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[AND9]]
|
||||
; MIPS32: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[OR8]], [[C3]](s32)
|
||||
; MIPS32: [[AND10:%[0-9]+]]:_(s32) = G_AND [[SHL7]], [[C4]]
|
||||
; MIPS32: [[AND11:%[0-9]+]]:_(s32) = G_AND [[OR8]], [[C4]]
|
||||
; MIPS32: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND11]], [[C3]](s32)
|
||||
; MIPS32: [[OR9:%[0-9]+]]:_(s32) = G_OR [[LSHR7]], [[AND10]]
|
||||
; MIPS32: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[OR9]], [[C5]](s32)
|
||||
; MIPS32: [[AND12:%[0-9]+]]:_(s32) = G_AND [[SHL8]], [[C6]]
|
||||
; MIPS32: [[AND13:%[0-9]+]]:_(s32) = G_AND [[OR9]], [[C6]]
|
||||
; MIPS32: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[AND13]], [[C5]](s32)
|
||||
; MIPS32: [[OR10:%[0-9]+]]:_(s32) = G_OR [[LSHR8]], [[AND12]]
|
||||
; MIPS32: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[OR10]], [[C7]](s32)
|
||||
; MIPS32: [[AND14:%[0-9]+]]:_(s32) = G_AND [[SHL9]], [[C8]]
|
||||
; MIPS32: [[AND15:%[0-9]+]]:_(s32) = G_AND [[OR10]], [[C8]]
|
||||
; MIPS32: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[AND15]], [[C7]](s32)
|
||||
; MIPS32: [[OR11:%[0-9]+]]:_(s32) = G_OR [[LSHR9]], [[AND14]]
|
||||
; MIPS32: $v0 = COPY [[OR5]](s32)
|
||||
; MIPS32: $v1 = COPY [[OR11]](s32)
|
||||
; MIPS32: RetRA implicit $v0, implicit $v1
|
||||
; MIPS32R2-LABEL: name: bitreverse_i64
|
||||
; MIPS32R2: liveins: $a0, $a1
|
||||
; MIPS32R2: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
|
||||
; MIPS32R2: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
|
||||
; MIPS32R2: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY1]]
|
||||
; MIPS32R2: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
|
||||
; MIPS32R2: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -252645136
|
||||
; MIPS32R2: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[BSWAP]], [[C]](s32)
|
||||
; MIPS32R2: [[AND:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C1]]
|
||||
; MIPS32R2: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BSWAP]], [[C1]]
|
||||
; MIPS32R2: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[C]](s32)
|
||||
; MIPS32R2: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[AND]]
|
||||
; MIPS32R2: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
|
||||
; MIPS32R2: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -858993460
|
||||
; MIPS32R2: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[OR]], [[C2]](s32)
|
||||
; MIPS32R2: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SHL1]], [[C3]]
|
||||
; MIPS32R2: [[AND3:%[0-9]+]]:_(s32) = G_AND [[OR]], [[C3]]
|
||||
; MIPS32R2: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[C2]](s32)
|
||||
; MIPS32R2: [[OR1:%[0-9]+]]:_(s32) = G_OR [[LSHR1]], [[AND2]]
|
||||
; MIPS32R2: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
|
||||
; MIPS32R2: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1431655766
|
||||
; MIPS32R2: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[OR1]], [[C4]](s32)
|
||||
; MIPS32R2: [[AND4:%[0-9]+]]:_(s32) = G_AND [[SHL2]], [[C5]]
|
||||
; MIPS32R2: [[AND5:%[0-9]+]]:_(s32) = G_AND [[OR1]], [[C5]]
|
||||
; MIPS32R2: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[C4]](s32)
|
||||
; MIPS32R2: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR2]], [[AND4]]
|
||||
; MIPS32R2: [[BSWAP1:%[0-9]+]]:_(s32) = G_BSWAP [[COPY]]
|
||||
; MIPS32R2: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[BSWAP1]], [[C]](s32)
|
||||
; MIPS32R2: [[AND6:%[0-9]+]]:_(s32) = G_AND [[SHL3]], [[C1]]
|
||||
; MIPS32R2: [[AND7:%[0-9]+]]:_(s32) = G_AND [[BSWAP1]], [[C1]]
|
||||
; MIPS32R2: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[C]](s32)
|
||||
; MIPS32R2: [[OR3:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[AND6]]
|
||||
; MIPS32R2: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[OR3]], [[C2]](s32)
|
||||
; MIPS32R2: [[AND8:%[0-9]+]]:_(s32) = G_AND [[SHL4]], [[C3]]
|
||||
; MIPS32R2: [[AND9:%[0-9]+]]:_(s32) = G_AND [[OR3]], [[C3]]
|
||||
; MIPS32R2: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND9]], [[C2]](s32)
|
||||
; MIPS32R2: [[OR4:%[0-9]+]]:_(s32) = G_OR [[LSHR4]], [[AND8]]
|
||||
; MIPS32R2: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[OR4]], [[C4]](s32)
|
||||
; MIPS32R2: [[AND10:%[0-9]+]]:_(s32) = G_AND [[SHL5]], [[C5]]
|
||||
; MIPS32R2: [[AND11:%[0-9]+]]:_(s32) = G_AND [[OR4]], [[C5]]
|
||||
; MIPS32R2: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND11]], [[C4]](s32)
|
||||
; MIPS32R2: [[OR5:%[0-9]+]]:_(s32) = G_OR [[LSHR5]], [[AND10]]
|
||||
; MIPS32R2: $v0 = COPY [[OR2]](s32)
|
||||
; MIPS32R2: $v1 = COPY [[OR5]](s32)
|
||||
; MIPS32R2: RetRA implicit $v0, implicit $v1
|
||||
%1:_(s32) = COPY $a0
|
||||
%2:_(s32) = COPY $a1
|
||||
%0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)
|
||||
%3:_(s64) = G_BITREVERSE %0
|
||||
%4:_(s32), %5:_(s32) = G_UNMERGE_VALUES %3(s64)
|
||||
$v0 = COPY %4(s32)
|
||||
$v1 = COPY %5(s32)
|
||||
RetRA implicit $v0, implicit $v1
|
||||
|
||||
...
|
||||
184
test/CodeGen/Mips/GlobalISel/llvm-ir/bitreverse.ll
Normal file
184
test/CodeGen/Mips/GlobalISel/llvm-ir/bitreverse.ll
Normal file
@ -0,0 +1,184 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32
|
||||
; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -mattr=+mips32r2 -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32R2
|
||||
|
||||
declare i32 @llvm.bitreverse.i32(i32)
|
||||
define i32 @bitreverse_i32(i32 signext %a) {
|
||||
; MIPS32-LABEL: bitreverse_i32:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: sll $1, $4, 24
|
||||
; MIPS32-NEXT: srl $2, $4, 24
|
||||
; MIPS32-NEXT: or $1, $2, $1
|
||||
; MIPS32-NEXT: andi $2, $4, 65280
|
||||
; MIPS32-NEXT: sll $2, $2, 8
|
||||
; MIPS32-NEXT: or $1, $1, $2
|
||||
; MIPS32-NEXT: srl $2, $4, 8
|
||||
; MIPS32-NEXT: andi $2, $2, 65280
|
||||
; MIPS32-NEXT: or $1, $1, $2
|
||||
; MIPS32-NEXT: lui $2, 61680
|
||||
; MIPS32-NEXT: ori $2, $2, 61680
|
||||
; MIPS32-NEXT: sll $3, $1, 4
|
||||
; MIPS32-NEXT: and $3, $3, $2
|
||||
; MIPS32-NEXT: and $1, $1, $2
|
||||
; MIPS32-NEXT: srl $1, $1, 4
|
||||
; MIPS32-NEXT: or $1, $1, $3
|
||||
; MIPS32-NEXT: lui $2, 52428
|
||||
; MIPS32-NEXT: ori $2, $2, 52428
|
||||
; MIPS32-NEXT: sll $3, $1, 2
|
||||
; MIPS32-NEXT: and $3, $3, $2
|
||||
; MIPS32-NEXT: and $1, $1, $2
|
||||
; MIPS32-NEXT: srl $1, $1, 2
|
||||
; MIPS32-NEXT: or $1, $1, $3
|
||||
; MIPS32-NEXT: lui $2, 43690
|
||||
; MIPS32-NEXT: ori $2, $2, 43690
|
||||
; MIPS32-NEXT: sll $3, $1, 1
|
||||
; MIPS32-NEXT: and $3, $3, $2
|
||||
; MIPS32-NEXT: and $1, $1, $2
|
||||
; MIPS32-NEXT: srl $1, $1, 1
|
||||
; MIPS32-NEXT: or $2, $1, $3
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
;
|
||||
; MIPS32R2-LABEL: bitreverse_i32:
|
||||
; MIPS32R2: # %bb.0: # %entry
|
||||
; MIPS32R2-NEXT: wsbh $1, $4
|
||||
; MIPS32R2-NEXT: rotr $1, $1, 16
|
||||
; MIPS32R2-NEXT: lui $2, 61680
|
||||
; MIPS32R2-NEXT: ori $2, $2, 61680
|
||||
; MIPS32R2-NEXT: sll $3, $1, 4
|
||||
; MIPS32R2-NEXT: and $3, $3, $2
|
||||
; MIPS32R2-NEXT: and $1, $1, $2
|
||||
; MIPS32R2-NEXT: srl $1, $1, 4
|
||||
; MIPS32R2-NEXT: or $1, $1, $3
|
||||
; MIPS32R2-NEXT: lui $2, 52428
|
||||
; MIPS32R2-NEXT: ori $2, $2, 52428
|
||||
; MIPS32R2-NEXT: sll $3, $1, 2
|
||||
; MIPS32R2-NEXT: and $3, $3, $2
|
||||
; MIPS32R2-NEXT: and $1, $1, $2
|
||||
; MIPS32R2-NEXT: srl $1, $1, 2
|
||||
; MIPS32R2-NEXT: or $1, $1, $3
|
||||
; MIPS32R2-NEXT: lui $2, 43690
|
||||
; MIPS32R2-NEXT: ori $2, $2, 43690
|
||||
; MIPS32R2-NEXT: sll $3, $1, 1
|
||||
; MIPS32R2-NEXT: and $3, $3, $2
|
||||
; MIPS32R2-NEXT: and $1, $1, $2
|
||||
; MIPS32R2-NEXT: srl $1, $1, 1
|
||||
; MIPS32R2-NEXT: or $2, $1, $3
|
||||
; MIPS32R2-NEXT: jr $ra
|
||||
; MIPS32R2-NEXT: nop
|
||||
entry:
|
||||
%0 = call i32 @llvm.bitreverse.i32(i32 %a)
|
||||
ret i32 %0
|
||||
}
|
||||
|
||||
declare i64 @llvm.bitreverse.i64(i64)
|
||||
define i64 @bitreverse_i64(i64 signext %a) {
|
||||
; MIPS32-LABEL: bitreverse_i64:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: sll $1, $5, 24
|
||||
; MIPS32-NEXT: srl $2, $5, 24
|
||||
; MIPS32-NEXT: or $1, $2, $1
|
||||
; MIPS32-NEXT: andi $2, $5, 65280
|
||||
; MIPS32-NEXT: sll $2, $2, 8
|
||||
; MIPS32-NEXT: or $1, $1, $2
|
||||
; MIPS32-NEXT: srl $2, $5, 8
|
||||
; MIPS32-NEXT: andi $2, $2, 65280
|
||||
; MIPS32-NEXT: or $1, $1, $2
|
||||
; MIPS32-NEXT: lui $2, 61680
|
||||
; MIPS32-NEXT: ori $2, $2, 61680
|
||||
; MIPS32-NEXT: sll $3, $1, 4
|
||||
; MIPS32-NEXT: and $3, $3, $2
|
||||
; MIPS32-NEXT: and $1, $1, $2
|
||||
; MIPS32-NEXT: srl $1, $1, 4
|
||||
; MIPS32-NEXT: or $1, $1, $3
|
||||
; MIPS32-NEXT: lui $3, 52428
|
||||
; MIPS32-NEXT: ori $3, $3, 52428
|
||||
; MIPS32-NEXT: sll $5, $1, 2
|
||||
; MIPS32-NEXT: and $5, $5, $3
|
||||
; MIPS32-NEXT: and $1, $1, $3
|
||||
; MIPS32-NEXT: srl $1, $1, 2
|
||||
; MIPS32-NEXT: or $1, $1, $5
|
||||
; MIPS32-NEXT: lui $5, 43690
|
||||
; MIPS32-NEXT: ori $5, $5, 43690
|
||||
; MIPS32-NEXT: sll $6, $1, 1
|
||||
; MIPS32-NEXT: and $6, $6, $5
|
||||
; MIPS32-NEXT: and $1, $1, $5
|
||||
; MIPS32-NEXT: srl $1, $1, 1
|
||||
; MIPS32-NEXT: or $1, $1, $6
|
||||
; MIPS32-NEXT: sll $6, $4, 24
|
||||
; MIPS32-NEXT: srl $7, $4, 24
|
||||
; MIPS32-NEXT: or $6, $7, $6
|
||||
; MIPS32-NEXT: andi $7, $4, 65280
|
||||
; MIPS32-NEXT: sll $7, $7, 8
|
||||
; MIPS32-NEXT: or $6, $6, $7
|
||||
; MIPS32-NEXT: srl $4, $4, 8
|
||||
; MIPS32-NEXT: andi $4, $4, 65280
|
||||
; MIPS32-NEXT: or $4, $6, $4
|
||||
; MIPS32-NEXT: sll $6, $4, 4
|
||||
; MIPS32-NEXT: and $6, $6, $2
|
||||
; MIPS32-NEXT: and $2, $4, $2
|
||||
; MIPS32-NEXT: srl $2, $2, 4
|
||||
; MIPS32-NEXT: or $2, $2, $6
|
||||
; MIPS32-NEXT: sll $4, $2, 2
|
||||
; MIPS32-NEXT: and $4, $4, $3
|
||||
; MIPS32-NEXT: and $2, $2, $3
|
||||
; MIPS32-NEXT: srl $2, $2, 2
|
||||
; MIPS32-NEXT: or $2, $2, $4
|
||||
; MIPS32-NEXT: sll $3, $2, 1
|
||||
; MIPS32-NEXT: and $3, $3, $5
|
||||
; MIPS32-NEXT: and $2, $2, $5
|
||||
; MIPS32-NEXT: srl $2, $2, 1
|
||||
; MIPS32-NEXT: or $3, $2, $3
|
||||
; MIPS32-NEXT: move $2, $1
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
;
|
||||
; MIPS32R2-LABEL: bitreverse_i64:
|
||||
; MIPS32R2: # %bb.0: # %entry
|
||||
; MIPS32R2-NEXT: wsbh $1, $5
|
||||
; MIPS32R2-NEXT: rotr $1, $1, 16
|
||||
; MIPS32R2-NEXT: lui $2, 61680
|
||||
; MIPS32R2-NEXT: ori $2, $2, 61680
|
||||
; MIPS32R2-NEXT: sll $3, $1, 4
|
||||
; MIPS32R2-NEXT: and $3, $3, $2
|
||||
; MIPS32R2-NEXT: and $1, $1, $2
|
||||
; MIPS32R2-NEXT: srl $1, $1, 4
|
||||
; MIPS32R2-NEXT: or $1, $1, $3
|
||||
; MIPS32R2-NEXT: lui $3, 52428
|
||||
; MIPS32R2-NEXT: ori $3, $3, 52428
|
||||
; MIPS32R2-NEXT: sll $5, $1, 2
|
||||
; MIPS32R2-NEXT: and $5, $5, $3
|
||||
; MIPS32R2-NEXT: and $1, $1, $3
|
||||
; MIPS32R2-NEXT: srl $1, $1, 2
|
||||
; MIPS32R2-NEXT: or $1, $1, $5
|
||||
; MIPS32R2-NEXT: lui $5, 43690
|
||||
; MIPS32R2-NEXT: ori $5, $5, 43690
|
||||
; MIPS32R2-NEXT: sll $6, $1, 1
|
||||
; MIPS32R2-NEXT: and $6, $6, $5
|
||||
; MIPS32R2-NEXT: and $1, $1, $5
|
||||
; MIPS32R2-NEXT: srl $1, $1, 1
|
||||
; MIPS32R2-NEXT: or $1, $1, $6
|
||||
; MIPS32R2-NEXT: wsbh $4, $4
|
||||
; MIPS32R2-NEXT: rotr $4, $4, 16
|
||||
; MIPS32R2-NEXT: sll $6, $4, 4
|
||||
; MIPS32R2-NEXT: and $6, $6, $2
|
||||
; MIPS32R2-NEXT: and $2, $4, $2
|
||||
; MIPS32R2-NEXT: srl $2, $2, 4
|
||||
; MIPS32R2-NEXT: or $2, $2, $6
|
||||
; MIPS32R2-NEXT: sll $4, $2, 2
|
||||
; MIPS32R2-NEXT: and $4, $4, $3
|
||||
; MIPS32R2-NEXT: and $2, $2, $3
|
||||
; MIPS32R2-NEXT: srl $2, $2, 2
|
||||
; MIPS32R2-NEXT: or $2, $2, $4
|
||||
; MIPS32R2-NEXT: sll $3, $2, 1
|
||||
; MIPS32R2-NEXT: and $3, $3, $5
|
||||
; MIPS32R2-NEXT: and $2, $2, $5
|
||||
; MIPS32R2-NEXT: srl $2, $2, 1
|
||||
; MIPS32R2-NEXT: or $3, $2, $3
|
||||
; MIPS32R2-NEXT: move $2, $1
|
||||
; MIPS32R2-NEXT: jr $ra
|
||||
; MIPS32R2-NEXT: nop
|
||||
entry:
|
||||
%0 = call i64 @llvm.bitreverse.i64(i64 %a)
|
||||
ret i64 %0
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user