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back-end libcall handling for ATOMIC_SWAP (__sync_lock_test_and_set)

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llvm-svn: 106342
This commit is contained in:
Jim Grosbach 2010-06-18 23:03:10 +00:00
parent b04dbfd059
commit b8c94667a8
4 changed files with 21 additions and 0 deletions
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4
include/llvm/CodeGen/RuntimeLibcalls.h
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@ -252,6 +252,10 @@ namespace RTLIB {
SYNC_VAL_COMPARE_AND_SWAP_2,
SYNC_VAL_COMPARE_AND_SWAP_4,
SYNC_VAL_COMPARE_AND_SWAP_8,
SYNC_LOCK_TEST_AND_SET_1,
SYNC_LOCK_TEST_AND_SET_2,
SYNC_LOCK_TEST_AND_SET_4,
SYNC_LOCK_TEST_AND_SET_8,
SYNC_FETCH_AND_ADD_1,
SYNC_FETCH_AND_ADD_2,
SYNC_FETCH_AND_ADD_4,

9
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
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@ -2399,6 +2399,15 @@ std::pair <SDValue, SDValue> SelectionDAGLegalize::ExpandAtomic(SDNode *Node) {
default:
llvm_unreachable("Unhandled atomic intrinsic Expand!");
break;
case ISD::ATOMIC_SWAP:
switch (VT.SimpleTy) {
default: llvm_unreachable("Unexpected value type for atomic!");
case MVT::i8: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_1; break;
case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break;
case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break;
case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break;
}
break;
case ISD::ATOMIC_CMP_SWAP:
switch (VT.SimpleTy) {
default: llvm_unreachable("Unexpected value type for atomic!");

4
lib/CodeGen/SelectionDAG/TargetLowering.cpp
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@ -265,6 +265,10 @@ static void InitLibcallNames(const char **Names) {
Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2";
Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4";
Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8";
Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1";
Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2";
Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4";
Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8";
Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1";
Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2";
Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4";

4
lib/Target/ARM/ARMISelLowering.cpp
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@ -420,6 +420,9 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Expand);
setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Expand);
setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
setOperationAction(ISD::ATOMIC_SWAP, MVT::i8, Expand);
setOperationAction(ISD::ATOMIC_SWAP, MVT::i16, Expand);
setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i8, Expand);
setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i16, Expand);
setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
@ -441,6 +444,7 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
}
// 64-bit versions are always libcalls (for now)
setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Expand);
setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Expand);
setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Expand);
setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Expand);
setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Expand);