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[DivRemPairs] make sure we have a valid CFG for hoisting division

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This transform was added with e38b7e894808ec2
and as shown in:
https://llvm.org/PR51241
...it could crash without an extra check of the blocks.

There might be a more compact way to write this constraint,
but we can't just count the successors/predecessors without
affecting a test that includes a switch instruction.

(cherry picked from commit 5b83261c1518a39636abe094123f1704bbfd972f)
This commit is contained in:
Sanjay Patel 2021-07-28 11:04:54 -04:00 committed by Tom Stellard
parent 7c9c296915
commit b92c9f9565
2 changed files with 36 additions and 3 deletions
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7
lib/Transforms/Scalar/DivRemPairs.cpp
View File

@ -272,9 +272,10 @@ static bool optimizeDivRem(Function &F, const TargetTransformInfo &TTI,
if (PredBB && IsSafeToHoist(RemInst, RemBB) &&
IsSafeToHoist(DivInst, DivBB) &&
llvm::all_of(successors(PredBB), [&](BasicBlock *BB) {
return BB == DivBB || BB == RemBB;
})) {
all_of(successors(PredBB),
[&](BasicBlock *BB) { return BB == DivBB || BB == RemBB; }) &&
all_of(predecessors(DivBB),
[&](BasicBlock *BB) { return BB == RemBB || BB == PredBB; })) {
DivDominates = true;
DivInst->moveBefore(PredBB->getTerminator());
Changed = true;

32
test/Transforms/DivRemPairs/X86/div-expanded-rem-pair.ll
View File

@ -529,3 +529,35 @@ return: ; preds = %if.then, %if.end3
%retval.0 = phi i64 [ %div, %if.end3 ], [ 0, %if.then ]
ret i64 %retval.0
}
; Negative test (this would create invalid IR and crash).
; The div block can't have predecessors other than the rem block
; and the common single pred block (it is reachable from entry here).
define i32 @PR51241(i1 %b1, i1 %b2, i32 %t0) {
; CHECK-LABEL: @PR51241(
; CHECK-NEXT: entry:
; CHECK-NEXT: br i1 [[B1:%.*]], label [[DIVBB:%.*]], label [[PREDBB:%.*]]
; CHECK: predbb:
; CHECK-NEXT: br i1 [[B2:%.*]], label [[DIVBB]], label [[REMBB:%.*]]
; CHECK: rembb:
; CHECK-NEXT: [[REM2:%.*]] = srem i32 7, [[T0:%.*]]
; CHECK-NEXT: br label [[DIVBB]]
; CHECK: divbb:
; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 7, [[T0]]
; CHECK-NEXT: ret i32 [[DIV]]
;
entry:
br i1 %b1, label %divbb, label %predbb
predbb:
br i1 %b2, label %divbb, label %rembb
rembb:
%rem2 = srem i32 7, %t0
br label %divbb
divbb:
%div = sdiv i32 7, %t0
ret i32 %div
}