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[ARM] Add support for MVE pre and post inc loads and stores
This adds pre- and post- increment and decrements for MVE loads and stores. It uses the builtin pre and post load/store detection, unlike Neon. Loads are selected with the code in tryT2IndexedLoad, stores are selected with tablegen patterns. The immediates have a +/-7bit range, multiplied by the size of the element. Differential Revision: https://reviews.llvm.org/D63840 llvm-svn: 368305
This commit is contained in:
David Green
parent
3265a2671b
commit
b937fefeae
@ -1113,6 +1113,16 @@ def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
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let IsStore = 1;
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let MemoryVT = f32;
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}
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def pre_truncstvi8 : PatFrag<(ops node:$val, node:$base, node:$offset),
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(pre_truncst node:$val, node:$base, node:$offset)> {
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let IsStore = 1;
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let ScalarMemoryVT = i8;
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}
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def pre_truncstvi16 : PatFrag<(ops node:$val, node:$base, node:$offset),
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(pre_truncst node:$val, node:$base, node:$offset)> {
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let IsStore = 1;
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let ScalarMemoryVT = i16;
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}
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def post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset),
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(istore node:$val, node:$ptr, node:$offset), [{
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@ -1150,6 +1160,16 @@ def post_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
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let IsStore = 1;
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let MemoryVT = f32;
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}
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def post_truncstvi8 : PatFrag<(ops node:$val, node:$base, node:$offset),
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(post_truncst node:$val, node:$base, node:$offset)> {
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let IsStore = 1;
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let ScalarMemoryVT = i8;
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}
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def post_truncstvi16 : PatFrag<(ops node:$val, node:$base, node:$offset),
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(post_truncst node:$val, node:$base, node:$offset)> {
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let IsStore = 1;
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let ScalarMemoryVT = i16;
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}
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def nonvolatile_load : PatFrag<(ops node:$ptr),
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(load node:$ptr), [{
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@ -146,9 +146,12 @@ public:
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SDValue &OffImm);
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bool SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
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SDValue &OffImm);
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template<unsigned Shift>
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bool SelectT2AddrModeImm7(SDValue N, SDValue &Base,
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SDValue &OffImm);
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template <unsigned Shift>
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bool SelectT2AddrModeImm7Offset(SDNode *Op, SDValue N, SDValue &OffImm);
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bool SelectT2AddrModeImm7Offset(SDNode *Op, SDValue N, SDValue &OffImm,
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unsigned Shift);
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template <unsigned Shift>
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bool SelectT2AddrModeImm7(SDValue N, SDValue &Base, SDValue &OffImm);
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bool SelectT2AddrModeSoReg(SDValue N, SDValue &Base,
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SDValue &OffReg, SDValue &ShImm);
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bool SelectT2AddrModeExclusive(SDValue N, SDValue &Base, SDValue &OffImm);
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@ -179,6 +182,7 @@ private:
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bool tryARMIndexedLoad(SDNode *N);
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bool tryT1IndexedLoad(SDNode *N);
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bool tryT2IndexedLoad(SDNode *N);
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bool tryMVEIndexedLoad(SDNode *N);
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/// SelectVLD - Select NEON load intrinsics. NumVecs should be
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/// 1, 2, 3 or 4. The opcode arrays specify the instructions used for
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@ -1307,6 +1311,31 @@ bool ARMDAGToDAGISel::SelectT2AddrModeImm7(SDValue N,
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return true;
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}
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template <unsigned Shift>
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bool ARMDAGToDAGISel::SelectT2AddrModeImm7Offset(SDNode *Op, SDValue N,
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SDValue &OffImm) {
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return SelectT2AddrModeImm7Offset(Op, N, OffImm, Shift);
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}
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bool ARMDAGToDAGISel::SelectT2AddrModeImm7Offset(SDNode *Op, SDValue N,
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SDValue &OffImm,
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unsigned Shift) {
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unsigned Opcode = Op->getOpcode();
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ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
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? cast<LoadSDNode>(Op)->getAddressingMode()
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: cast<StoreSDNode>(Op)->getAddressingMode();
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int RHSC;
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if (isScaledConstantInRange(N, 1 << Shift, 0, 0x80, RHSC)) { // 7 bits.
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OffImm =
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((AM == ISD::PRE_INC) || (AM == ISD::POST_INC))
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? CurDAG->getTargetConstant(RHSC * (1 << Shift), SDLoc(N), MVT::i32)
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: CurDAG->getTargetConstant(-RHSC * (1 << Shift), SDLoc(N),
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MVT::i32);
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return true;
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}
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return false;
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}
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bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue N,
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SDValue &Base,
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SDValue &OffReg, SDValue &ShImm) {
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@ -1565,6 +1594,68 @@ bool ARMDAGToDAGISel::tryT2IndexedLoad(SDNode *N) {
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return false;
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}
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bool ARMDAGToDAGISel::tryMVEIndexedLoad(SDNode *N) {
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LoadSDNode *LD = cast<LoadSDNode>(N);
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ISD::MemIndexedMode AM = LD->getAddressingMode();
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if (AM == ISD::UNINDEXED)
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return false;
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EVT LoadedVT = LD->getMemoryVT();
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if (!LoadedVT.isVector())
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return false;
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bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
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SDValue Offset;
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bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
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unsigned Opcode = 0;
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unsigned Align = LD->getAlignment();
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bool IsLE = Subtarget->isLittle();
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if (Align >= 2 && LoadedVT == MVT::v4i16 &&
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SelectT2AddrModeImm7Offset(N, LD->getOffset(), Offset, 1)) {
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if (isSExtLd)
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Opcode = isPre ? ARM::MVE_VLDRHS32_pre : ARM::MVE_VLDRHS32_post;
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else
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Opcode = isPre ? ARM::MVE_VLDRHU32_pre : ARM::MVE_VLDRHU32_post;
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} else if (LoadedVT == MVT::v8i8 &&
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SelectT2AddrModeImm7Offset(N, LD->getOffset(), Offset, 0)) {
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if (isSExtLd)
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Opcode = isPre ? ARM::MVE_VLDRBS16_pre : ARM::MVE_VLDRBS16_post;
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else
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Opcode = isPre ? ARM::MVE_VLDRBU16_pre : ARM::MVE_VLDRBU16_post;
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} else if (LoadedVT == MVT::v4i8 &&
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SelectT2AddrModeImm7Offset(N, LD->getOffset(), Offset, 0)) {
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if (isSExtLd)
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Opcode = isPre ? ARM::MVE_VLDRBS32_pre : ARM::MVE_VLDRBS32_post;
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else
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Opcode = isPre ? ARM::MVE_VLDRBU32_pre : ARM::MVE_VLDRBU32_post;
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} else if (Align >= 4 &&
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(IsLE || LoadedVT == MVT::v4i32 || LoadedVT == MVT::v4f32) &&
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SelectT2AddrModeImm7Offset(N, LD->getOffset(), Offset, 2))
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Opcode = isPre ? ARM::MVE_VLDRWU32_pre : ARM::MVE_VLDRWU32_post;
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else if (Align >= 2 &&
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(IsLE || LoadedVT == MVT::v8i16 || LoadedVT == MVT::v8f16) &&
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SelectT2AddrModeImm7Offset(N, LD->getOffset(), Offset, 1))
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Opcode = isPre ? ARM::MVE_VLDRHU16_pre : ARM::MVE_VLDRHU16_post;
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else if ((IsLE || LoadedVT == MVT::v16i8) &&
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SelectT2AddrModeImm7Offset(N, LD->getOffset(), Offset, 0))
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Opcode = isPre ? ARM::MVE_VLDRBU8_pre : ARM::MVE_VLDRBU8_post;
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else
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return false;
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SDValue Chain = LD->getChain();
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SDValue Base = LD->getBasePtr();
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SDValue Ops[] = {Base, Offset,
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CurDAG->getTargetConstant(ARMVCC::None, SDLoc(N), MVT::i32),
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CurDAG->getRegister(0, MVT::i32), Chain};
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SDNode *New = CurDAG->getMachineNode(Opcode, SDLoc(N), LD->getValueType(0),
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MVT::i32, MVT::Other, Ops);
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transferMemOperands(N, New);
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ReplaceUses(SDValue(N, 0), SDValue(New, 1));
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ReplaceUses(SDValue(N, 1), SDValue(New, 0));
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ReplaceUses(SDValue(N, 2), SDValue(New, 2));
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CurDAG->RemoveDeadNode(N);
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return true;
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}
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/// Form a GPRPair pseudo register from a pair of GPR regs.
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SDNode *ARMDAGToDAGISel::createGPRPairNode(EVT VT, SDValue V0, SDValue V1) {
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SDLoc dl(V0.getNode());
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@ -2987,6 +3078,8 @@ void ARMDAGToDAGISel::Select(SDNode *N) {
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return;
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}
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case ISD::LOAD: {
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if (Subtarget->hasMVEIntegerOps() && tryMVEIndexedLoad(N))
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return;
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if (Subtarget->isThumb() && Subtarget->hasThumb2()) {
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if (tryT2IndexedLoad(N))
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return;
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@ -273,6 +273,13 @@ void ARMTargetLowering::addMVEVectorTypes(bool HasMVEFP) {
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setOperationAction(ISD::FP_TO_SINT, VT, Expand);
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setOperationAction(ISD::FP_TO_UINT, VT, Expand);
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}
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// Pre and Post inc are supported on loads and stores
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for (unsigned im = (unsigned)ISD::PRE_INC;
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im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
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setIndexedLoadAction(im, VT, Legal);
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setIndexedStoreAction(im, VT, Legal);
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}
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}
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const MVT FloatTypes[] = { MVT::v8f16, MVT::v4f32 };
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@ -291,6 +298,13 @@ void ARMTargetLowering::addMVEVectorTypes(bool HasMVEFP) {
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setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Legal);
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setOperationAction(ISD::SETCC, VT, Custom);
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// Pre and Post inc are supported on loads and stores
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for (unsigned im = (unsigned)ISD::PRE_INC;
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im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
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setIndexedLoadAction(im, VT, Legal);
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setIndexedStoreAction(im, VT, Legal);
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}
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if (HasMVEFP) {
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setOperationAction(ISD::FMINNUM, VT, Legal);
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setOperationAction(ISD::FMAXNUM, VT, Legal);
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@ -338,6 +352,17 @@ void ARMTargetLowering::addMVEVectorTypes(bool HasMVEFP) {
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setTruncStoreAction(MVT::v4i32, MVT::v4i8, Legal);
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setTruncStoreAction(MVT::v8i16, MVT::v8i8, Legal);
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// Pre and Post inc on these are legal, given the correct extends
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for (unsigned im = (unsigned)ISD::PRE_INC;
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im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
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setIndexedLoadAction(im, MVT::v8i8, Legal);
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setIndexedStoreAction(im, MVT::v8i8, Legal);
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setIndexedLoadAction(im, MVT::v4i8, Legal);
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setIndexedStoreAction(im, MVT::v4i8, Legal);
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setIndexedLoadAction(im, MVT::v4i16, Legal);
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setIndexedStoreAction(im, MVT::v4i16, Legal);
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}
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// Predicate types
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const MVT pTypes[] = {MVT::v16i1, MVT::v8i1, MVT::v4i1};
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for (auto VT : pTypes) {
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@ -14620,6 +14645,52 @@ static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
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return false;
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}
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static bool getMVEIndexedAddressParts(SDNode *Ptr, EVT VT, unsigned Align,
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bool isSEXTLoad, bool isLE, SDValue &Base,
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SDValue &Offset, bool &isInc,
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SelectionDAG &DAG) {
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if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
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return false;
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if (!isa<ConstantSDNode>(Ptr->getOperand(1)))
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return false;
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ConstantSDNode *RHS = cast<ConstantSDNode>(Ptr->getOperand(1));
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int RHSC = (int)RHS->getZExtValue();
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auto IsInRange = [&](int RHSC, int Limit, int Scale) {
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if (RHSC < 0 && RHSC > -Limit * Scale && RHSC % Scale == 0) {
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assert(Ptr->getOpcode() == ISD::ADD);
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isInc = false;
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Offset = DAG.getConstant(-RHSC, SDLoc(Ptr), RHS->getValueType(0));
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return true;
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} else if (RHSC > 0 && RHSC < Limit * Scale && RHSC % Scale == 0) {
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isInc = Ptr->getOpcode() == ISD::ADD;
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Offset = DAG.getConstant(RHSC, SDLoc(Ptr), RHS->getValueType(0));
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return true;
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}
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return false;
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};
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// Try to find a matching instruction based on s/zext, Alignment, Offset and
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// (in BE) type.
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Base = Ptr->getOperand(0);
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if (VT == MVT::v4i16) {
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if (Align >= 2 && IsInRange(RHSC, 0x80, 2))
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return true;
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} else if (VT == MVT::v4i8 || VT == MVT::v8i8) {
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if (IsInRange(RHSC, 0x80, 1))
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return true;
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} else if (Align >= 4 && (isLE || VT == MVT::v4i32 || VT == MVT::v4f32) &&
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IsInRange(RHSC, 0x80, 4))
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return true;
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else if (Align >= 2 && (isLE || VT == MVT::v8i16 || VT == MVT::v8f16) &&
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IsInRange(RHSC, 0x80, 2))
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return true;
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else if ((isLE || VT == MVT::v16i8) && IsInRange(RHSC, 0x80, 1))
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return true;
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return false;
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}
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/// getPreIndexedAddressParts - returns true by value, base pointer and
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/// offset pointer and addressing mode by reference if the node's address
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/// can be legally represented as pre-indexed load / store address.
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@ -14633,25 +14704,35 @@ ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
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EVT VT;
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SDValue Ptr;
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unsigned Align;
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bool isSEXTLoad = false;
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if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
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Ptr = LD->getBasePtr();
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VT = LD->getMemoryVT();
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VT = LD->getMemoryVT();
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Align = LD->getAlignment();
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isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
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} else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
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Ptr = ST->getBasePtr();
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VT = ST->getMemoryVT();
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VT = ST->getMemoryVT();
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Align = ST->getAlignment();
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} else
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return false;
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bool isInc;
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bool isLegal = false;
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if (Subtarget->isThumb2())
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isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
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Offset, isInc, DAG);
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else
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isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
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Offset, isInc, DAG);
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if (VT.isVector())
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isLegal = Subtarget->hasMVEIntegerOps() &&
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getMVEIndexedAddressParts(Ptr.getNode(), VT, Align, isSEXTLoad,
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Subtarget->isLittle(), Base, Offset,
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isInc, DAG);
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else {
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if (Subtarget->isThumb2())
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isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
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Offset, isInc, DAG);
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else
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isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
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Offset, isInc, DAG);
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}
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if (!isLegal)
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return false;
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@ -14669,15 +14750,18 @@ bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
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SelectionDAG &DAG) const {
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EVT VT;
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SDValue Ptr;
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unsigned Align;
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bool isSEXTLoad = false, isNonExt;
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if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
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VT = LD->getMemoryVT();
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VT = LD->getMemoryVT();
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Ptr = LD->getBasePtr();
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Align = LD->getAlignment();
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isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
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isNonExt = LD->getExtensionType() == ISD::NON_EXTLOAD;
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} else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
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VT = ST->getMemoryVT();
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VT = ST->getMemoryVT();
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Ptr = ST->getBasePtr();
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Align = ST->getAlignment();
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isNonExt = !ST->isTruncatingStore();
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} else
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return false;
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@ -14700,12 +14784,19 @@ bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
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bool isInc;
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bool isLegal = false;
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if (Subtarget->isThumb2())
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isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
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isInc, DAG);
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else
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isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
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if (VT.isVector())
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isLegal = Subtarget->hasMVEIntegerOps() &&
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getMVEIndexedAddressParts(Op, VT, Align, isSEXTLoad,
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Subtarget->isLittle(), Base, Offset,
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isInc, DAG);
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else {
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if (Subtarget->isThumb2())
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isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
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isInc, DAG);
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else
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isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
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isInc, DAG);
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}
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if (!isLegal)
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return false;
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@ -221,7 +221,9 @@ def t2am_imm7shift0OffsetAsmOperand : t2am_imm7shiftOffsetAsmOperand<0>;
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def t2am_imm7shift1OffsetAsmOperand : t2am_imm7shiftOffsetAsmOperand<1>;
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def t2am_imm7shift2OffsetAsmOperand : t2am_imm7shiftOffsetAsmOperand<2>;
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class t2am_imm7_offset<int shift> : MemOperand {
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class t2am_imm7_offset<int shift> : MemOperand,
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ComplexPattern<i32, 1, "SelectT2AddrModeImm7Offset<"#shift#">",
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[], [SDNPWantRoot]> {
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// They are printed the same way as the imm8 version
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let PrintMethod = "printT2AddrModeImm8OffsetOperand";
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let ParserMatchClass =
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@ -4812,6 +4814,38 @@ multiclass MVE_unpred_vector_load<Instruction RegImmInst, PatFrag LoadKind,
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def : MVE_unpred_vector_load_typed<v2f64, RegImmInst, LoadKind, shift>;
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}
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class MVE_unpred_vector_offset_store_typed<ValueType Ty, Instruction Opcode,
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PatFrag StoreKind, int shift>
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: Pat<(StoreKind (Ty MQPR:$Rt), tGPR:$Rn, t2am_imm7_offset<shift>:$addr),
|
||||
(Opcode MQPR:$Rt, tGPR:$Rn, t2am_imm7_offset<shift>:$addr)>;
|
||||
|
||||
multiclass MVE_unpred_vector_offset_store<Instruction RegImmInst, PatFrag StoreKind,
|
||||
int shift> {
|
||||
def : MVE_unpred_vector_offset_store_typed<v16i8, RegImmInst, StoreKind, shift>;
|
||||
def : MVE_unpred_vector_offset_store_typed<v8i16, RegImmInst, StoreKind, shift>;
|
||||
def : MVE_unpred_vector_offset_store_typed<v8f16, RegImmInst, StoreKind, shift>;
|
||||
def : MVE_unpred_vector_offset_store_typed<v4i32, RegImmInst, StoreKind, shift>;
|
||||
def : MVE_unpred_vector_offset_store_typed<v4f32, RegImmInst, StoreKind, shift>;
|
||||
def : MVE_unpred_vector_offset_store_typed<v2i64, RegImmInst, StoreKind, shift>;
|
||||
def : MVE_unpred_vector_offset_store_typed<v2f64, RegImmInst, StoreKind, shift>;
|
||||
}
|
||||
def aligned32_pre_store : PatFrag<(ops node:$val, node:$ptr, node:$offset),
|
||||
(pre_store node:$val, node:$ptr, node:$offset), [{
|
||||
return cast<StoreSDNode>(N)->getAlignment() >= 4;
|
||||
}]>;
|
||||
def aligned32_post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset),
|
||||
(post_store node:$val, node:$ptr, node:$offset), [{
|
||||
return cast<StoreSDNode>(N)->getAlignment() >= 4;
|
||||
}]>;
|
||||
def aligned16_pre_store : PatFrag<(ops node:$val, node:$ptr, node:$offset),
|
||||
(pre_store node:$val, node:$ptr, node:$offset), [{
|
||||
return cast<StoreSDNode>(N)->getAlignment() == 2;
|
||||
}]>;
|
||||
def aligned16_post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset),
|
||||
(post_store node:$val, node:$ptr, node:$offset), [{
|
||||
return cast<StoreSDNode>(N)->getAlignment() == 2;
|
||||
}]>;
|
||||
|
||||
let Predicates = [HasMVEInt, IsLE] in {
|
||||
defm : MVE_unpred_vector_store<MVE_VSTRBU8, byte_alignedstore, 0>;
|
||||
defm : MVE_unpred_vector_store<MVE_VSTRHU16, hword_alignedstore, 1>;
|
||||
@ -4820,6 +4854,13 @@ let Predicates = [HasMVEInt, IsLE] in {
|
||||
defm : MVE_unpred_vector_load<MVE_VLDRBU8, byte_alignedload, 0>;
|
||||
defm : MVE_unpred_vector_load<MVE_VLDRHU16, hword_alignedload, 1>;
|
||||
defm : MVE_unpred_vector_load<MVE_VLDRWU32, alignedload32, 2>;
|
||||
|
||||
defm : MVE_unpred_vector_offset_store<MVE_VSTRBU8_pre, pre_store, 0>;
|
||||
defm : MVE_unpred_vector_offset_store<MVE_VSTRBU8_post, post_store, 0>;
|
||||
defm : MVE_unpred_vector_offset_store<MVE_VSTRHU16_pre, aligned16_pre_store, 1>;
|
||||
defm : MVE_unpred_vector_offset_store<MVE_VSTRHU16_post, aligned16_post_store, 1>;
|
||||
defm : MVE_unpred_vector_offset_store<MVE_VSTRWU32_pre, aligned32_pre_store, 2>;
|
||||
defm : MVE_unpred_vector_offset_store<MVE_VSTRWU32_post, aligned32_post_store, 2>;
|
||||
}
|
||||
|
||||
let Predicates = [HasMVEInt, IsBE] in {
|
||||
@ -4860,6 +4901,17 @@ let Predicates = [HasMVEInt, IsBE] in {
|
||||
(MVE_VSTRBU8 (MVE_VREV16_8 MQPR:$val), t2addrmode_imm7<0>:$addr)>;
|
||||
def : Pat<(store (v8f16 MQPR:$val), t2addrmode_imm7<0>:$addr),
|
||||
(MVE_VSTRBU8 (MVE_VREV16_8 MQPR:$val), t2addrmode_imm7<0>:$addr)>;
|
||||
|
||||
def : MVE_unpred_vector_offset_store_typed<v16i8, MVE_VSTRBU8_pre, pre_store, 0>;
|
||||
def : MVE_unpred_vector_offset_store_typed<v16i8, MVE_VSTRBU8_post, post_store, 0>;
|
||||
def : MVE_unpred_vector_offset_store_typed<v8i16, MVE_VSTRHU16_pre, aligned16_pre_store, 1>;
|
||||
def : MVE_unpred_vector_offset_store_typed<v8i16, MVE_VSTRHU16_post, aligned16_post_store, 1>;
|
||||
def : MVE_unpred_vector_offset_store_typed<v8f16, MVE_VSTRHU16_pre, aligned16_pre_store, 1>;
|
||||
def : MVE_unpred_vector_offset_store_typed<v8f16, MVE_VSTRHU16_post, aligned16_post_store, 1>;
|
||||
def : MVE_unpred_vector_offset_store_typed<v4i32, MVE_VSTRWU32_pre, aligned32_pre_store, 2>;
|
||||
def : MVE_unpred_vector_offset_store_typed<v4i32, MVE_VSTRWU32_post, aligned32_post_store, 2>;
|
||||
def : MVE_unpred_vector_offset_store_typed<v4f32, MVE_VSTRWU32_pre, aligned32_pre_store, 2>;
|
||||
def : MVE_unpred_vector_offset_store_typed<v4f32, MVE_VSTRWU32_post, aligned32_post_store, 2>;
|
||||
}
|
||||
|
||||
let Predicates = [HasMVEInt] in {
|
||||
@ -4877,6 +4929,10 @@ let Predicates = [HasMVEInt] in {
|
||||
let MinAlignment = 2 in {
|
||||
def truncstorevi16_align2 : PatFrag<(ops node:$val, node:$ptr),
|
||||
(truncstorevi16 node:$val, node:$ptr)>;
|
||||
def post_truncstvi16_align2 : PatFrag<(ops node:$val, node:$base, node:$offset),
|
||||
(post_truncstvi16 node:$val, node:$base, node:$offset)>;
|
||||
def pre_truncstvi16_align2 : PatFrag<(ops node:$val, node:$base, node:$offset),
|
||||
(pre_truncstvi16 node:$val, node:$base, node:$offset)>;
|
||||
}
|
||||
|
||||
let Predicates = [HasMVEInt] in {
|
||||
@ -4886,6 +4942,20 @@ let Predicates = [HasMVEInt] in {
|
||||
(MVE_VSTRB32 MQPR:$val, t2addrmode_imm7<0>:$addr)>;
|
||||
def : Pat<(truncstorevi16_align2 (v4i32 MQPR:$val), t2addrmode_imm7<1>:$addr),
|
||||
(MVE_VSTRH32 MQPR:$val, t2addrmode_imm7<1>:$addr)>;
|
||||
|
||||
def : Pat<(post_truncstvi8 (v8i16 MQPR:$Rt), tGPR:$Rn, t2am_imm7_offset<0>:$addr),
|
||||
(MVE_VSTRB16_post MQPR:$Rt, tGPR:$Rn, t2am_imm7_offset<0>:$addr)>;
|
||||
def : Pat<(post_truncstvi8 (v4i32 MQPR:$Rt), tGPR:$Rn, t2am_imm7_offset<0>:$addr),
|
||||
(MVE_VSTRB32_post MQPR:$Rt, tGPR:$Rn, t2am_imm7_offset<0>:$addr)>;
|
||||
def : Pat<(post_truncstvi16_align2 (v4i32 MQPR:$Rt), tGPR:$Rn, t2am_imm7_offset<1>:$addr),
|
||||
(MVE_VSTRH32_post MQPR:$Rt, tGPR:$Rn, t2am_imm7_offset<1>:$addr)>;
|
||||
|
||||
def : Pat<(pre_truncstvi8 (v8i16 MQPR:$Rt), tGPR:$Rn, t2am_imm7_offset<0>:$addr),
|
||||
(MVE_VSTRB16_pre MQPR:$Rt, tGPR:$Rn, t2am_imm7_offset<0>:$addr)>;
|
||||
def : Pat<(pre_truncstvi8 (v4i32 MQPR:$Rt), tGPR:$Rn, t2am_imm7_offset<0>:$addr),
|
||||
(MVE_VSTRB32_pre MQPR:$Rt, tGPR:$Rn, t2am_imm7_offset<0>:$addr)>;
|
||||
def : Pat<(pre_truncstvi16_align2 (v4i32 MQPR:$Rt), tGPR:$Rn, t2am_imm7_offset<1>:$addr),
|
||||
(MVE_VSTRH32_pre MQPR:$Rt, tGPR:$Rn, t2am_imm7_offset<1>:$addr)>;
|
||||
}
|
||||
|
||||
|
||||
|
||||
@ -4,8 +4,7 @@
|
||||
define i8* @ldrwu32_4(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrwu32_4:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrw.u32 q0, [r0]
|
||||
; CHECK-NEXT: adds r0, #4
|
||||
; CHECK-NEXT: vldrw.u32 q0, [r0], #4
|
||||
; CHECK-NEXT: vstrw.32 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -20,8 +19,7 @@ entry:
|
||||
define i8* @ldrwu32_3(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrwu32_3:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrw.u32 q0, [r0]
|
||||
; CHECK-NEXT: adds r0, #3
|
||||
; CHECK-NEXT: vldrb.u8 q0, [r0], #3
|
||||
; CHECK-NEXT: vstrw.32 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -36,8 +34,7 @@ entry:
|
||||
define i8* @ldrwu32_m4(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrwu32_m4:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrw.u32 q0, [r0]
|
||||
; CHECK-NEXT: subs r0, #4
|
||||
; CHECK-NEXT: vldrw.u32 q0, [r0], #-4
|
||||
; CHECK-NEXT: vstrw.32 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -52,8 +49,7 @@ entry:
|
||||
define i8* @ldrwu32_508(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrwu32_508:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrw.u32 q0, [r0]
|
||||
; CHECK-NEXT: add.w r0, r0, #508
|
||||
; CHECK-NEXT: vldrw.u32 q0, [r0], #508
|
||||
; CHECK-NEXT: vstrw.32 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -84,8 +80,7 @@ entry:
|
||||
define i8* @ldrwu32_m508(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrwu32_m508:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrw.u32 q0, [r0]
|
||||
; CHECK-NEXT: sub.w r0, r0, #508
|
||||
; CHECK-NEXT: vldrw.u32 q0, [r0], #-508
|
||||
; CHECK-NEXT: vstrw.32 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -117,8 +112,7 @@ entry:
|
||||
define i8* @ldrhu32_4(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrhu32_4:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrh.u32 q0, [r0]
|
||||
; CHECK-NEXT: adds r0, #4
|
||||
; CHECK-NEXT: vldrh.u32 q0, [r0], #4
|
||||
; CHECK-NEXT: vstrw.32 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -151,8 +145,7 @@ entry:
|
||||
define i8* @ldrhu32_2(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrhu32_2:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrh.u32 q0, [r0]
|
||||
; CHECK-NEXT: adds r0, #2
|
||||
; CHECK-NEXT: vldrh.u32 q0, [r0], #2
|
||||
; CHECK-NEXT: vstrw.32 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -168,8 +161,7 @@ entry:
|
||||
define i8* @ldrhu32_254(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrhu32_254:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrh.u32 q0, [r0]
|
||||
; CHECK-NEXT: adds r0, #254
|
||||
; CHECK-NEXT: vldrh.u32 q0, [r0], #254
|
||||
; CHECK-NEXT: vstrw.32 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -203,8 +195,7 @@ entry:
|
||||
define i8* @ldrhs32_4(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrhs32_4:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrh.s32 q0, [r0]
|
||||
; CHECK-NEXT: adds r0, #4
|
||||
; CHECK-NEXT: vldrh.s32 q0, [r0], #4
|
||||
; CHECK-NEXT: vstrw.32 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -237,8 +228,7 @@ entry:
|
||||
define i8* @ldrhs32_2(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrhs32_2:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrh.s32 q0, [r0]
|
||||
; CHECK-NEXT: adds r0, #2
|
||||
; CHECK-NEXT: vldrh.s32 q0, [r0], #2
|
||||
; CHECK-NEXT: vstrw.32 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -254,8 +244,7 @@ entry:
|
||||
define i8* @ldrhs32_254(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrhs32_254:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrh.s32 q0, [r0]
|
||||
; CHECK-NEXT: adds r0, #254
|
||||
; CHECK-NEXT: vldrh.s32 q0, [r0], #254
|
||||
; CHECK-NEXT: vstrw.32 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -289,8 +278,7 @@ entry:
|
||||
define i8* @ldrhu16_4(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrhu16_4:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrh.u16 q0, [r0]
|
||||
; CHECK-NEXT: adds r0, #4
|
||||
; CHECK-NEXT: vldrh.u16 q0, [r0], #4
|
||||
; CHECK-NEXT: vstrh.16 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -305,8 +293,7 @@ entry:
|
||||
define i8* @ldrhu16_3(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrhu16_3:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrh.u16 q0, [r0]
|
||||
; CHECK-NEXT: adds r0, #3
|
||||
; CHECK-NEXT: vldrb.u8 q0, [r0], #3
|
||||
; CHECK-NEXT: vstrh.16 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -321,8 +308,7 @@ entry:
|
||||
define i8* @ldrhu16_2(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrhu16_2:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrh.u16 q0, [r0]
|
||||
; CHECK-NEXT: adds r0, #2
|
||||
; CHECK-NEXT: vldrh.u16 q0, [r0], #2
|
||||
; CHECK-NEXT: vstrh.16 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -337,8 +323,7 @@ entry:
|
||||
define i8* @ldrhu16_254(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrhu16_254:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrh.u16 q0, [r0]
|
||||
; CHECK-NEXT: adds r0, #254
|
||||
; CHECK-NEXT: vldrh.u16 q0, [r0], #254
|
||||
; CHECK-NEXT: vstrh.16 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -370,8 +355,7 @@ entry:
|
||||
define i8* @ldrbu32_4(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrbu32_4:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.u32 q0, [r0]
|
||||
; CHECK-NEXT: adds r0, #4
|
||||
; CHECK-NEXT: vldrb.u32 q0, [r0], #4
|
||||
; CHECK-NEXT: vstrw.32 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -387,8 +371,7 @@ entry:
|
||||
define i8* @ldrbu32_3(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrbu32_3:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.u32 q0, [r0]
|
||||
; CHECK-NEXT: adds r0, #3
|
||||
; CHECK-NEXT: vldrb.u32 q0, [r0], #3
|
||||
; CHECK-NEXT: vstrw.32 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -404,8 +387,7 @@ entry:
|
||||
define i8* @ldrbu32_127(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrbu32_127:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.u32 q0, [r0]
|
||||
; CHECK-NEXT: adds r0, #127
|
||||
; CHECK-NEXT: vldrb.u32 q0, [r0], #127
|
||||
; CHECK-NEXT: vstrw.32 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -439,8 +421,7 @@ entry:
|
||||
define i8* @ldrbs32_4(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrbs32_4:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.s32 q0, [r0]
|
||||
; CHECK-NEXT: adds r0, #4
|
||||
; CHECK-NEXT: vldrb.s32 q0, [r0], #4
|
||||
; CHECK-NEXT: vstrw.32 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -456,8 +437,7 @@ entry:
|
||||
define i8* @ldrbs32_3(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrbs32_3:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.s32 q0, [r0]
|
||||
; CHECK-NEXT: adds r0, #3
|
||||
; CHECK-NEXT: vldrb.s32 q0, [r0], #3
|
||||
; CHECK-NEXT: vstrw.32 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -473,8 +453,7 @@ entry:
|
||||
define i8* @ldrbs32_127(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrbs32_127:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.s32 q0, [r0]
|
||||
; CHECK-NEXT: adds r0, #127
|
||||
; CHECK-NEXT: vldrb.s32 q0, [r0], #127
|
||||
; CHECK-NEXT: vstrw.32 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -508,8 +487,7 @@ entry:
|
||||
define i8* @ldrbu16_4(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrbu16_4:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.u16 q0, [r0]
|
||||
; CHECK-NEXT: adds r0, #4
|
||||
; CHECK-NEXT: vldrb.u16 q0, [r0], #4
|
||||
; CHECK-NEXT: vstrh.16 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -525,8 +503,7 @@ entry:
|
||||
define i8* @ldrbu16_3(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrbu16_3:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.u16 q0, [r0]
|
||||
; CHECK-NEXT: adds r0, #3
|
||||
; CHECK-NEXT: vldrb.u16 q0, [r0], #3
|
||||
; CHECK-NEXT: vstrh.16 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -542,8 +519,7 @@ entry:
|
||||
define i8* @ldrbu16_127(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrbu16_127:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.u16 q0, [r0]
|
||||
; CHECK-NEXT: adds r0, #127
|
||||
; CHECK-NEXT: vldrb.u16 q0, [r0], #127
|
||||
; CHECK-NEXT: vstrh.16 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -577,8 +553,7 @@ entry:
|
||||
define i8* @ldrbs16_4(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrbs16_4:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.s16 q0, [r0]
|
||||
; CHECK-NEXT: adds r0, #4
|
||||
; CHECK-NEXT: vldrb.s16 q0, [r0], #4
|
||||
; CHECK-NEXT: vstrh.16 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -594,8 +569,7 @@ entry:
|
||||
define i8* @ldrbs16_3(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrbs16_3:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.s16 q0, [r0]
|
||||
; CHECK-NEXT: adds r0, #3
|
||||
; CHECK-NEXT: vldrb.s16 q0, [r0], #3
|
||||
; CHECK-NEXT: vstrh.16 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -611,8 +585,7 @@ entry:
|
||||
define i8* @ldrbs16_127(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrbs16_127:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.s16 q0, [r0]
|
||||
; CHECK-NEXT: adds r0, #127
|
||||
; CHECK-NEXT: vldrb.s16 q0, [r0], #127
|
||||
; CHECK-NEXT: vstrh.16 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -646,8 +619,7 @@ entry:
|
||||
define i8* @ldrbu8_4(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrbu8_4:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.u8 q0, [r0]
|
||||
; CHECK-NEXT: adds r0, #4
|
||||
; CHECK-NEXT: vldrb.u8 q0, [r0], #4
|
||||
; CHECK-NEXT: vstrb.8 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -662,8 +634,7 @@ entry:
|
||||
define i8* @ldrbu8_3(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrbu8_3:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.u8 q0, [r0]
|
||||
; CHECK-NEXT: adds r0, #3
|
||||
; CHECK-NEXT: vldrb.u8 q0, [r0], #3
|
||||
; CHECK-NEXT: vstrb.8 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -678,8 +649,7 @@ entry:
|
||||
define i8* @ldrbu8_127(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrbu8_127:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.u8 q0, [r0]
|
||||
; CHECK-NEXT: adds r0, #127
|
||||
; CHECK-NEXT: vldrb.u8 q0, [r0], #127
|
||||
; CHECK-NEXT: vstrb.8 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -710,8 +680,7 @@ entry:
|
||||
define i8* @ldrwf32_4(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrwf32_4:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrw.u32 q0, [r0]
|
||||
; CHECK-NEXT: adds r0, #4
|
||||
; CHECK-NEXT: vldrw.u32 q0, [r0], #4
|
||||
; CHECK-NEXT: vstrw.32 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -726,8 +695,7 @@ entry:
|
||||
define i8* @ldrwf16_4(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrwf16_4:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrh.u16 q0, [r0]
|
||||
; CHECK-NEXT: adds r0, #4
|
||||
; CHECK-NEXT: vldrh.u16 q0, [r0], #4
|
||||
; CHECK-NEXT: vstrh.16 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -742,8 +710,7 @@ entry:
|
||||
define i8* @ldrwi32_align1(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrwi32_align1:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.u8 q0, [r0]
|
||||
; CHECK-NEXT: adds r0, #3
|
||||
; CHECK-NEXT: vldrb.u8 q0, [r0], #3
|
||||
; CHECK-NEXT: vstrw.32 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -758,8 +725,7 @@ entry:
|
||||
define i8* @ldrhi16_align1(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrhi16_align1:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.u8 q0, [r0]
|
||||
; CHECK-NEXT: adds r0, #3
|
||||
; CHECK-NEXT: vldrb.u8 q0, [r0], #3
|
||||
; CHECK-NEXT: vstrh.16 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -798,8 +764,7 @@ entry:
|
||||
define i8* @ldrf32_align1(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrf32_align1:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.u8 q0, [r0]
|
||||
; CHECK-NEXT: adds r0, #3
|
||||
; CHECK-NEXT: vldrb.u8 q0, [r0], #3
|
||||
; CHECK-NEXT: vstrw.32 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -814,8 +779,7 @@ entry:
|
||||
define i8* @ldrf16_align1(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrf16_align1:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.u8 q0, [r0]
|
||||
; CHECK-NEXT: adds r0, #3
|
||||
; CHECK-NEXT: vldrb.u8 q0, [r0], #3
|
||||
; CHECK-NEXT: vstrh.16 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -835,8 +799,7 @@ define i8* @strw32_4(i8* %y, i8* %x) {
|
||||
; CHECK-LABEL: strw32_4:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrw.u32 q0, [r1]
|
||||
; CHECK-NEXT: vstrw.32 q0, [r0]
|
||||
; CHECK-NEXT: adds r0, #4
|
||||
; CHECK-NEXT: vstrb.8 q0, [r0], #4
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = getelementptr inbounds i8, i8* %y, i32 4
|
||||
@ -851,8 +814,7 @@ define i8* @strw32_3(i8* %y, i8* %x) {
|
||||
; CHECK-LABEL: strw32_3:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrw.u32 q0, [r1]
|
||||
; CHECK-NEXT: vstrw.32 q0, [r0]
|
||||
; CHECK-NEXT: adds r0, #3
|
||||
; CHECK-NEXT: vstrb.8 q0, [r0], #3
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = getelementptr inbounds i8, i8* %y, i32 3
|
||||
@ -867,8 +829,7 @@ define i8* @strw32_m4(i8* %y, i8* %x) {
|
||||
; CHECK-LABEL: strw32_m4:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrw.u32 q0, [r1]
|
||||
; CHECK-NEXT: vstrw.32 q0, [r0]
|
||||
; CHECK-NEXT: subs r0, #4
|
||||
; CHECK-NEXT: vstrb.8 q0, [r0], #-4
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = getelementptr inbounds i8, i8* %y, i32 -4
|
||||
@ -883,8 +844,7 @@ define i8* @strw32_508(i8* %y, i8* %x) {
|
||||
; CHECK-LABEL: strw32_508:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrw.u32 q0, [r1]
|
||||
; CHECK-NEXT: vstrw.32 q0, [r0]
|
||||
; CHECK-NEXT: add.w r0, r0, #508
|
||||
; CHECK-NEXT: vstrw.32 q0, [r0], #508
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = getelementptr inbounds i8, i8* %y, i32 508
|
||||
@ -915,8 +875,7 @@ define i8* @strw32_m508(i8* %y, i8* %x) {
|
||||
; CHECK-LABEL: strw32_m508:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrw.u32 q0, [r1]
|
||||
; CHECK-NEXT: vstrw.32 q0, [r0]
|
||||
; CHECK-NEXT: sub.w r0, r0, #508
|
||||
; CHECK-NEXT: vstrw.32 q0, [r0], #-508
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = getelementptr inbounds i8, i8* %y, i32 -508
|
||||
@ -948,8 +907,7 @@ define i8* @strh32_4(i8* %y, i8* %x) {
|
||||
; CHECK-LABEL: strh32_4:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrh.u32 q0, [r1]
|
||||
; CHECK-NEXT: vstrh.32 q0, [r0]
|
||||
; CHECK-NEXT: adds r0, #4
|
||||
; CHECK-NEXT: vstrh.32 q0, [r0], #4
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = getelementptr inbounds i8, i8* %y, i32 4
|
||||
@ -980,8 +938,7 @@ define i8* @strh32_2(i8* %y, i8* %x) {
|
||||
; CHECK-LABEL: strh32_2:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrh.u32 q0, [r1]
|
||||
; CHECK-NEXT: vstrh.32 q0, [r0]
|
||||
; CHECK-NEXT: adds r0, #2
|
||||
; CHECK-NEXT: vstrh.32 q0, [r0], #2
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = getelementptr inbounds i8, i8* %y, i32 2
|
||||
@ -996,8 +953,7 @@ define i8* @strh32_254(i8* %y, i8* %x) {
|
||||
; CHECK-LABEL: strh32_254:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrh.u32 q0, [r1]
|
||||
; CHECK-NEXT: vstrh.32 q0, [r0]
|
||||
; CHECK-NEXT: adds r0, #254
|
||||
; CHECK-NEXT: vstrh.32 q0, [r0], #254
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = getelementptr inbounds i8, i8* %y, i32 254
|
||||
@ -1029,8 +985,7 @@ define i8* @strh16_4(i8* %y, i8* %x) {
|
||||
; CHECK-LABEL: strh16_4:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrh.u16 q0, [r1]
|
||||
; CHECK-NEXT: vstrh.16 q0, [r0]
|
||||
; CHECK-NEXT: adds r0, #4
|
||||
; CHECK-NEXT: vstrb.8 q0, [r0], #4
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = getelementptr inbounds i8, i8* %y, i32 4
|
||||
@ -1045,8 +1000,7 @@ define i8* @strh16_3(i8* %y, i8* %x) {
|
||||
; CHECK-LABEL: strh16_3:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrh.u16 q0, [r1]
|
||||
; CHECK-NEXT: vstrh.16 q0, [r0]
|
||||
; CHECK-NEXT: adds r0, #3
|
||||
; CHECK-NEXT: vstrb.8 q0, [r0], #3
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = getelementptr inbounds i8, i8* %y, i32 3
|
||||
@ -1061,8 +1015,7 @@ define i8* @strh16_2(i8* %y, i8* %x) {
|
||||
; CHECK-LABEL: strh16_2:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrh.u16 q0, [r1]
|
||||
; CHECK-NEXT: vstrh.16 q0, [r0]
|
||||
; CHECK-NEXT: adds r0, #2
|
||||
; CHECK-NEXT: vstrb.8 q0, [r0], #2
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = getelementptr inbounds i8, i8* %y, i32 2
|
||||
@ -1077,8 +1030,7 @@ define i8* @strh16_254(i8* %y, i8* %x) {
|
||||
; CHECK-LABEL: strh16_254:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrh.u16 q0, [r1]
|
||||
; CHECK-NEXT: vstrh.16 q0, [r0]
|
||||
; CHECK-NEXT: adds r0, #254
|
||||
; CHECK-NEXT: vstrh.16 q0, [r0], #254
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = getelementptr inbounds i8, i8* %y, i32 254
|
||||
@ -1110,8 +1062,7 @@ define i8* @strb32_4(i8* %y, i8* %x) {
|
||||
; CHECK-LABEL: strb32_4:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.u32 q0, [r1]
|
||||
; CHECK-NEXT: vstrb.32 q0, [r0]
|
||||
; CHECK-NEXT: adds r0, #4
|
||||
; CHECK-NEXT: vstrb.32 q0, [r0], #4
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = getelementptr inbounds i8, i8* %y, i32 4
|
||||
@ -1126,8 +1077,7 @@ define i8* @strb32_3(i8* %y, i8* %x) {
|
||||
; CHECK-LABEL: strb32_3:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.u32 q0, [r1]
|
||||
; CHECK-NEXT: vstrb.32 q0, [r0]
|
||||
; CHECK-NEXT: adds r0, #3
|
||||
; CHECK-NEXT: vstrb.32 q0, [r0], #3
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = getelementptr inbounds i8, i8* %y, i32 3
|
||||
@ -1142,8 +1092,7 @@ define i8* @strb32_127(i8* %y, i8* %x) {
|
||||
; CHECK-LABEL: strb32_127:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.u32 q0, [r1]
|
||||
; CHECK-NEXT: vstrb.32 q0, [r0]
|
||||
; CHECK-NEXT: adds r0, #127
|
||||
; CHECK-NEXT: vstrb.32 q0, [r0], #127
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = getelementptr inbounds i8, i8* %y, i32 127
|
||||
@ -1175,8 +1124,7 @@ define i8* @strb16_4(i8* %y, i8* %x) {
|
||||
; CHECK-LABEL: strb16_4:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.u16 q0, [r1]
|
||||
; CHECK-NEXT: vstrb.16 q0, [r0]
|
||||
; CHECK-NEXT: adds r0, #4
|
||||
; CHECK-NEXT: vstrb.16 q0, [r0], #4
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = getelementptr inbounds i8, i8* %y, i32 4
|
||||
@ -1191,8 +1139,7 @@ define i8* @strb16_3(i8* %y, i8* %x) {
|
||||
; CHECK-LABEL: strb16_3:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.u16 q0, [r1]
|
||||
; CHECK-NEXT: vstrb.16 q0, [r0]
|
||||
; CHECK-NEXT: adds r0, #3
|
||||
; CHECK-NEXT: vstrb.16 q0, [r0], #3
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = getelementptr inbounds i8, i8* %y, i32 3
|
||||
@ -1207,8 +1154,7 @@ define i8* @strb16_127(i8* %y, i8* %x) {
|
||||
; CHECK-LABEL: strb16_127:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.u16 q0, [r1]
|
||||
; CHECK-NEXT: vstrb.16 q0, [r0]
|
||||
; CHECK-NEXT: adds r0, #127
|
||||
; CHECK-NEXT: vstrb.16 q0, [r0], #127
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = getelementptr inbounds i8, i8* %y, i32 127
|
||||
@ -1240,8 +1186,7 @@ define i8* @strb8_4(i8* %y, i8* %x) {
|
||||
; CHECK-LABEL: strb8_4:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.u8 q0, [r1]
|
||||
; CHECK-NEXT: vstrb.8 q0, [r0]
|
||||
; CHECK-NEXT: adds r0, #4
|
||||
; CHECK-NEXT: vstrb.8 q0, [r0], #4
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = getelementptr inbounds i8, i8* %y, i32 4
|
||||
@ -1256,8 +1201,7 @@ define i8* @strb8_3(i8* %y, i8* %x) {
|
||||
; CHECK-LABEL: strb8_3:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.u8 q0, [r1]
|
||||
; CHECK-NEXT: vstrb.8 q0, [r0]
|
||||
; CHECK-NEXT: adds r0, #3
|
||||
; CHECK-NEXT: vstrb.8 q0, [r0], #3
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = getelementptr inbounds i8, i8* %y, i32 3
|
||||
@ -1272,8 +1216,7 @@ define i8* @strb8_127(i8* %y, i8* %x) {
|
||||
; CHECK-LABEL: strb8_127:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.u8 q0, [r1]
|
||||
; CHECK-NEXT: vstrb.8 q0, [r0]
|
||||
; CHECK-NEXT: adds r0, #127
|
||||
; CHECK-NEXT: vstrb.8 q0, [r0], #127
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = getelementptr inbounds i8, i8* %y, i32 127
|
||||
@ -1304,8 +1247,7 @@ define i8* @strf32_4(i8* %y, i8* %x) {
|
||||
; CHECK-LABEL: strf32_4:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrw.u32 q0, [r1]
|
||||
; CHECK-NEXT: vstrw.32 q0, [r0]
|
||||
; CHECK-NEXT: adds r0, #4
|
||||
; CHECK-NEXT: vstrb.8 q0, [r0], #4
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = getelementptr inbounds i8, i8* %y, i32 4
|
||||
@ -1320,8 +1262,7 @@ define i8* @strf16_4(i8* %y, i8* %x) {
|
||||
; CHECK-LABEL: strf16_4:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrh.u16 q0, [r1]
|
||||
; CHECK-NEXT: vstrh.16 q0, [r0]
|
||||
; CHECK-NEXT: adds r0, #4
|
||||
; CHECK-NEXT: vstrb.8 q0, [r0], #4
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = getelementptr inbounds i8, i8* %y, i32 4
|
||||
@ -1336,8 +1277,7 @@ define i8* @strwi32_align1(i8* %y, i8* %x) {
|
||||
; CHECK-LABEL: strwi32_align1:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrw.u32 q0, [r1]
|
||||
; CHECK-NEXT: vstrb.8 q0, [r0]
|
||||
; CHECK-NEXT: adds r0, #3
|
||||
; CHECK-NEXT: vstrb.8 q0, [r0], #3
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = getelementptr inbounds i8, i8* %y, i32 3
|
||||
@ -1352,8 +1292,7 @@ define i8* @strhi16_align1(i8* %y, i8* %x) {
|
||||
; CHECK-LABEL: strhi16_align1:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrh.u16 q0, [r1]
|
||||
; CHECK-NEXT: vstrb.8 q0, [r0]
|
||||
; CHECK-NEXT: adds r0, #3
|
||||
; CHECK-NEXT: vstrb.8 q0, [r0], #3
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = getelementptr inbounds i8, i8* %y, i32 3
|
||||
@ -1392,8 +1331,7 @@ define i8* @strf32_align1(i8* %y, i8* %x) {
|
||||
; CHECK-LABEL: strf32_align1:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrw.u32 q0, [r1]
|
||||
; CHECK-NEXT: vstrb.8 q0, [r0]
|
||||
; CHECK-NEXT: adds r0, #3
|
||||
; CHECK-NEXT: vstrb.8 q0, [r0], #3
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = getelementptr inbounds i8, i8* %y, i32 3
|
||||
@ -1408,8 +1346,7 @@ define i8* @strf16_align1(i8* %y, i8* %x) {
|
||||
; CHECK-LABEL: strf16_align1:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrh.u16 q0, [r1]
|
||||
; CHECK-NEXT: vstrb.8 q0, [r0]
|
||||
; CHECK-NEXT: adds r0, #3
|
||||
; CHECK-NEXT: vstrb.8 q0, [r0], #3
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = getelementptr inbounds i8, i8* %y, i32 3
|
||||
|
||||
@ -4,8 +4,7 @@
|
||||
define i8* @ldrwu32_4(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrwu32_4:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrw.u32 q0, [r0, #4]
|
||||
; CHECK-NEXT: adds r0, #4
|
||||
; CHECK-NEXT: vldrw.u32 q0, [r0, #4]!
|
||||
; CHECK-NEXT: vstrw.32 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -20,8 +19,7 @@ entry:
|
||||
define i8* @ldrwu32_3(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrwu32_3:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: adds r0, #3
|
||||
; CHECK-NEXT: vldrw.u32 q0, [r0]
|
||||
; CHECK-NEXT: vldrb.u8 q0, [r0, #3]!
|
||||
; CHECK-NEXT: vstrw.32 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -36,8 +34,7 @@ entry:
|
||||
define i8* @ldrwu32_m4(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrwu32_m4:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrw.u32 q0, [r0, #-4]
|
||||
; CHECK-NEXT: subs r0, #4
|
||||
; CHECK-NEXT: vldrw.u32 q0, [r0, #-4]!
|
||||
; CHECK-NEXT: vstrw.32 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -52,8 +49,7 @@ entry:
|
||||
define i8* @ldrwu32_508(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrwu32_508:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: add.w r0, r0, #508
|
||||
; CHECK-NEXT: vldrw.u32 q0, [r0]
|
||||
; CHECK-NEXT: vldrw.u32 q0, [r0, #508]!
|
||||
; CHECK-NEXT: vstrw.32 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -84,8 +80,7 @@ entry:
|
||||
define i8* @ldrwu32_m508(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrwu32_m508:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: sub.w r0, r0, #508
|
||||
; CHECK-NEXT: vldrw.u32 q0, [r0]
|
||||
; CHECK-NEXT: vldrw.u32 q0, [r0, #-508]!
|
||||
; CHECK-NEXT: vstrw.32 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -117,8 +112,7 @@ entry:
|
||||
define i8* @ldrhu32_4(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrhu32_4:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrh.u32 q0, [r0, #4]
|
||||
; CHECK-NEXT: adds r0, #4
|
||||
; CHECK-NEXT: vldrh.u32 q0, [r0, #4]!
|
||||
; CHECK-NEXT: vstrw.32 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -151,8 +145,7 @@ entry:
|
||||
define i8* @ldrhu32_2(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrhu32_2:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrh.u32 q0, [r0, #2]
|
||||
; CHECK-NEXT: adds r0, #2
|
||||
; CHECK-NEXT: vldrh.u32 q0, [r0, #2]!
|
||||
; CHECK-NEXT: vstrw.32 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -168,8 +161,7 @@ entry:
|
||||
define i8* @ldrhu32_254(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrhu32_254:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: adds r0, #254
|
||||
; CHECK-NEXT: vldrh.u32 q0, [r0]
|
||||
; CHECK-NEXT: vldrh.u32 q0, [r0, #254]!
|
||||
; CHECK-NEXT: vstrw.32 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -203,8 +195,7 @@ entry:
|
||||
define i8* @ldrhs32_4(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrhs32_4:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrh.s32 q0, [r0, #4]
|
||||
; CHECK-NEXT: adds r0, #4
|
||||
; CHECK-NEXT: vldrh.s32 q0, [r0, #4]!
|
||||
; CHECK-NEXT: vstrw.32 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -237,8 +228,7 @@ entry:
|
||||
define i8* @ldrhs32_2(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrhs32_2:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrh.s32 q0, [r0, #2]
|
||||
; CHECK-NEXT: adds r0, #2
|
||||
; CHECK-NEXT: vldrh.s32 q0, [r0, #2]!
|
||||
; CHECK-NEXT: vstrw.32 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -254,8 +244,7 @@ entry:
|
||||
define i8* @ldrhs32_254(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrhs32_254:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: adds r0, #254
|
||||
; CHECK-NEXT: vldrh.s32 q0, [r0]
|
||||
; CHECK-NEXT: vldrh.s32 q0, [r0, #254]!
|
||||
; CHECK-NEXT: vstrw.32 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -289,8 +278,7 @@ entry:
|
||||
define i8* @ldrhu16_4(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrhu16_4:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrh.u16 q0, [r0, #4]
|
||||
; CHECK-NEXT: adds r0, #4
|
||||
; CHECK-NEXT: vldrh.u16 q0, [r0, #4]!
|
||||
; CHECK-NEXT: vstrh.16 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -305,8 +293,7 @@ entry:
|
||||
define i8* @ldrhu16_3(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrhu16_3:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: adds r0, #3
|
||||
; CHECK-NEXT: vldrh.u16 q0, [r0]
|
||||
; CHECK-NEXT: vldrb.u8 q0, [r0, #3]!
|
||||
; CHECK-NEXT: vstrh.16 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -321,8 +308,7 @@ entry:
|
||||
define i8* @ldrhu16_2(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrhu16_2:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrh.u16 q0, [r0, #2]
|
||||
; CHECK-NEXT: adds r0, #2
|
||||
; CHECK-NEXT: vldrh.u16 q0, [r0, #2]!
|
||||
; CHECK-NEXT: vstrh.16 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -337,8 +323,7 @@ entry:
|
||||
define i8* @ldrhu16_254(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrhu16_254:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: adds r0, #254
|
||||
; CHECK-NEXT: vldrh.u16 q0, [r0]
|
||||
; CHECK-NEXT: vldrh.u16 q0, [r0, #254]!
|
||||
; CHECK-NEXT: vstrh.16 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -370,8 +355,7 @@ entry:
|
||||
define i8* @ldrbu32_4(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrbu32_4:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.u32 q0, [r0, #4]
|
||||
; CHECK-NEXT: adds r0, #4
|
||||
; CHECK-NEXT: vldrb.u32 q0, [r0, #4]!
|
||||
; CHECK-NEXT: vstrw.32 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -387,8 +371,7 @@ entry:
|
||||
define i8* @ldrbu32_3(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrbu32_3:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.u32 q0, [r0, #3]
|
||||
; CHECK-NEXT: adds r0, #3
|
||||
; CHECK-NEXT: vldrb.u32 q0, [r0, #3]!
|
||||
; CHECK-NEXT: vstrw.32 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -404,8 +387,7 @@ entry:
|
||||
define i8* @ldrbu32_127(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrbu32_127:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: adds r0, #127
|
||||
; CHECK-NEXT: vldrb.u32 q0, [r0]
|
||||
; CHECK-NEXT: vldrb.u32 q0, [r0, #127]!
|
||||
; CHECK-NEXT: vstrw.32 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -439,8 +421,7 @@ entry:
|
||||
define i8* @ldrbs32_4(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrbs32_4:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.s32 q0, [r0, #4]
|
||||
; CHECK-NEXT: adds r0, #4
|
||||
; CHECK-NEXT: vldrb.s32 q0, [r0, #4]!
|
||||
; CHECK-NEXT: vstrw.32 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -456,8 +437,7 @@ entry:
|
||||
define i8* @ldrbs32_3(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrbs32_3:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.s32 q0, [r0, #3]
|
||||
; CHECK-NEXT: adds r0, #3
|
||||
; CHECK-NEXT: vldrb.s32 q0, [r0, #3]!
|
||||
; CHECK-NEXT: vstrw.32 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -473,8 +453,7 @@ entry:
|
||||
define i8* @ldrbs32_127(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrbs32_127:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: adds r0, #127
|
||||
; CHECK-NEXT: vldrb.s32 q0, [r0]
|
||||
; CHECK-NEXT: vldrb.s32 q0, [r0, #127]!
|
||||
; CHECK-NEXT: vstrw.32 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -508,8 +487,7 @@ entry:
|
||||
define i8* @ldrbu16_4(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrbu16_4:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.u16 q0, [r0, #4]
|
||||
; CHECK-NEXT: adds r0, #4
|
||||
; CHECK-NEXT: vldrb.u16 q0, [r0, #4]!
|
||||
; CHECK-NEXT: vstrh.16 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -525,8 +503,7 @@ entry:
|
||||
define i8* @ldrbu16_3(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrbu16_3:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.u16 q0, [r0, #3]
|
||||
; CHECK-NEXT: adds r0, #3
|
||||
; CHECK-NEXT: vldrb.u16 q0, [r0, #3]!
|
||||
; CHECK-NEXT: vstrh.16 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -542,8 +519,7 @@ entry:
|
||||
define i8* @ldrbu16_127(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrbu16_127:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: adds r0, #127
|
||||
; CHECK-NEXT: vldrb.u16 q0, [r0]
|
||||
; CHECK-NEXT: vldrb.u16 q0, [r0, #127]!
|
||||
; CHECK-NEXT: vstrh.16 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -577,8 +553,7 @@ entry:
|
||||
define i8* @ldrbs16_4(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrbs16_4:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.s16 q0, [r0, #4]
|
||||
; CHECK-NEXT: adds r0, #4
|
||||
; CHECK-NEXT: vldrb.s16 q0, [r0, #4]!
|
||||
; CHECK-NEXT: vstrh.16 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -594,8 +569,7 @@ entry:
|
||||
define i8* @ldrbs16_3(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrbs16_3:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.s16 q0, [r0, #3]
|
||||
; CHECK-NEXT: adds r0, #3
|
||||
; CHECK-NEXT: vldrb.s16 q0, [r0, #3]!
|
||||
; CHECK-NEXT: vstrh.16 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -611,8 +585,7 @@ entry:
|
||||
define i8* @ldrbs16_127(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrbs16_127:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: adds r0, #127
|
||||
; CHECK-NEXT: vldrb.s16 q0, [r0]
|
||||
; CHECK-NEXT: vldrb.s16 q0, [r0, #127]!
|
||||
; CHECK-NEXT: vstrh.16 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -646,8 +619,7 @@ entry:
|
||||
define i8* @ldrbu8_4(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrbu8_4:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.u8 q0, [r0, #4]
|
||||
; CHECK-NEXT: adds r0, #4
|
||||
; CHECK-NEXT: vldrb.u8 q0, [r0, #4]!
|
||||
; CHECK-NEXT: vstrb.8 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -662,8 +634,7 @@ entry:
|
||||
define i8* @ldrbu8_3(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrbu8_3:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.u8 q0, [r0, #3]
|
||||
; CHECK-NEXT: adds r0, #3
|
||||
; CHECK-NEXT: vldrb.u8 q0, [r0, #3]!
|
||||
; CHECK-NEXT: vstrb.8 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -678,8 +649,7 @@ entry:
|
||||
define i8* @ldrbu8_127(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrbu8_127:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: adds r0, #127
|
||||
; CHECK-NEXT: vldrb.u8 q0, [r0]
|
||||
; CHECK-NEXT: vldrb.u8 q0, [r0, #127]!
|
||||
; CHECK-NEXT: vstrb.8 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -710,8 +680,7 @@ entry:
|
||||
define i8* @ldrwf32_4(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrwf32_4:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrw.u32 q0, [r0, #4]
|
||||
; CHECK-NEXT: adds r0, #4
|
||||
; CHECK-NEXT: vldrw.u32 q0, [r0, #4]!
|
||||
; CHECK-NEXT: vstrw.32 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -726,8 +695,7 @@ entry:
|
||||
define i8* @ldrwf16_4(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrwf16_4:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrh.u16 q0, [r0, #4]
|
||||
; CHECK-NEXT: adds r0, #4
|
||||
; CHECK-NEXT: vldrh.u16 q0, [r0, #4]!
|
||||
; CHECK-NEXT: vstrh.16 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -742,8 +710,7 @@ entry:
|
||||
define i8* @ldrwi32_align1(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrwi32_align1:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.u8 q0, [r0, #3]
|
||||
; CHECK-NEXT: adds r0, #3
|
||||
; CHECK-NEXT: vldrb.u8 q0, [r0, #3]!
|
||||
; CHECK-NEXT: vstrw.32 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -758,8 +725,7 @@ entry:
|
||||
define i8* @ldrhi16_align1(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrhi16_align1:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.u8 q0, [r0, #3]
|
||||
; CHECK-NEXT: adds r0, #3
|
||||
; CHECK-NEXT: vldrb.u8 q0, [r0, #3]!
|
||||
; CHECK-NEXT: vstrh.16 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -798,8 +764,7 @@ entry:
|
||||
define i8* @ldrf32_align1(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrf32_align1:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.u8 q0, [r0, #3]
|
||||
; CHECK-NEXT: adds r0, #3
|
||||
; CHECK-NEXT: vldrb.u8 q0, [r0, #3]!
|
||||
; CHECK-NEXT: vstrw.32 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -814,8 +779,7 @@ entry:
|
||||
define i8* @ldrf16_align1(i8* %x, i8* %y) {
|
||||
; CHECK-LABEL: ldrf16_align1:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.u8 q0, [r0, #3]
|
||||
; CHECK-NEXT: adds r0, #3
|
||||
; CHECK-NEXT: vldrb.u8 q0, [r0, #3]!
|
||||
; CHECK-NEXT: vstrh.16 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -835,8 +799,7 @@ define i8* @strw32_4(i8* %y, i8* %x) {
|
||||
; CHECK-LABEL: strw32_4:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrw.u32 q0, [r1]
|
||||
; CHECK-NEXT: vstrw.32 q0, [r0, #4]
|
||||
; CHECK-NEXT: adds r0, #4
|
||||
; CHECK-NEXT: vstrb.8 q0, [r0, #4]!
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = getelementptr inbounds i8, i8* %y, i32 4
|
||||
@ -850,9 +813,8 @@ entry:
|
||||
define i8* @strw32_3(i8* %y, i8* %x) {
|
||||
; CHECK-LABEL: strw32_3:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: adds r0, #3
|
||||
; CHECK-NEXT: vldrw.u32 q0, [r1]
|
||||
; CHECK-NEXT: vstrw.32 q0, [r0]
|
||||
; CHECK-NEXT: vstrb.8 q0, [r0, #3]!
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = getelementptr inbounds i8, i8* %y, i32 3
|
||||
@ -867,8 +829,7 @@ define i8* @strw32_m4(i8* %y, i8* %x) {
|
||||
; CHECK-LABEL: strw32_m4:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrw.u32 q0, [r1]
|
||||
; CHECK-NEXT: vstrw.32 q0, [r0, #-4]
|
||||
; CHECK-NEXT: subs r0, #4
|
||||
; CHECK-NEXT: vstrb.8 q0, [r0, #-4]!
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = getelementptr inbounds i8, i8* %y, i32 -4
|
||||
@ -882,9 +843,8 @@ entry:
|
||||
define i8* @strw32_508(i8* %y, i8* %x) {
|
||||
; CHECK-LABEL: strw32_508:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: add.w r0, r0, #508
|
||||
; CHECK-NEXT: vldrw.u32 q0, [r1]
|
||||
; CHECK-NEXT: vstrw.32 q0, [r0]
|
||||
; CHECK-NEXT: vstrw.32 q0, [r0, #508]!
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = getelementptr inbounds i8, i8* %y, i32 508
|
||||
@ -914,9 +874,8 @@ entry:
|
||||
define i8* @strw32_m508(i8* %y, i8* %x) {
|
||||
; CHECK-LABEL: strw32_m508:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: sub.w r0, r0, #508
|
||||
; CHECK-NEXT: vldrw.u32 q0, [r1]
|
||||
; CHECK-NEXT: vstrw.32 q0, [r0]
|
||||
; CHECK-NEXT: vstrw.32 q0, [r0, #-508]!
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = getelementptr inbounds i8, i8* %y, i32 -508
|
||||
@ -948,8 +907,7 @@ define i8* @strh32_4(i8* %y, i8* %x) {
|
||||
; CHECK-LABEL: strh32_4:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrh.u32 q0, [r1]
|
||||
; CHECK-NEXT: vstrh.32 q0, [r0, #4]
|
||||
; CHECK-NEXT: adds r0, #4
|
||||
; CHECK-NEXT: vstrh.32 q0, [r0, #4]!
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = getelementptr inbounds i8, i8* %y, i32 4
|
||||
@ -980,8 +938,7 @@ define i8* @strh32_2(i8* %y, i8* %x) {
|
||||
; CHECK-LABEL: strh32_2:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrh.u32 q0, [r1]
|
||||
; CHECK-NEXT: vstrh.32 q0, [r0, #2]
|
||||
; CHECK-NEXT: adds r0, #2
|
||||
; CHECK-NEXT: vstrh.32 q0, [r0, #2]!
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = getelementptr inbounds i8, i8* %y, i32 2
|
||||
@ -995,9 +952,8 @@ entry:
|
||||
define i8* @strh32_254(i8* %y, i8* %x) {
|
||||
; CHECK-LABEL: strh32_254:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: adds r0, #254
|
||||
; CHECK-NEXT: vldrh.u32 q0, [r1]
|
||||
; CHECK-NEXT: vstrh.32 q0, [r0]
|
||||
; CHECK-NEXT: vstrh.32 q0, [r0, #254]!
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = getelementptr inbounds i8, i8* %y, i32 254
|
||||
@ -1029,8 +985,7 @@ define i8* @strh16_4(i8* %y, i8* %x) {
|
||||
; CHECK-LABEL: strh16_4:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrh.u16 q0, [r1]
|
||||
; CHECK-NEXT: vstrh.16 q0, [r0, #4]
|
||||
; CHECK-NEXT: adds r0, #4
|
||||
; CHECK-NEXT: vstrb.8 q0, [r0, #4]!
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = getelementptr inbounds i8, i8* %y, i32 4
|
||||
@ -1044,9 +999,8 @@ entry:
|
||||
define i8* @strh16_3(i8* %y, i8* %x) {
|
||||
; CHECK-LABEL: strh16_3:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: adds r0, #3
|
||||
; CHECK-NEXT: vldrh.u16 q0, [r1]
|
||||
; CHECK-NEXT: vstrh.16 q0, [r0]
|
||||
; CHECK-NEXT: vstrb.8 q0, [r0, #3]!
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = getelementptr inbounds i8, i8* %y, i32 3
|
||||
@ -1061,8 +1015,7 @@ define i8* @strh16_2(i8* %y, i8* %x) {
|
||||
; CHECK-LABEL: strh16_2:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrh.u16 q0, [r1]
|
||||
; CHECK-NEXT: vstrh.16 q0, [r0, #2]
|
||||
; CHECK-NEXT: adds r0, #2
|
||||
; CHECK-NEXT: vstrb.8 q0, [r0, #2]!
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = getelementptr inbounds i8, i8* %y, i32 2
|
||||
@ -1076,9 +1029,8 @@ entry:
|
||||
define i8* @strh16_254(i8* %y, i8* %x) {
|
||||
; CHECK-LABEL: strh16_254:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: adds r0, #254
|
||||
; CHECK-NEXT: vldrh.u16 q0, [r1]
|
||||
; CHECK-NEXT: vstrh.16 q0, [r0]
|
||||
; CHECK-NEXT: vstrh.16 q0, [r0, #254]!
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = getelementptr inbounds i8, i8* %y, i32 254
|
||||
@ -1110,8 +1062,7 @@ define i8* @strb32_4(i8* %y, i8* %x) {
|
||||
; CHECK-LABEL: strb32_4:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.u32 q0, [r1]
|
||||
; CHECK-NEXT: vstrb.32 q0, [r0, #4]
|
||||
; CHECK-NEXT: adds r0, #4
|
||||
; CHECK-NEXT: vstrb.32 q0, [r0, #4]!
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = getelementptr inbounds i8, i8* %y, i32 4
|
||||
@ -1126,8 +1077,7 @@ define i8* @strb32_3(i8* %y, i8* %x) {
|
||||
; CHECK-LABEL: strb32_3:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.u32 q0, [r1]
|
||||
; CHECK-NEXT: vstrb.32 q0, [r0, #3]
|
||||
; CHECK-NEXT: adds r0, #3
|
||||
; CHECK-NEXT: vstrb.32 q0, [r0, #3]!
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = getelementptr inbounds i8, i8* %y, i32 3
|
||||
@ -1141,9 +1091,8 @@ entry:
|
||||
define i8* @strb32_127(i8* %y, i8* %x) {
|
||||
; CHECK-LABEL: strb32_127:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: adds r0, #127
|
||||
; CHECK-NEXT: vldrb.u32 q0, [r1]
|
||||
; CHECK-NEXT: vstrb.32 q0, [r0]
|
||||
; CHECK-NEXT: vstrb.32 q0, [r0, #127]!
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = getelementptr inbounds i8, i8* %y, i32 127
|
||||
@ -1175,8 +1124,7 @@ define i8* @strb16_4(i8* %y, i8* %x) {
|
||||
; CHECK-LABEL: strb16_4:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.u16 q0, [r1]
|
||||
; CHECK-NEXT: vstrb.16 q0, [r0, #4]
|
||||
; CHECK-NEXT: adds r0, #4
|
||||
; CHECK-NEXT: vstrb.16 q0, [r0, #4]!
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = getelementptr inbounds i8, i8* %y, i32 4
|
||||
@ -1191,8 +1139,7 @@ define i8* @strb16_3(i8* %y, i8* %x) {
|
||||
; CHECK-LABEL: strb16_3:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.u16 q0, [r1]
|
||||
; CHECK-NEXT: vstrb.16 q0, [r0, #3]
|
||||
; CHECK-NEXT: adds r0, #3
|
||||
; CHECK-NEXT: vstrb.16 q0, [r0, #3]!
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = getelementptr inbounds i8, i8* %y, i32 3
|
||||
@ -1206,9 +1153,8 @@ entry:
|
||||
define i8* @strb16_127(i8* %y, i8* %x) {
|
||||
; CHECK-LABEL: strb16_127:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: adds r0, #127
|
||||
; CHECK-NEXT: vldrb.u16 q0, [r1]
|
||||
; CHECK-NEXT: vstrb.16 q0, [r0]
|
||||
; CHECK-NEXT: vstrb.16 q0, [r0, #127]!
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = getelementptr inbounds i8, i8* %y, i32 127
|
||||
@ -1240,8 +1186,7 @@ define i8* @strb8_4(i8* %y, i8* %x) {
|
||||
; CHECK-LABEL: strb8_4:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.u8 q0, [r1]
|
||||
; CHECK-NEXT: vstrb.8 q0, [r0, #4]
|
||||
; CHECK-NEXT: adds r0, #4
|
||||
; CHECK-NEXT: vstrb.8 q0, [r0, #4]!
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = getelementptr inbounds i8, i8* %y, i32 4
|
||||
@ -1256,8 +1201,7 @@ define i8* @strb8_3(i8* %y, i8* %x) {
|
||||
; CHECK-LABEL: strb8_3:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrb.u8 q0, [r1]
|
||||
; CHECK-NEXT: vstrb.8 q0, [r0, #3]
|
||||
; CHECK-NEXT: adds r0, #3
|
||||
; CHECK-NEXT: vstrb.8 q0, [r0, #3]!
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = getelementptr inbounds i8, i8* %y, i32 3
|
||||
@ -1271,9 +1215,8 @@ entry:
|
||||
define i8* @strb8_127(i8* %y, i8* %x) {
|
||||
; CHECK-LABEL: strb8_127:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: adds r0, #127
|
||||
; CHECK-NEXT: vldrb.u8 q0, [r1]
|
||||
; CHECK-NEXT: vstrb.8 q0, [r0]
|
||||
; CHECK-NEXT: vstrb.8 q0, [r0, #127]!
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = getelementptr inbounds i8, i8* %y, i32 127
|
||||
@ -1304,8 +1247,7 @@ define i8* @strf32_4(i8* %y, i8* %x) {
|
||||
; CHECK-LABEL: strf32_4:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrw.u32 q0, [r1]
|
||||
; CHECK-NEXT: vstrw.32 q0, [r0, #4]
|
||||
; CHECK-NEXT: adds r0, #4
|
||||
; CHECK-NEXT: vstrb.8 q0, [r0, #4]!
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = getelementptr inbounds i8, i8* %y, i32 4
|
||||
@ -1320,8 +1262,7 @@ define i8* @strf16_4(i8* %y, i8* %x) {
|
||||
; CHECK-LABEL: strf16_4:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrh.u16 q0, [r1]
|
||||
; CHECK-NEXT: vstrh.16 q0, [r0, #4]
|
||||
; CHECK-NEXT: adds r0, #4
|
||||
; CHECK-NEXT: vstrb.8 q0, [r0, #4]!
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = getelementptr inbounds i8, i8* %y, i32 4
|
||||
@ -1336,8 +1277,7 @@ define i8* @strwi32_align1(i8* %y, i8* %x) {
|
||||
; CHECK-LABEL: strwi32_align1:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrw.u32 q0, [r1]
|
||||
; CHECK-NEXT: vstrb.8 q0, [r0, #3]
|
||||
; CHECK-NEXT: adds r0, #3
|
||||
; CHECK-NEXT: vstrb.8 q0, [r0, #3]!
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = getelementptr inbounds i8, i8* %y, i32 3
|
||||
@ -1352,8 +1292,7 @@ define i8* @strhi16_align1(i8* %y, i8* %x) {
|
||||
; CHECK-LABEL: strhi16_align1:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrh.u16 q0, [r1]
|
||||
; CHECK-NEXT: vstrb.8 q0, [r0, #3]
|
||||
; CHECK-NEXT: adds r0, #3
|
||||
; CHECK-NEXT: vstrb.8 q0, [r0, #3]!
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = getelementptr inbounds i8, i8* %y, i32 3
|
||||
@ -1391,8 +1330,7 @@ define i8* @strf32_align1(i8* %y, i8* %x) {
|
||||
; CHECK-LABEL: strf32_align1:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrw.u32 q0, [r1]
|
||||
; CHECK-NEXT: vstrb.8 q0, [r0, #3]
|
||||
; CHECK-NEXT: adds r0, #3
|
||||
; CHECK-NEXT: vstrb.8 q0, [r0, #3]!
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = getelementptr inbounds i8, i8* %y, i32 3
|
||||
@ -1407,8 +1345,7 @@ define i8* @strf16_align1(i8* %y, i8* %x) {
|
||||
; CHECK-LABEL: strf16_align1:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrh.u16 q0, [r1]
|
||||
; CHECK-NEXT: vstrb.8 q0, [r0, #3]
|
||||
; CHECK-NEXT: adds r0, #3
|
||||
; CHECK-NEXT: vstrb.8 q0, [r0, #3]!
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%z = getelementptr inbounds i8, i8* %y, i32 3
|
||||
|
||||
@ -55,8 +55,8 @@ entry:
|
||||
define hidden void @fwd_float16_t(%struct.s_float16_t* noalias nocapture %v) local_unnamed_addr #0 {
|
||||
; CHECK-LABEL: fwd_float16_t:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldrh.u16 q0, [r0]
|
||||
; CHECK-NEXT: vstrh.16 q0, [r0, #16]
|
||||
; CHECK-NEXT: vldrh.u16 q0, [r0], #16
|
||||
; CHECK-NEXT: vstrh.16 q0, [r0]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%arrayidx3 = getelementptr inbounds %struct.s_float16_t, %struct.s_float16_t* %v, i32 0, i32 1, i32 0
|
||||
@ -130,8 +130,8 @@ for.end:
|
||||
define hidden void @bwd_float16_t(%struct.s_float16_t* noalias nocapture %v) local_unnamed_addr #0 {
|
||||
; CHECK-LABEL: bwd_float16_t:
|
||||
; CHECK: @ %bb.0: @ %for.end
|
||||
; CHECK-NEXT: vldrh.u16 q0, [r0]
|
||||
; CHECK-NEXT: vstrh.16 q0, [r0, #-16]
|
||||
; CHECK-NEXT: vldrh.u16 q0, [r0], #-16
|
||||
; CHECK-NEXT: vstrh.16 q0, [r0]
|
||||
; CHECK-NEXT: bx lr
|
||||
for.end:
|
||||
%0 = bitcast %struct.s_float16_t* %v to <8 x half>*
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user