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Operand 1 should be a register. We don't care if it's a preg, vreg, or 0.

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llvm-svn: 45699
This commit is contained in:
Bill Wendling 2008-01-07 08:05:29 +00:00
parent 9aefefc673
commit b94c1f2999
1 changed files with 9 additions and 13 deletions
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22
lib/Target/X86/X86InstrInfo.cpp
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@ -771,19 +771,15 @@ bool X86InstrInfo::isReallySideEffectFree(MachineInstr *MI) const {
switch (MI->getOpcode()) {
default: break;
case X86::MOV32rm:
if (MI->getOperand(1).isRegister()) {
unsigned Reg = MI->getOperand(1).getReg();
const X86Subtarget &ST = TM.getSubtarget<X86Subtarget>();
// Loads from stubs of global addresses are side effect free.
if (Reg != 0 && MRegisterInfo::isVirtualRegister(Reg) &&
MI->getOperand(2).isImm() && MI->getOperand(3).isReg() &&
MI->getOperand(4).isGlobal() &&
ST.GVRequiresExtraLoad(MI->getOperand(4).getGlobal(), TM, false) &&
MI->getOperand(2).getImm() == 1 &&
MI->getOperand(3).getReg() == 0)
return true;
}
// Loads from stubs of global addresses are side effect free.
if (MI->getOperand(1).isReg() &&
MI->getOperand(2).isImm() && MI->getOperand(3).isReg() &&
MI->getOperand(4).isGlobal() &&
TM.getSubtarget<X86Subtarget>().GVRequiresExtraLoad
(MI->getOperand(4).getGlobal(), TM, false) &&
MI->getOperand(2).getImm() == 1 &&
MI->getOperand(3).getReg() == 0)
return true;
// FALLTHROUGH
case X86::MOV8rm:
case X86::MOV16rm: