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[ARM GlobalISel] Allow calls to varargs functions
Allow varargs functions to be called, both in arm and thumb mode. This boils down to choosing the correct calling convention, which we can easily test by making sure arm_aapcscc is used instead of arm_aapcs_vfpcc when the callee is variadic. llvm-svn: 351424
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Diana Picus
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dcf62df83b
commit
b99810417e
@ -561,13 +561,14 @@ bool ARMCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
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MIB.addRegMask(TRI->getCallPreservedMask(MF, CallConv));
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bool IsVarArg = false;
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SmallVector<ArgInfo, 8> ArgInfos;
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for (auto Arg : OrigArgs) {
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if (!isSupportedType(DL, TLI, Arg.Ty))
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return false;
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if (!Arg.IsFixed)
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return false;
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IsVarArg = true;
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if (Arg.Flags.isByVal())
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return false;
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@ -581,7 +582,7 @@ bool ARMCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
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MIRBuilder.buildUnmerge(Regs, Arg.Reg);
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}
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auto ArgAssignFn = TLI.CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
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auto ArgAssignFn = TLI.CCAssignFnForCall(CallConv, IsVarArg);
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OutgoingValueHandler ArgHandler(MIRBuilder, MRI, MIB, ArgAssignFn);
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if (!handleAssignments(MIRBuilder, ArgInfos, ArgHandler))
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return false;
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@ -600,7 +601,7 @@ bool ARMCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
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SplitRegs.push_back(Reg);
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});
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auto RetAssignFn = TLI.CCAssignFnForReturn(CallConv, /*IsVarArg=*/false);
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auto RetAssignFn = TLI.CCAssignFnForReturn(CallConv, IsVarArg);
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CallReturnHandler RetHandler(MIRBuilder, MRI, MIB, RetAssignFn);
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if (!handleAssignments(MIRBuilder, ArgInfos, RetHandler))
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return false;
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@ -83,13 +83,6 @@ define void @test_vararg_definition(i32 %a, ...) {
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ret void
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}
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define void @test_vararg_call(i32 %a) {
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; CHECK: remark: {{.*}} unable to translate instruction: call
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; CHECK-LABEL: warning: Instruction selection used fallback path for test_vararg_call
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call void(i32, ...) @test_vararg_definition(i32 %a, i32 %a, i32 %a)
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ret void
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}
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define i32 @test_thumb(i32 %a) #0 {
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; CHECK: remark: {{.*}} unable to lower arguments: i32 (i32)*
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; CHECK-LABEL: warning: Instruction selection used fallback path for test_thumb
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86
test/CodeGen/ARM/GlobalISel/irtranslator-varargs-lowering.ll
Normal file
86
test/CodeGen/ARM/GlobalISel/irtranslator-varargs-lowering.ll
Normal file
@ -0,0 +1,86 @@
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; RUN: llc -mtriple arm-unknown -mattr=+vfp2,+v6t2 -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=ARM
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; RUN: llc -mtriple thumb-unknown -mattr=+vfp2,+v6t2 -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=THUMB
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declare arm_aapcscc i32 @int_varargs_target(i32, ...)
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define arm_aapcscc i32 @test_call_to_varargs_with_ints(i32 *%a, i32 %b) {
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; CHECK-LABEL: name: test_call_to_varargs_with_ints
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; CHECK-DAG: [[AVREG:%[0-9]+]]:_(p0) = COPY $r0
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; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s32) = COPY $r1
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; CHECK: ADJCALLSTACKDOWN 8, 0, 14, $noreg, implicit-def $sp, implicit $sp
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; CHECK-DAG: $r0 = COPY [[BVREG]]
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; CHECK-DAG: $r1 = COPY [[AVREG]]
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; CHECK-DAG: $r2 = COPY [[BVREG]]
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; CHECK-DAG: $r3 = COPY [[AVREG]]
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; CHECK: [[SP1:%[0-9]+]]:_(p0) = COPY $sp
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; CHECK: [[OFF1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK: [[FI1:%[0-9]+]]:_(p0) = G_GEP [[SP1]], [[OFF1]](s32)
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; CHECK: G_STORE [[BVREG]](s32), [[FI1]](p0){{.*}}store 4
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; CHECK: [[SP2:%[0-9]+]]:_(p0) = COPY $sp
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; CHECK: [[OFF2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
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; CHECK: [[FI2:%[0-9]+]]:_(p0) = G_GEP [[SP2]], [[OFF2]](s32)
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; CHECK: G_STORE [[AVREG]](p0), [[FI2]](p0){{.*}}store 4
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; ARM: BL @int_varargs_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
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; THUMB: tBL 14, $noreg, @int_varargs_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
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; CHECK: [[RVREG:%[0-9]+]]:_(s32) = COPY $r0
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; CHECK: ADJCALLSTACKUP 8, 0, 14, $noreg, implicit-def $sp, implicit $sp
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; CHECK: $r0 = COPY [[RVREG]]
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; ARM: BX_RET 14, $noreg, implicit $r0
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; THUMB: tBX_RET 14, $noreg, implicit $r0
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entry:
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%r = notail call arm_aapcscc i32(i32, ...) @int_varargs_target(i32 %b, i32 *%a, i32 %b, i32 *%a, i32 %b, i32 *%a)
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ret i32 %r
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}
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declare arm_aapcs_vfpcc float @float_varargs_target(float, double, ...)
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define arm_aapcs_vfpcc float @test_call_to_varargs_with_floats(float %a, double %b) {
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; CHECK-LABEL: name: test_call_to_varargs_with_floats
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; CHECK-DAG: [[AVREG:%[0-9]+]]:_(s32) = COPY $s0
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; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s64) = COPY $d1
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; CHECK: ADJCALLSTACKDOWN 8, 0, 14, $noreg, implicit-def $sp, implicit $sp
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; CHECK-DAG: $r0 = COPY [[AVREG]]
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; CHECK-DAG: [[B1:%[0-9]+]]:_(s32), [[B2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BVREG]](s64)
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; CHECK-DAG: $r2 = COPY [[B1]]
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; CHECK-DAG: $r3 = COPY [[B2]]
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; CHECK: [[SP1:%[0-9]+]]:_(p0) = COPY $sp
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; CHECK: [[OFF1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK: [[FI1:%[0-9]+]]:_(p0) = G_GEP [[SP1]], [[OFF1]](s32)
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; CHECK: G_STORE [[BVREG]](s64), [[FI1]](p0){{.*}}store 8
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; ARM: BL @float_varargs_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r2, implicit $r3, implicit-def $r0
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; THUMB: tBL 14, $noreg, @float_varargs_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r2, implicit $r3, implicit-def $r0
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; CHECK: [[RVREG:%[0-9]+]]:_(s32) = COPY $r0
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; CHECK: ADJCALLSTACKUP 8, 0, 14, $noreg, implicit-def $sp, implicit $sp
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; CHECK: $s0 = COPY [[RVREG]]
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; ARM: BX_RET 14, $noreg, implicit $s0
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; THUMB: tBX_RET 14, $noreg, implicit $s0
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entry:
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%r = notail call arm_aapcs_vfpcc float(float, double, ...) @float_varargs_target(float %a, double %b, double %b)
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ret float %r
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}
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define arm_aapcs_vfpcc float @test_indirect_call_to_varargs(float (float, double, ...) *%fptr, float %a, double %b) {
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; CHECK-LABEL: name: test_indirect_call_to_varargs
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; CHECK-DAG: [[FPTRVREG:%[0-9]+]]:gpr(p0) = COPY $r0
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; CHECK-DAG: [[AVREG:%[0-9]+]]:_(s32) = COPY $s0
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; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s64) = COPY $d1
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; CHECK: ADJCALLSTACKDOWN 8, 0, 14, $noreg, implicit-def $sp, implicit $sp
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; CHECK-DAG: $r0 = COPY [[AVREG]]
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; CHECK-DAG: [[B1:%[0-9]+]]:_(s32), [[B2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BVREG]](s64)
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; CHECK-DAG: $r2 = COPY [[B1]]
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; CHECK-DAG: $r3 = COPY [[B2]]
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; CHECK: [[SP1:%[0-9]+]]:_(p0) = COPY $sp
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; CHECK: [[OFF1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK: [[FI1:%[0-9]+]]:_(p0) = G_GEP [[SP1]], [[OFF1]](s32)
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; CHECK: G_STORE [[BVREG]](s64), [[FI1]](p0){{.*}}store 8
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; ARM: BLX [[FPTRVREG]](p0), csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r2, implicit $r3, implicit-def $r0
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; THUMB: tBLXr 14, $noreg, [[FPTRVREG]](p0), csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r2, implicit $r3, implicit-def $r0
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; CHECK: [[RVREG:%[0-9]+]]:_(s32) = COPY $r0
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; CHECK: ADJCALLSTACKUP 8, 0, 14, $noreg, implicit-def $sp, implicit $sp
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; CHECK: $s0 = COPY [[RVREG]]
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; ARM: BX_RET 14, $noreg, implicit $s0
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; THUMB: tBX_RET 14, $noreg, implicit $s0
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entry:
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%r = notail call arm_aapcs_vfpcc float(float, double, ...) %fptr(float %a, double %b, double %b)
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ret float %r
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}
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