From b9bb673ebd20efb9a5a1b46e90aa8889a2bf1395 Mon Sep 17 00:00:00 2001
From: Oliver Cruickshank <oliver.cruickshank@arm.com>
Date: Mon, 16 Sep 2019 15:20:10 +0000
Subject: [PATCH] [ARM] Add patterns for BSWAP intrinsic on MVE

BSWAP can use the VREV instruction on MVE to produce better results than
expanding.

llvm-svn: 372002
---
 lib/Target/ARM/ARMISelLowering.cpp |  1 +
 lib/Target/ARM/ARMInstrMVE.td      |  7 ++++++
 test/CodeGen/Thumb2/mve-bswap.ll   | 37 ++++++++++++++++++++++++++++++
 3 files changed, 45 insertions(+)
 create mode 100644 test/CodeGen/Thumb2/mve-bswap.ll

diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
index c5848c95094..6f7b6214e95 100644
--- a/lib/Target/ARM/ARMISelLowering.cpp
+++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -264,6 +264,7 @@ void ARMTargetLowering::addMVEVectorTypes(bool HasMVEFP) {
     setOperationAction(ISD::CTLZ, VT, Legal);
     setOperationAction(ISD::CTTZ, VT, Expand);
     setOperationAction(ISD::BITREVERSE, VT, Legal);
+    setOperationAction(ISD::BSWAP, VT, Legal);
 
     // No native support for these.
     setOperationAction(ISD::UDIV, VT, Expand);
diff --git a/lib/Target/ARM/ARMInstrMVE.td b/lib/Target/ARM/ARMInstrMVE.td
index b931dd01d29..9623b4d1d57 100644
--- a/lib/Target/ARM/ARMInstrMVE.td
+++ b/lib/Target/ARM/ARMInstrMVE.td
@@ -1057,6 +1057,13 @@ def MVE_VREV32_16 : MVE_VREV<"vrev32", "16", 0b01, 0b01>;
 
 def MVE_VREV16_8  : MVE_VREV<"vrev16", "8", 0b00, 0b10>;
 
+let Predicates = [HasMVEInt] in {
+  def : Pat<(v8i16 (bswap (v8i16 MQPR:$src))),
+            (v8i16 (MVE_VREV16_8 (v8i16 MQPR:$src)))>;
+  def : Pat<(v4i32 (bswap (v4i32 MQPR:$src))),
+            (v4i32 (MVE_VREV32_8 (v4i32 MQPR:$src)))>;
+}
+
 let Predicates = [HasMVEInt] in {
   def : Pat<(v4i32 (ARMvrev64 (v4i32 MQPR:$src))),
             (v4i32 (MVE_VREV64_32 (v4i32 MQPR:$src)))>;
diff --git a/test/CodeGen/Thumb2/mve-bswap.ll b/test/CodeGen/Thumb2/mve-bswap.ll
new file mode 100644
index 00000000000..c7d3f844fd7
--- /dev/null
+++ b/test/CodeGen/Thumb2/mve-bswap.ll
@@ -0,0 +1,37 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -verify-machineinstrs -mattr=+mve %s -o - | FileCheck %s
+
+define arm_aapcs_vfpcc <4 x i32> @bswap_4i32_t(<4 x i32> %src){
+; CHECK-LABEL: bswap_4i32_t:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vrev32.8 q0, q0
+; CHECK-NEXT:    bx lr
+entry:
+    %0 = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %src)
+    ret <4 x i32> %0
+}
+
+define arm_aapcs_vfpcc <8 x i16> @bswap_8i16_t(<8 x i16> %src){
+; CHECK-LABEL: bswap_8i16_t:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vrev16.8 q0, q0
+; CHECK-NEXT:    bx lr
+entry:
+    %0 = call <8 x i16> @llvm.bswap.v8i16(<8 x i16> %src)
+    ret <8 x i16> %0
+}
+
+define arm_aapcs_vfpcc <2 x i64> @bswap_2i64_t(<2 x i64> %src){
+; CHECK-LABEL: bswap_2i64_t:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vrev64.8 q1, q0
+; CHECK-NEXT:    vmov q0, q1
+; CHECK-NEXT:    bx lr
+entry:
+    %0 = call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %src)
+    ret <2 x i64> %0
+}
+
+declare <2 x i64> @llvm.bswap.v2i64(<2 x i64>)
+declare <4 x i32> @llvm.bswap.v4i32(<4 x i32>)
+declare <8 x i16> @llvm.bswap.v8i16(<8 x i16>)