mirror of
https://github.com/RPCS3/llvm-mirror.git
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[AMDGPU] Simplify memory legalizer
- Make code easier to maintain. - Avoid generating waitcnts for VMEM if the address sppace does not involve VMEM. - Add support to generate waitcnts for LDS and GDS memory. Differential Revision: https://reviews.llvm.org/D47504 llvm-svn: 334241
This commit is contained in:
Tony Tye
parent
694b5c1ad6
commit
b9df9119fc
File diff suppressed because it is too large
Load Diff
69
test/CodeGen/AMDGPU/memory-legalizer-invalid-addrspace.mir
Normal file
69
test/CodeGen/AMDGPU/memory-legalizer-invalid-addrspace.mir
Normal file
@ -0,0 +1,69 @@
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# RUN: not llc -march=amdgcn -mcpu=gfx803 -run-pass si-memory-legalizer %s -o - 2>&1 | FileCheck -check-prefix=GCN %s
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---
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# GCN: error: <unknown>:0:0: in function invalid_load void (): Unsupported atomic address space
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name: invalid_load
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1
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$vgpr0 = V_MOV_B32_e32 $sgpr2, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr2_sgpr3
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$vgpr1 = V_MOV_B32_e32 killed $sgpr3, implicit $exec, implicit $sgpr2_sgpr3, implicit $exec
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renamable $vgpr2 = FLAT_LOAD_DWORD killed renamable $vgpr0_vgpr1, 0, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load seq_cst 4 from `i32 addrspace(42)* undef`)
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$vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
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$vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
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FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32* undef`)
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S_ENDPGM
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...
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---
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# GCN: error: <unknown>:0:0: in function invalid_store void (): Unsupported atomic address space
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name: invalid_store
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1
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$vgpr2 = V_MOV_B32_e32 killed $sgpr2, implicit $exec, implicit $exec
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$vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
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$vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
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FLAT_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (volatile store syncscope("agent") seq_cst 4 into `i32 addrspace(42)* undef`)
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S_ENDPGM
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...
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---
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# GCN: error: <unknown>:0:0: in function invalid_cmpxchg void (): Unsupported atomic address space
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name: invalid_cmpxchg
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1
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$vgpr3 = V_MOV_B32_e32 $sgpr1, implicit $exec, implicit-def $vgpr2_vgpr3, implicit $sgpr0_sgpr1
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$vgpr0 = V_MOV_B32_e32 killed $sgpr4, implicit $exec, implicit $exec
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$vgpr1 = V_MOV_B32_e32 killed $sgpr5, implicit $exec, implicit $exec
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$vgpr2 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
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FLAT_ATOMIC_CMPSWAP killed renamable $vgpr2_vgpr3, killed renamable $vgpr0_vgpr1, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load store syncscope("workgroup") seq_cst seq_cst 4 on `i32 addrspace(42)* undef`)
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S_ENDPGM
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...
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---
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# GCN: error: <unknown>:0:0: in function invalid_rmw void (): Unsupported atomic address space
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name: invalid_rmw
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1
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$vgpr0 = V_MOV_B32_e32 $sgpr2, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr2_sgpr3
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$vgpr1 = V_MOV_B32_e32 killed $sgpr3, implicit $exec, implicit $sgpr2_sgpr3, implicit $exec
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$vgpr2 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
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FLAT_ATOMIC_SWAP killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load store syncscope("wavefront") seq_cst 4 on `i32 addrspace(42)* undef`)
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S_ENDPGM
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...
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@ -1,14 +1,14 @@
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; RUN: not llc -mtriple=amdgcn-amd- -mcpu=gfx803 -verify-machineinstrs < %s 2>&1 | FileCheck %s
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; RUN: not llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -verify-machineinstrs < %s 2>&1 | FileCheck %s
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; CHECK: error: <unknown>:0:0: in function invalid_fence void (): Unsupported synchronization scope
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; CHECK: error: <unknown>:0:0: in function invalid_fence void (): Unsupported atomic synchronization scope
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define amdgpu_kernel void @invalid_fence() {
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entry:
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fence syncscope("invalid") seq_cst
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ret void
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}
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; CHECK: error: <unknown>:0:0: in function invalid_load void (i32*, i32*): Unsupported synchronization scope
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; CHECK: error: <unknown>:0:0: in function invalid_load void (i32*, i32*): Unsupported non-inclusive atomic synchronization scope
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define amdgpu_kernel void @invalid_load(
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i32* %in, i32* %out) {
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entry:
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@ -17,7 +17,7 @@ entry:
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ret void
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}
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; CHECK: error: <unknown>:0:0: in function invalid_store void (i32, i32*): Unsupported synchronization scope
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; CHECK: error: <unknown>:0:0: in function invalid_store void (i32, i32*): Unsupported non-inclusive atomic synchronization scope
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define amdgpu_kernel void @invalid_store(
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i32 %in, i32* %out) {
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entry:
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@ -25,7 +25,7 @@ entry:
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ret void
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}
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; CHECK: error: <unknown>:0:0: in function invalid_cmpxchg void (i32*, i32, i32): Unsupported synchronization scope
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; CHECK: error: <unknown>:0:0: in function invalid_cmpxchg void (i32*, i32, i32): Unsupported non-inclusive atomic synchronization scope
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define amdgpu_kernel void @invalid_cmpxchg(
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i32* %out, i32 %in, i32 %old) {
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entry:
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@ -34,7 +34,7 @@ entry:
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ret void
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}
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; CHECK: error: <unknown>:0:0: in function invalid_rmw void (i32*, i32): Unsupported synchronization scope
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; CHECK: error: <unknown>:0:0: in function invalid_rmw void (i32*, i32): Unsupported non-inclusive atomic synchronization scope
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define amdgpu_kernel void @invalid_rmw(
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i32* %out, i32 %in) {
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entry:
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@ -9,7 +9,7 @@ declare i32 @llvm.amdgcn.workitem.id.x()
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; GCN-NOT: s_waitcnt vmcnt(0){{$}}
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; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
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; GCN-NOT: s_waitcnt vmcnt(0){{$}}
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; GCN-NOT: buffer_wbinvl1_vol
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; GFX89-NOT: buffer_wbinvl1_vol
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; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
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define amdgpu_kernel void @system_unordered(
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i32* %in, i32* %out) {
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@ -23,7 +23,7 @@ entry:
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; GCN-NOT: s_waitcnt vmcnt(0){{$}}
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; GFX89: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}] glc{{$}}
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; GCN-NOT: s_waitcnt vmcnt(0){{$}}
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; GCN-NOT: buffer_wbinvl1_vol
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; GFX89-NOT: buffer_wbinvl1_vol
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; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
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define amdgpu_kernel void @system_monotonic(
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i32* %in, i32* %out) {
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@ -65,7 +65,7 @@ entry:
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; GCN-NOT: s_waitcnt vmcnt(0){{$}}
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; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
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; GCN-NOT: s_waitcnt vmcnt(0){{$}}
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; GCN-NOT: buffer_wbinvl1_vol
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; GFX89-NOT: buffer_wbinvl1_vol
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; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
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define amdgpu_kernel void @singlethread_unordered(
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i32* %in, i32* %out) {
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@ -79,7 +79,7 @@ entry:
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; GCN-NOT: s_waitcnt vmcnt(0){{$}}
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; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
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; GCN-NOT: s_waitcnt vmcnt(0){{$}}
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; GCN-NOT: buffer_wbinvl1_vol
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; GFX89-NOT: buffer_wbinvl1_vol
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; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
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define amdgpu_kernel void @singlethread_monotonic(
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i32* %in, i32* %out) {
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@ -93,7 +93,7 @@ entry:
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; GCN-NOT: s_waitcnt vmcnt(0){{$}}
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; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
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; GCN-NOT: s_waitcnt vmcnt(0){{$}}
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; GCN-NOT: buffer_wbinvl1_vol
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; GFX89-NOT: buffer_wbinvl1_vol
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; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
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define amdgpu_kernel void @singlethread_acquire(
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i32* %in, i32* %out) {
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@ -107,7 +107,7 @@ entry:
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; GCN-NOT: s_waitcnt vmcnt(0){{$}}
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; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
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; GCN-NOT: s_waitcnt vmcnt(0){{$}}
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; GCN-NOT: buffer_wbinvl1_vol
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; GFX89-NOT: buffer_wbinvl1_vol
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; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
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define amdgpu_kernel void @singlethread_seq_cst(
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i32* %in, i32* %out) {
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@ -121,7 +121,7 @@ entry:
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; GCN-NOT: s_waitcnt vmcnt(0){{$}}
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; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
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; GCN-NOT: s_waitcnt vmcnt(0){{$}}
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; GCN-NOT: buffer_wbinvl1_vol
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; GFX89-NOT: buffer_wbinvl1_vol
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; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
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define amdgpu_kernel void @agent_unordered(
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i32* %in, i32* %out) {
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@ -135,7 +135,7 @@ entry:
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; GCN-NOT: s_waitcnt vmcnt(0){{$}}
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; GFX89: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}] glc{{$}}
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; GCN-NOT: s_waitcnt vmcnt(0){{$}}
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; GCN-NOT: buffer_wbinvl1_vol
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; GFX89-NOT: buffer_wbinvl1_vol
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; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
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define amdgpu_kernel void @agent_monotonic(
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i32* %in, i32* %out) {
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@ -175,9 +175,9 @@ entry:
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; GCN-LABEL: {{^}}workgroup_unordered:
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; GCN-NOT: s_waitcnt vmcnt(0){{$}}
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; GFX89: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
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; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
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; GCN-NOT: s_waitcnt vmcnt(0){{$}}
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; GCN-NOT: buffer_wbinvl1_vol
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; GFX89-NOT: buffer_wbinvl1_vol
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; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
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define amdgpu_kernel void @workgroup_unordered(
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i32* %in, i32* %out) {
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@ -191,7 +191,7 @@ entry:
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; GCN-NOT: s_waitcnt vmcnt(0){{$}}
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; GFX89: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
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; GCN-NOT: s_waitcnt vmcnt(0){{$}}
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; GCN-NOT: buffer_wbinvl1_vol
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; GFX89-NOT: buffer_wbinvl1_vol
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; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
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define amdgpu_kernel void @workgroup_monotonic(
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i32* %in, i32* %out) {
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@ -233,7 +233,7 @@ entry:
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; GCN-NOT: s_waitcnt vmcnt(0){{$}}
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; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
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; GCN-NOT: s_waitcnt vmcnt(0){{$}}
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; GCN-NOT: buffer_wbinvl1_vol
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; GFX89-NOT: buffer_wbinvl1_vol
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; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
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define amdgpu_kernel void @wavefront_unordered(
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i32* %in, i32* %out) {
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@ -247,7 +247,7 @@ entry:
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; GCN-NOT: s_waitcnt vmcnt(0){{$}}
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; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
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; GCN-NOT: s_waitcnt vmcnt(0){{$}}
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; GCN-NOT: buffer_wbinvl1_vol
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; GFX89-NOT: buffer_wbinvl1_vol
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; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
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define amdgpu_kernel void @wavefront_monotonic(
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i32* %in, i32* %out) {
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@ -261,7 +261,7 @@ entry:
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; GCN-NOT: s_waitcnt vmcnt(0){{$}}
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; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
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; GCN-NOT: s_waitcnt vmcnt(0){{$}}
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; GCN-NOT: buffer_wbinvl1_vol
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; GFX89-NOT: buffer_wbinvl1_vol
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; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
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define amdgpu_kernel void @wavefront_acquire(
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i32* %in, i32* %out) {
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@ -275,7 +275,7 @@ entry:
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; GCN-NOT: s_waitcnt vmcnt(0){{$}}
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; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
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; GCN-NOT: s_waitcnt vmcnt(0){{$}}
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; GCN-NOT: buffer_wbinvl1_vol
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; GFX89-NOT: buffer_wbinvl1_vol
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; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
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define amdgpu_kernel void @wavefront_seq_cst(
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i32* %in, i32* %out) {
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1054
test/CodeGen/AMDGPU/memory-legalizer-local.mir
Normal file
1054
test/CodeGen/AMDGPU/memory-legalizer-local.mir
Normal file
File diff suppressed because it is too large
Load Diff
@ -1,119 +1,19 @@
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# RUN: llc -march=amdgcn -mcpu=gfx803 -run-pass si-memory-legalizer %s -o - | FileCheck %s
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# RUN: llc -march=amdgcn -mcpu=gfx803 -run-pass si-memory-legalizer %s -o - | FileCheck -check-prefix=GCN %s
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--- |
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; ModuleID = 'memory-legalizer-multiple-mem-operands.ll'
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source_filename = "memory-legalizer-multiple-mem-operands.ll"
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target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5"
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define amdgpu_kernel void @multiple_mem_operands(i32 addrspace(1)* %out, i32 %cond, i32 %if_offset, i32 %else_offset) #0 {
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entry:
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%scratch0 = alloca [8192 x i32], addrspace(5)
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%scratch1 = alloca [8192 x i32], addrspace(5)
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%scratchptr01 = bitcast [8192 x i32] addrspace(5)* %scratch0 to i32 addrspace(5)*
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store i32 1, i32 addrspace(5)* %scratchptr01
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%scratchptr12 = bitcast [8192 x i32] addrspace(5)* %scratch1 to i32 addrspace(5)*
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store i32 2, i32 addrspace(5)* %scratchptr12
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%cmp = icmp eq i32 %cond, 0
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br i1 %cmp, label %if, label %else, !structurizecfg.uniform !0, !amdgpu.uniform !0
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if: ; preds = %entry
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%if_ptr = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %scratch0, i32 0, i32 %if_offset, !amdgpu.uniform !0
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%if_value = load atomic i32, i32 addrspace(5)* %if_ptr syncscope("workgroup") seq_cst, align 4
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br label %done, !structurizecfg.uniform !0
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else: ; preds = %entry
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%else_ptr = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %scratch1, i32 0, i32 %else_offset, !amdgpu.uniform !0
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%else_value = load atomic i32, i32 addrspace(5)* %else_ptr syncscope("agent") unordered, align 4
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br label %done, !structurizecfg.uniform !0
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done: ; preds = %else, %if
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%value = phi i32 [ %if_value, %if ], [ %else_value, %else ]
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store i32 %value, i32 addrspace(1)* %out
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ret void
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}
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; Function Attrs: convergent nounwind
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declare { i1, i64 } @llvm.amdgcn.if(i1) #1
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; Function Attrs: convergent nounwind
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declare { i1, i64 } @llvm.amdgcn.else(i64) #1
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; Function Attrs: convergent nounwind readnone
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declare i64 @llvm.amdgcn.break(i64) #2
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; Function Attrs: convergent nounwind readnone
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declare i64 @llvm.amdgcn.if.break(i1, i64) #2
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; Function Attrs: convergent nounwind readnone
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declare i64 @llvm.amdgcn.else.break(i64, i64) #2
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; Function Attrs: convergent nounwind
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declare i1 @llvm.amdgcn.loop(i64) #1
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; Function Attrs: convergent nounwind
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declare void @llvm.amdgcn.end.cf(i64) #1
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attributes #0 = { "target-cpu"="gfx803" }
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attributes #1 = { convergent nounwind }
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attributes #2 = { convergent nounwind readnone }
|
||||
|
||||
!0 = !{}
|
||||
|
||||
...
|
||||
---
|
||||
|
||||
# CHECK-LABEL: name: multiple_mem_operands
|
||||
# GCN-LABEL: name: multiple_mem_operands
|
||||
|
||||
# CHECK-LABEL: bb.3.done:
|
||||
# CHECK: S_WAITCNT 3952
|
||||
# CHECK-NEXT: BUFFER_LOAD_DWORD_OFFEN
|
||||
# CHECK-NEXT: S_WAITCNT 3952
|
||||
# CHECK-NEXT: BUFFER_WBINVL1_VOL
|
||||
# GCN-LABEL: bb.3:
|
||||
# GCN: S_WAITCNT 3952
|
||||
# GCN-NEXT: BUFFER_LOAD_DWORD_OFFEN
|
||||
# GCN-NEXT: S_WAITCNT 3952
|
||||
# GCN-NEXT: BUFFER_WBINVL1_VOL
|
||||
|
||||
name: multiple_mem_operands
|
||||
alignment: 0
|
||||
exposesReturnsTwice: false
|
||||
legalized: false
|
||||
regBankSelected: false
|
||||
selected: false
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
liveins:
|
||||
- { reg: '$sgpr0_sgpr1', virtual-reg: '' }
|
||||
- { reg: '$sgpr3', virtual-reg: '' }
|
||||
frameInfo:
|
||||
isFrameAddressTaken: false
|
||||
isReturnAddressTaken: false
|
||||
hasStackMap: false
|
||||
hasPatchPoint: false
|
||||
stackSize: 65540
|
||||
offsetAdjustment: 0
|
||||
maxAlignment: 4
|
||||
adjustsStack: false
|
||||
hasCalls: false
|
||||
stackProtector: ''
|
||||
maxCallFrameSize: 0
|
||||
hasOpaqueSPAdjustment: false
|
||||
hasVAStart: false
|
||||
hasMustTailInVarArgFunc: false
|
||||
savePoint: ''
|
||||
restorePoint: ''
|
||||
fixedStack:
|
||||
- { id: 0, type: default, offset: 0, size: 4, alignment: 4, stack-id: 0,
|
||||
isImmutable: false, isAliased: false, callee-saved-register: '' }
|
||||
stack:
|
||||
- { id: 0, name: scratch0, type: default, offset: 4, size: 32768, alignment: 4,
|
||||
stack-id: 0, callee-saved-register: '', local-offset: 0,
|
||||
debug-info-variable: '', debug-info-expression: '',
|
||||
debug-info-location: '' }
|
||||
- { id: 1, name: scratch1, type: default, offset: 32772, size: 32768,
|
||||
alignment: 4, stack-id: 0, callee-saved-register: '', local-offset: 32768,
|
||||
debug-info-variable: '', debug-info-expression: '',
|
||||
debug-info-location: '' }
|
||||
constants:
|
||||
body: |
|
||||
bb.0.entry:
|
||||
successors: %bb.1.if(0x30000000), %bb.2.else(0x50000000)
|
||||
successors: %bb.1(0x30000000), %bb.2(0x50000000)
|
||||
liveins: $sgpr0_sgpr1, $sgpr3
|
||||
|
||||
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 44, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(2)* undef`)
|
||||
@ -123,43 +23,43 @@ body: |
|
||||
$sgpr10 = S_MOV_B32 4294967295, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11
|
||||
$sgpr11 = S_MOV_B32 15204352, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11
|
||||
$vgpr0 = V_MOV_B32_e32 1, implicit $exec
|
||||
BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr8_sgpr9_sgpr10_sgpr11, $sgpr3, 4, 0, 0, 0, implicit $exec :: (store 4 into %ir.scratchptr01)
|
||||
BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr8_sgpr9_sgpr10_sgpr11, $sgpr3, 4, 0, 0, 0, implicit $exec :: (store 4 into `i32 addrspace(5)* undef`)
|
||||
S_WAITCNT 127
|
||||
S_CMP_LG_U32 killed $sgpr2, 0, implicit-def $scc
|
||||
S_WAITCNT 3855
|
||||
$vgpr0 = V_MOV_B32_e32 2, implicit $exec
|
||||
$vgpr1 = V_MOV_B32_e32 32772, implicit $exec
|
||||
BUFFER_STORE_DWORD_OFFEN killed $vgpr0, killed $vgpr1, $sgpr8_sgpr9_sgpr10_sgpr11, $sgpr3, 0, 0, 0, 0, implicit $exec :: (store 4 into %ir.scratchptr12)
|
||||
S_CBRANCH_SCC0 %bb.1.if, implicit killed $scc
|
||||
BUFFER_STORE_DWORD_OFFEN killed $vgpr0, killed $vgpr1, $sgpr8_sgpr9_sgpr10_sgpr11, $sgpr3, 0, 0, 0, 0, implicit $exec :: (store 4 into `i32 addrspace(5)* undef`)
|
||||
S_CBRANCH_SCC0 %bb.1, implicit killed $scc
|
||||
|
||||
bb.2.else:
|
||||
successors: %bb.3.done(0x80000000)
|
||||
bb.2:
|
||||
successors: %bb.3(0x80000000)
|
||||
liveins: $sgpr0_sgpr1, $sgpr4_sgpr5, $sgpr3, $sgpr8_sgpr9_sgpr10_sgpr11
|
||||
|
||||
$sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 52, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(2)* undef`)
|
||||
S_WAITCNT 3855
|
||||
$vgpr0 = V_MOV_B32_e32 32772, implicit $exec
|
||||
S_BRANCH %bb.3.done
|
||||
S_BRANCH %bb.3
|
||||
|
||||
bb.1.if:
|
||||
successors: %bb.3.done(0x80000000)
|
||||
bb.1:
|
||||
successors: %bb.3(0x80000000)
|
||||
liveins: $sgpr0_sgpr1, $sgpr4_sgpr5, $sgpr3, $sgpr8_sgpr9_sgpr10_sgpr11
|
||||
|
||||
$sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 48, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(2)* undef`)
|
||||
S_WAITCNT 3855
|
||||
$vgpr0 = V_MOV_B32_e32 4, implicit $exec
|
||||
|
||||
bb.3.done:
|
||||
bb.3:
|
||||
liveins: $sgpr3, $sgpr4_sgpr5, $sgpr8_sgpr9_sgpr10_sgpr11, $vgpr0, $sgpr0
|
||||
|
||||
S_WAITCNT 127
|
||||
$sgpr0 = S_LSHL_B32 killed $sgpr0, 2, implicit-def dead $scc
|
||||
$vgpr0 = V_ADD_I32_e32 killed $sgpr0, killed $vgpr0, implicit-def dead $vcc, implicit $exec
|
||||
$vgpr0 = BUFFER_LOAD_DWORD_OFFEN killed $vgpr0, killed $sgpr8_sgpr9_sgpr10_sgpr11, $sgpr3, 0, 0, 0, 0, implicit $exec :: (load syncscope("agent") unordered 4 from %ir.else_ptr), (load syncscope("workgroup") seq_cst 4 from %ir.if_ptr)
|
||||
$vgpr0 = BUFFER_LOAD_DWORD_OFFEN killed $vgpr0, killed $sgpr8_sgpr9_sgpr10_sgpr11, $sgpr3, 0, 0, 0, 0, implicit $exec :: (load syncscope("agent") unordered 4 from `i32 addrspace(1)* undef`), (load syncscope("workgroup") seq_cst 4 from `[8192 x i32] addrspace(5)* undef`)
|
||||
$vgpr1 = V_MOV_B32_e32 $sgpr4, implicit $exec, implicit-def $vgpr1_vgpr2, implicit $sgpr4_sgpr5
|
||||
$vgpr2 = V_MOV_B32_e32 killed $sgpr5, implicit $exec, implicit $sgpr4_sgpr5, implicit $exec
|
||||
S_WAITCNT 3952
|
||||
FLAT_STORE_DWORD killed $vgpr1_vgpr2, killed $vgpr0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into %ir.out)
|
||||
FLAT_STORE_DWORD killed $vgpr1_vgpr2, killed $vgpr0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into `i32 addrspace(1)* undef`)
|
||||
S_ENDPGM
|
||||
|
||||
...
|
||||
|
||||
1054
test/CodeGen/AMDGPU/memory-legalizer-region.mir
Normal file
1054
test/CodeGen/AMDGPU/memory-legalizer-region.mir
Normal file
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user