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[GlobalISel] Add X,Y<dead> = G_UNMERGE Z -> X = G_TRUNC Z
Add a combiner helper that replaces G_UNMERGE where all the destination lanes are dead except the first one with a G_TRUNC. Differential Revision: https://reviews.llvm.org/D87174
This commit is contained in:
Quentin Colombet
parent
a1f6a63fbc
commit
b9fe935943
@ -258,6 +258,10 @@ public:
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bool applyCombineUnmergeConstant(MachineInstr &MI,
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SmallVectorImpl<APInt> &Csts);
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/// Transform X, Y<dead> = G_UNMERGE Z -> X = G_TRUNC Z.
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bool matchCombineUnmergeWithDeadLanesToTrunc(MachineInstr &MI);
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bool applyCombineUnmergeWithDeadLanesToTrunc(MachineInstr &MI);
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/// Transform IntToPtr(PtrToInt(x)) to x if cast is in the same address space.
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bool matchCombineI2PToP2I(MachineInstr &MI, Register &Reg);
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bool applyCombineI2PToP2I(MachineInstr &MI, Register &Reg);
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@ -421,6 +421,14 @@ def unmerge_cst : GICombineRule<
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(apply [{ return Helper.applyCombineUnmergeConstant(*${d}, ${info}); }])
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>;
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// Transform x,y<dead> = unmerge z -> x = trunc z.
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def unmerge_dead_to_trunc : GICombineRule<
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(defs root:$d),
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(match (wip_match_opcode G_UNMERGE_VALUES): $d,
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[{ return Helper.matchCombineUnmergeWithDeadLanesToTrunc(*${d}); }]),
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(apply [{ return Helper.applyCombineUnmergeWithDeadLanesToTrunc(*${d}); }])
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>;
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// FIXME: These should use the custom predicate feature once it lands.
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def undef_combines : GICombineGroup<[undef_to_fp_zero, undef_to_int_zero,
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undef_to_negative_one,
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@ -452,4 +460,4 @@ def all_combines : GICombineGroup<[trivial_combines, ptr_add_immed_chain,
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width_reduction_combines, select_combines,
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known_bits_simplifications, ext_ext_fold,
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not_cmp_fold, opt_brcond_by_inverting_cond,
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unmerge_merge, fabs_fabs_fold, unmerge_cst]>;
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unmerge_merge, fabs_fabs_fold, unmerge_cst, unmerge_dead_to_trunc]>;
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@ -1654,6 +1654,39 @@ bool CombinerHelper::applyCombineUnmergeConstant(MachineInstr &MI,
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return true;
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}
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bool CombinerHelper::matchCombineUnmergeWithDeadLanesToTrunc(MachineInstr &MI) {
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assert(MI.getOpcode() == TargetOpcode::G_UNMERGE_VALUES &&
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"Expected an unmerge");
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// Check that all the lanes are dead except the first one.
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for (unsigned Idx = 1, EndIdx = MI.getNumDefs(); Idx != EndIdx; ++Idx) {
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if (!MRI.use_nodbg_empty(MI.getOperand(Idx).getReg()))
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return false;
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}
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return true;
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}
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bool CombinerHelper::applyCombineUnmergeWithDeadLanesToTrunc(MachineInstr &MI) {
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Builder.setInstrAndDebugLoc(MI);
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Register SrcReg = MI.getOperand(MI.getNumDefs()).getReg();
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// Truncating a vector is going to truncate every single lane,
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// whereas we want the full lowbits.
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// Do the operation on a scalar instead.
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LLT SrcTy = MRI.getType(SrcReg);
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if (SrcTy.isVector())
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SrcReg =
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Builder.buildCast(LLT::scalar(SrcTy.getSizeInBits()), SrcReg).getReg(0);
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Register Dst0Reg = MI.getOperand(0).getReg();
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LLT Dst0Ty = MRI.getType(Dst0Reg);
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if (Dst0Ty.isVector()) {
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auto MIB = Builder.buildTrunc(LLT::scalar(Dst0Ty.getSizeInBits()), SrcReg);
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Builder.buildCast(Dst0Reg, MIB);
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} else
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Builder.buildTrunc(Dst0Reg, SrcReg);
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MI.eraseFromParent();
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return true;
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}
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bool CombinerHelper::matchCombineShiftToUnmerge(MachineInstr &MI,
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unsigned TargetShiftSize,
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unsigned &ShiftVal) {
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@ -292,3 +292,80 @@ body: |
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$h2 = COPY %3(s16)
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$h3 = COPY %4(s16)
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...
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# Transform unmerge into trunc when only the first definition is live.
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---
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name: test_combine_unmerge_dead_to_trunc
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body: |
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bb.1:
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; CHECK-LABEL: name: test_combine_unmerge_dead_to_trunc
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
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; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s64)
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; CHECK: $h0 = COPY [[TRUNC]](s16)
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%0:_(s64) = COPY $x0
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%1:_(s16),%2:_(s16),%3:_(s16),%4:_(s16) = G_UNMERGE_VALUES %0(s64)
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$h0 = COPY %1(s16)
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...
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# Don't transform unmerge into trunc when middle lanes are live.
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---
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name: test_dont_combine_unmerge_dead_to_trunc
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body: |
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bb.1:
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; CHECK-LABEL: name: test_dont_combine_unmerge_dead_to_trunc
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
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; CHECK: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](s64)
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; CHECK: $h0 = COPY [[UV2]](s16)
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%0:_(s64) = COPY $x0
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%1:_(s16),%2:_(s16),%3:_(s16),%4:_(s16) = G_UNMERGE_VALUES %0(s64)
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$h0 = COPY %3(s16)
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...
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# Transform unmerge into trunc when only the first definition is live, even
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# if the input and output types are vectors.
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---
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name: test_combine_unmerge_dead_to_trunc_vec_in_n_out
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body: |
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bb.1:
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; CHECK-LABEL: name: test_combine_unmerge_dead_to_trunc_vec_in_n_out
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; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $x0
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; CHECK: [[BITCAST:%[0-9]+]]:_(s64) = G_BITCAST [[COPY]](<2 x s32>)
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; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[BITCAST]](s64)
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; CHECK: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[TRUNC]](s32)
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; CHECK: $w0 = COPY [[BITCAST1]](<2 x s16>)
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%0:_(<2 x s32>) = COPY $x0
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%1:_(<2 x s16>),%2:_(<2 x s16>) = G_UNMERGE_VALUES %0(<2 x s32>)
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$w0 = COPY %1(<2 x s16>)
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...
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# Transform unmerge into trunc when only the first definition is live, even
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# if the input type is vector.
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---
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name: test_combine_unmerge_dead_to_trunc_vec_in
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body: |
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bb.1:
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; CHECK-LABEL: name: test_combine_unmerge_dead_to_trunc_vec_in
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; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $x0
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; CHECK: [[BITCAST:%[0-9]+]]:_(s64) = G_BITCAST [[COPY]](<2 x s32>)
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; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s64)
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; CHECK: $h0 = COPY [[TRUNC]](s16)
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%0:_(<2 x s32>) = COPY $x0
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%1:_(s16),%2:_(s16),%3:_(s16),%4:_(s16) = G_UNMERGE_VALUES %0(<2 x s32>)
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$h0 = COPY %1(s16)
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...
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# Transform unmerge into trunc when only the first definition is live, even
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# if the output type are vector.
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---
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name: test_combine_unmerge_dead_to_trunc_vec_out
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body: |
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bb.1:
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; CHECK-LABEL: name: test_combine_unmerge_dead_to_trunc_vec_out
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
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; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
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; CHECK: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[TRUNC]](s32)
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; CHECK: $w0 = COPY [[BITCAST]](<2 x s16>)
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%0:_(s64) = COPY $x0
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%1:_(<2 x s16>),%2:_(<2 x s16>) = G_UNMERGE_VALUES %0(s64)
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$w0 = COPY %1(<2 x s16>)
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...
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@ -12,9 +12,9 @@ body: |
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; CHECK-LABEL: name: narrow_shl_s64_32_s64amt
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; CHECK: liveins: $vgpr0_vgpr1
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
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; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
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; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C]](s32), [[UV]](s32)
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; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C]](s32), [[TRUNC]](s32)
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; CHECK: $vgpr0_vgpr1 = COPY [[MV]](s64)
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%0:_(s64) = COPY $vgpr0_vgpr1
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%1:_(s64) = G_CONSTANT i64 32
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@ -32,9 +32,9 @@ body: |
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; CHECK-LABEL: name: narrow_shl_s64_32
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; CHECK: liveins: $vgpr0_vgpr1
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
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; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
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; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C]](s32), [[UV]](s32)
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; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C]](s32), [[TRUNC]](s32)
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; CHECK: $vgpr0_vgpr1 = COPY [[MV]](s64)
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%0:_(s64) = COPY $vgpr0_vgpr1
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%1:_(s32) = G_CONSTANT i32 32
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@ -52,9 +52,9 @@ body: |
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; CHECK-LABEL: name: narrow_shl_s64_33
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; CHECK: liveins: $vgpr0_vgpr1
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
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; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
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; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
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; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UV]], [[C]](s32)
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; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]](s32)
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; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C1]](s32), [[SHL]](s32)
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; CHECK: $vgpr0_vgpr1 = COPY [[MV]](s64)
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@ -93,9 +93,9 @@ body: |
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; CHECK-LABEL: name: narrow_shl_s64_63
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; CHECK: liveins: $vgpr0_vgpr1
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
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; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
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; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
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; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UV]], [[C]](s32)
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; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]](s32)
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; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C1]](s32), [[SHL]](s32)
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; CHECK: $vgpr0_vgpr1 = COPY [[MV]](s64)
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@ -110,15 +110,16 @@ define amdgpu_ps void @image_store_v3f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t,
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; UNPACKED: [[COPY11:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr3
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; UNPACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
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; UNPACKED: [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
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; UNPACKED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
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; UNPACKED: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY10]](<2 x s16>)
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; UNPACKED: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[COPY10]](<2 x s16>), [[COPY11]](<2 x s16>), [[DEF]](<2 x s16>)
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; UNPACKED: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[CONCAT_VECTORS]](<6 x s16>)
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; UNPACKED: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BITCAST]](s96)
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; UNPACKED: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
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; UNPACKED: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
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; UNPACKED: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY11]](<2 x s16>)
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; UNPACKED: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
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; UNPACKED: [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
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; UNPACKED: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C]](s32)
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; UNPACKED: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
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; UNPACKED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
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; UNPACKED: [[COPY12:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
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; UNPACKED: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
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; UNPACKED: [[COPY14:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
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; UNPACKED: [[COPY14:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
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; UNPACKED: [[BUILD_VECTOR2:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32)
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; UNPACKED: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2d), [[BUILD_VECTOR2]](<3 x s32>), 7, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable store 6 into custom "TargetCustom8", align 8)
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; UNPACKED: S_ENDPGM 0
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@ -140,9 +141,29 @@ define amdgpu_ps void @image_store_v3f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t,
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; PACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
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; PACKED: [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
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; PACKED: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[COPY10]](<2 x s16>), [[COPY11]](<2 x s16>), [[DEF]](<2 x s16>)
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; PACKED: [[UV:%[0-9]+]]:_(<3 x s16>), [[UV1:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<6 x s16>)
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; PACKED: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[CONCAT_VECTORS]](<6 x s16>)
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; PACKED: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BITCAST]](s96)
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; PACKED: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
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; PACKED: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C]](s32)
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; PACKED: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
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; PACKED: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
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; PACKED: [[COPY12:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
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; PACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
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; PACKED: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
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; PACKED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C1]]
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; PACKED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
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; PACKED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
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; PACKED: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
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; PACKED: [[COPY14:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
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; PACKED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C1]]
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; PACKED: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; PACKED: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C]](s32)
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; PACKED: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
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; PACKED: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
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; PACKED: [[CONCAT_VECTORS1:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST1]](<2 x s16>), [[BITCAST2]](<2 x s16>), [[DEF]](<2 x s16>)
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; PACKED: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS1]](<6 x s16>), 0
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; PACKED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
|
||||
; PACKED: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2d), [[UV]](<3 x s16>), 7, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable store 6 into custom "TargetCustom8", align 8)
|
||||
; PACKED: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2d), [[EXTRACT]](<3 x s16>), 7, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable store 6 into custom "TargetCustom8", align 8)
|
||||
; PACKED: S_ENDPGM 0
|
||||
call void @llvm.amdgcn.image.store.2d.v3f16.i32(<3 x half> %in, i32 7, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret void
|
||||
|
||||
@ -174,22 +174,20 @@ define amdgpu_ps <3 x i32> @s_buffer_load_v3i32(<4 x i32> inreg %rsrc, i32 inreg
|
||||
; GFX6: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; GFX6: [[S_BUFFER_LOAD_DWORDX4_SGPR:%[0-9]+]]:sgpr_128 = S_BUFFER_LOAD_DWORDX4_SGPR [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load 12, align 4)
|
||||
; GFX6: [[DEF:%[0-9]+]]:sgpr_128 = IMPLICIT_DEF
|
||||
; GFX6: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_512_with_sub0_sub1_sub2 = REG_SEQUENCE [[S_BUFFER_LOAD_DWORDX4_SGPR]], %subreg.sub0_sub1_sub2_sub3, [[DEF]], %subreg.sub4_sub5_sub6_sub7, [[DEF]], %subreg.sub8_sub9_sub10_sub11
|
||||
; GFX6: [[COPY5:%[0-9]+]]:sgpr_96 = COPY [[REG_SEQUENCE1]].sub0_sub1_sub2
|
||||
; GFX6: [[COPY6:%[0-9]+]]:sgpr_96 = COPY [[REG_SEQUENCE1]].sub3_sub4_sub5
|
||||
; GFX6: [[COPY7:%[0-9]+]]:sgpr_96 = COPY [[REG_SEQUENCE1]].sub6_sub7_sub8
|
||||
; GFX6: [[COPY8:%[0-9]+]]:sgpr_96 = COPY [[REG_SEQUENCE1]].sub9_sub10_sub11
|
||||
; GFX6: [[COPY9:%[0-9]+]]:sreg_32 = COPY [[COPY5]].sub0
|
||||
; GFX6: [[COPY10:%[0-9]+]]:sreg_32 = COPY [[COPY5]].sub1
|
||||
; GFX6: [[COPY11:%[0-9]+]]:sreg_32 = COPY [[COPY5]].sub2
|
||||
; GFX6: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[COPY9]]
|
||||
; GFX6: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec
|
||||
; GFX6: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_512 = REG_SEQUENCE [[S_BUFFER_LOAD_DWORDX4_SGPR]], %subreg.sub0_sub1_sub2_sub3, [[DEF]], %subreg.sub4_sub5_sub6_sub7, [[DEF]], %subreg.sub8_sub9_sub10_sub11
|
||||
; GFX6: [[COPY5:%[0-9]+]]:sgpr_512_with_sub0_sub1_sub2 = COPY [[REG_SEQUENCE1]]
|
||||
; GFX6: [[COPY6:%[0-9]+]]:sgpr_96 = COPY [[COPY5]].sub0_sub1_sub2
|
||||
; GFX6: [[COPY7:%[0-9]+]]:sreg_32 = COPY [[COPY6]].sub0
|
||||
; GFX6: [[COPY8:%[0-9]+]]:sreg_32 = COPY [[COPY6]].sub1
|
||||
; GFX6: [[COPY9:%[0-9]+]]:sreg_32 = COPY [[COPY6]].sub2
|
||||
; GFX6: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY7]]
|
||||
; GFX6: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec
|
||||
; GFX6: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
|
||||
; GFX6: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[COPY10]]
|
||||
; GFX6: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY13]], implicit $exec
|
||||
; GFX6: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[COPY8]]
|
||||
; GFX6: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec
|
||||
; GFX6: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]]
|
||||
; GFX6: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[COPY11]]
|
||||
; GFX6: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY14]], implicit $exec
|
||||
; GFX6: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[COPY9]]
|
||||
; GFX6: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec
|
||||
; GFX6: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]]
|
||||
; GFX6: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2
|
||||
; GFX7-LABEL: name: s_buffer_load_v3i32
|
||||
@ -203,22 +201,20 @@ define amdgpu_ps <3 x i32> @s_buffer_load_v3i32(<4 x i32> inreg %rsrc, i32 inreg
|
||||
; GFX7: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; GFX7: [[S_BUFFER_LOAD_DWORDX4_SGPR:%[0-9]+]]:sgpr_128 = S_BUFFER_LOAD_DWORDX4_SGPR [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load 12, align 4)
|
||||
; GFX7: [[DEF:%[0-9]+]]:sgpr_128 = IMPLICIT_DEF
|
||||
; GFX7: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_512_with_sub0_sub1_sub2 = REG_SEQUENCE [[S_BUFFER_LOAD_DWORDX4_SGPR]], %subreg.sub0_sub1_sub2_sub3, [[DEF]], %subreg.sub4_sub5_sub6_sub7, [[DEF]], %subreg.sub8_sub9_sub10_sub11
|
||||
; GFX7: [[COPY5:%[0-9]+]]:sgpr_96 = COPY [[REG_SEQUENCE1]].sub0_sub1_sub2
|
||||
; GFX7: [[COPY6:%[0-9]+]]:sgpr_96 = COPY [[REG_SEQUENCE1]].sub3_sub4_sub5
|
||||
; GFX7: [[COPY7:%[0-9]+]]:sgpr_96 = COPY [[REG_SEQUENCE1]].sub6_sub7_sub8
|
||||
; GFX7: [[COPY8:%[0-9]+]]:sgpr_96 = COPY [[REG_SEQUENCE1]].sub9_sub10_sub11
|
||||
; GFX7: [[COPY9:%[0-9]+]]:sreg_32 = COPY [[COPY5]].sub0
|
||||
; GFX7: [[COPY10:%[0-9]+]]:sreg_32 = COPY [[COPY5]].sub1
|
||||
; GFX7: [[COPY11:%[0-9]+]]:sreg_32 = COPY [[COPY5]].sub2
|
||||
; GFX7: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[COPY9]]
|
||||
; GFX7: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec
|
||||
; GFX7: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_512 = REG_SEQUENCE [[S_BUFFER_LOAD_DWORDX4_SGPR]], %subreg.sub0_sub1_sub2_sub3, [[DEF]], %subreg.sub4_sub5_sub6_sub7, [[DEF]], %subreg.sub8_sub9_sub10_sub11
|
||||
; GFX7: [[COPY5:%[0-9]+]]:sgpr_512_with_sub0_sub1_sub2 = COPY [[REG_SEQUENCE1]]
|
||||
; GFX7: [[COPY6:%[0-9]+]]:sgpr_96 = COPY [[COPY5]].sub0_sub1_sub2
|
||||
; GFX7: [[COPY7:%[0-9]+]]:sreg_32 = COPY [[COPY6]].sub0
|
||||
; GFX7: [[COPY8:%[0-9]+]]:sreg_32 = COPY [[COPY6]].sub1
|
||||
; GFX7: [[COPY9:%[0-9]+]]:sreg_32 = COPY [[COPY6]].sub2
|
||||
; GFX7: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY7]]
|
||||
; GFX7: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec
|
||||
; GFX7: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
|
||||
; GFX7: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[COPY10]]
|
||||
; GFX7: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY13]], implicit $exec
|
||||
; GFX7: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[COPY8]]
|
||||
; GFX7: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec
|
||||
; GFX7: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]]
|
||||
; GFX7: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[COPY11]]
|
||||
; GFX7: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY14]], implicit $exec
|
||||
; GFX7: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[COPY9]]
|
||||
; GFX7: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec
|
||||
; GFX7: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]]
|
||||
; GFX7: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2
|
||||
; GFX8-LABEL: name: s_buffer_load_v3i32
|
||||
@ -232,22 +228,20 @@ define amdgpu_ps <3 x i32> @s_buffer_load_v3i32(<4 x i32> inreg %rsrc, i32 inreg
|
||||
; GFX8: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; GFX8: [[S_BUFFER_LOAD_DWORDX4_SGPR:%[0-9]+]]:sgpr_128 = S_BUFFER_LOAD_DWORDX4_SGPR [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load 12, align 4)
|
||||
; GFX8: [[DEF:%[0-9]+]]:sgpr_128 = IMPLICIT_DEF
|
||||
; GFX8: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_512_with_sub0_sub1_sub2 = REG_SEQUENCE [[S_BUFFER_LOAD_DWORDX4_SGPR]], %subreg.sub0_sub1_sub2_sub3, [[DEF]], %subreg.sub4_sub5_sub6_sub7, [[DEF]], %subreg.sub8_sub9_sub10_sub11
|
||||
; GFX8: [[COPY5:%[0-9]+]]:sgpr_96 = COPY [[REG_SEQUENCE1]].sub0_sub1_sub2
|
||||
; GFX8: [[COPY6:%[0-9]+]]:sgpr_96 = COPY [[REG_SEQUENCE1]].sub3_sub4_sub5
|
||||
; GFX8: [[COPY7:%[0-9]+]]:sgpr_96 = COPY [[REG_SEQUENCE1]].sub6_sub7_sub8
|
||||
; GFX8: [[COPY8:%[0-9]+]]:sgpr_96 = COPY [[REG_SEQUENCE1]].sub9_sub10_sub11
|
||||
; GFX8: [[COPY9:%[0-9]+]]:sreg_32 = COPY [[COPY5]].sub0
|
||||
; GFX8: [[COPY10:%[0-9]+]]:sreg_32 = COPY [[COPY5]].sub1
|
||||
; GFX8: [[COPY11:%[0-9]+]]:sreg_32 = COPY [[COPY5]].sub2
|
||||
; GFX8: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[COPY9]]
|
||||
; GFX8: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec
|
||||
; GFX8: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_512 = REG_SEQUENCE [[S_BUFFER_LOAD_DWORDX4_SGPR]], %subreg.sub0_sub1_sub2_sub3, [[DEF]], %subreg.sub4_sub5_sub6_sub7, [[DEF]], %subreg.sub8_sub9_sub10_sub11
|
||||
; GFX8: [[COPY5:%[0-9]+]]:sgpr_512_with_sub0_sub1_sub2 = COPY [[REG_SEQUENCE1]]
|
||||
; GFX8: [[COPY6:%[0-9]+]]:sgpr_96 = COPY [[COPY5]].sub0_sub1_sub2
|
||||
; GFX8: [[COPY7:%[0-9]+]]:sreg_32 = COPY [[COPY6]].sub0
|
||||
; GFX8: [[COPY8:%[0-9]+]]:sreg_32 = COPY [[COPY6]].sub1
|
||||
; GFX8: [[COPY9:%[0-9]+]]:sreg_32 = COPY [[COPY6]].sub2
|
||||
; GFX8: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY7]]
|
||||
; GFX8: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec
|
||||
; GFX8: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
|
||||
; GFX8: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[COPY10]]
|
||||
; GFX8: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY13]], implicit $exec
|
||||
; GFX8: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[COPY8]]
|
||||
; GFX8: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec
|
||||
; GFX8: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]]
|
||||
; GFX8: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[COPY11]]
|
||||
; GFX8: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY14]], implicit $exec
|
||||
; GFX8: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[COPY9]]
|
||||
; GFX8: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec
|
||||
; GFX8: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]]
|
||||
; GFX8: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2
|
||||
%val = call <3 x i32> @llvm.amdgcn.s.buffer.load.v3i32(<4 x i32> %rsrc, i32 %soffset, i32 0)
|
||||
@ -1600,15 +1594,12 @@ define amdgpu_ps <3 x float> @s_buffer_load_v3f32_vgpr_offset(<4 x i32> inreg %r
|
||||
; GFX6: [[COPY6:%[0-9]+]]:vreg_128 = COPY [[DEF]]
|
||||
; GFX6: [[REG_SEQUENCE1:%[0-9]+]]:vreg_512 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[COPY5]], %subreg.sub4_sub5_sub6_sub7, [[COPY6]], %subreg.sub8_sub9_sub10_sub11
|
||||
; GFX6: [[COPY7:%[0-9]+]]:vreg_96 = COPY [[REG_SEQUENCE1]].sub0_sub1_sub2
|
||||
; GFX6: [[COPY8:%[0-9]+]]:vreg_96 = COPY [[REG_SEQUENCE1]].sub3_sub4_sub5
|
||||
; GFX6: [[COPY9:%[0-9]+]]:vreg_96 = COPY [[REG_SEQUENCE1]].sub6_sub7_sub8
|
||||
; GFX6: [[COPY10:%[0-9]+]]:vreg_96 = COPY [[REG_SEQUENCE1]].sub9_sub10_sub11
|
||||
; GFX6: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[COPY7]].sub0
|
||||
; GFX6: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[COPY7]].sub1
|
||||
; GFX6: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[COPY7]].sub2
|
||||
; GFX6: $vgpr0 = COPY [[COPY11]]
|
||||
; GFX6: $vgpr1 = COPY [[COPY12]]
|
||||
; GFX6: $vgpr2 = COPY [[COPY13]]
|
||||
; GFX6: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY7]].sub0
|
||||
; GFX6: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY7]].sub1
|
||||
; GFX6: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY7]].sub2
|
||||
; GFX6: $vgpr0 = COPY [[COPY8]]
|
||||
; GFX6: $vgpr1 = COPY [[COPY9]]
|
||||
; GFX6: $vgpr2 = COPY [[COPY10]]
|
||||
; GFX6: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2
|
||||
; GFX7-LABEL: name: s_buffer_load_v3f32_vgpr_offset
|
||||
; GFX7: bb.1 (%ir-block.0):
|
||||
@ -1626,15 +1617,12 @@ define amdgpu_ps <3 x float> @s_buffer_load_v3f32_vgpr_offset(<4 x i32> inreg %r
|
||||
; GFX7: [[COPY6:%[0-9]+]]:vreg_128 = COPY [[DEF]]
|
||||
; GFX7: [[REG_SEQUENCE1:%[0-9]+]]:vreg_512 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[COPY5]], %subreg.sub4_sub5_sub6_sub7, [[COPY6]], %subreg.sub8_sub9_sub10_sub11
|
||||
; GFX7: [[COPY7:%[0-9]+]]:vreg_96 = COPY [[REG_SEQUENCE1]].sub0_sub1_sub2
|
||||
; GFX7: [[COPY8:%[0-9]+]]:vreg_96 = COPY [[REG_SEQUENCE1]].sub3_sub4_sub5
|
||||
; GFX7: [[COPY9:%[0-9]+]]:vreg_96 = COPY [[REG_SEQUENCE1]].sub6_sub7_sub8
|
||||
; GFX7: [[COPY10:%[0-9]+]]:vreg_96 = COPY [[REG_SEQUENCE1]].sub9_sub10_sub11
|
||||
; GFX7: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[COPY7]].sub0
|
||||
; GFX7: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[COPY7]].sub1
|
||||
; GFX7: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[COPY7]].sub2
|
||||
; GFX7: $vgpr0 = COPY [[COPY11]]
|
||||
; GFX7: $vgpr1 = COPY [[COPY12]]
|
||||
; GFX7: $vgpr2 = COPY [[COPY13]]
|
||||
; GFX7: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY7]].sub0
|
||||
; GFX7: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY7]].sub1
|
||||
; GFX7: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY7]].sub2
|
||||
; GFX7: $vgpr0 = COPY [[COPY8]]
|
||||
; GFX7: $vgpr1 = COPY [[COPY9]]
|
||||
; GFX7: $vgpr2 = COPY [[COPY10]]
|
||||
; GFX7: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2
|
||||
; GFX8-LABEL: name: s_buffer_load_v3f32_vgpr_offset
|
||||
; GFX8: bb.1 (%ir-block.0):
|
||||
@ -1652,15 +1640,12 @@ define amdgpu_ps <3 x float> @s_buffer_load_v3f32_vgpr_offset(<4 x i32> inreg %r
|
||||
; GFX8: [[COPY6:%[0-9]+]]:vreg_128 = COPY [[DEF]]
|
||||
; GFX8: [[REG_SEQUENCE1:%[0-9]+]]:vreg_512 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[COPY5]], %subreg.sub4_sub5_sub6_sub7, [[COPY6]], %subreg.sub8_sub9_sub10_sub11
|
||||
; GFX8: [[COPY7:%[0-9]+]]:vreg_96 = COPY [[REG_SEQUENCE1]].sub0_sub1_sub2
|
||||
; GFX8: [[COPY8:%[0-9]+]]:vreg_96 = COPY [[REG_SEQUENCE1]].sub3_sub4_sub5
|
||||
; GFX8: [[COPY9:%[0-9]+]]:vreg_96 = COPY [[REG_SEQUENCE1]].sub6_sub7_sub8
|
||||
; GFX8: [[COPY10:%[0-9]+]]:vreg_96 = COPY [[REG_SEQUENCE1]].sub9_sub10_sub11
|
||||
; GFX8: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[COPY7]].sub0
|
||||
; GFX8: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[COPY7]].sub1
|
||||
; GFX8: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[COPY7]].sub2
|
||||
; GFX8: $vgpr0 = COPY [[COPY11]]
|
||||
; GFX8: $vgpr1 = COPY [[COPY12]]
|
||||
; GFX8: $vgpr2 = COPY [[COPY13]]
|
||||
; GFX8: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY7]].sub0
|
||||
; GFX8: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY7]].sub1
|
||||
; GFX8: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY7]].sub2
|
||||
; GFX8: $vgpr0 = COPY [[COPY8]]
|
||||
; GFX8: $vgpr1 = COPY [[COPY9]]
|
||||
; GFX8: $vgpr2 = COPY [[COPY10]]
|
||||
; GFX8: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2
|
||||
%val = call <3 x float> @llvm.amdgcn.s.buffer.load.v3f32(<4 x i32> %rsrc, i32 %soffset, i32 0)
|
||||
ret <3 x float> %val
|
||||
|
||||
@ -37,8 +37,9 @@ body: |
|
||||
; GCN-LABEL: name: select_from_same_results_of_unmerge_values
|
||||
; GCN: liveins: $vgpr0
|
||||
; GCN: [[DEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
|
||||
; GCN: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<2 x s32>)
|
||||
; GCN: $vgpr0 = COPY [[UV]](s32)
|
||||
; GCN: [[BITCAST:%[0-9]+]]:_(s64) = G_BITCAST [[DEF]](<2 x s32>)
|
||||
; GCN: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[BITCAST]](s64)
|
||||
; GCN: $vgpr0 = COPY [[TRUNC]](s32)
|
||||
; GCN: SI_RETURN_TO_EPILOG $vgpr0
|
||||
%0:_(<2 x s32>) = G_IMPLICIT_DEF
|
||||
%1:_(s32) = COPY $vgpr0
|
||||
|
||||
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Reference in New Issue
Block a user