mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-24 03:33:20 +01:00
Somehow, custom lowering of i64 multiplications got dropped along the way.
llvm-svn: 53689
This commit is contained in:
Scott Michel
parent
4c8c8e3aad
commit
ba160e6396
@ -42,7 +42,7 @@ namespace {
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const MVT valtype;
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const int prefslot_byte;
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};
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const valtype_map_s valtype_map[] = {
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{ MVT::i1, 3 },
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{ MVT::i8, 3 },
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@ -120,7 +120,7 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM)
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// Use _setjmp/_longjmp instead of setjmp/longjmp.
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setUseUnderscoreSetJmp(true);
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setUseUnderscoreLongJmp(true);
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// Set up the SPU's register classes:
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addRegisterClass(MVT::i8, SPU::R8CRegisterClass);
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addRegisterClass(MVT::i16, SPU::R16CRegisterClass);
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@ -129,7 +129,7 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM)
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addRegisterClass(MVT::f32, SPU::R32FPRegisterClass);
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addRegisterClass(MVT::f64, SPU::R64FPRegisterClass);
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addRegisterClass(MVT::i128, SPU::GPRCRegisterClass);
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// SPU has no sign or zero extended loads for i1, i8, i16:
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setLoadXAction(ISD::EXTLOAD, MVT::i1, Promote);
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setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
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@ -148,7 +148,7 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM)
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setTruncStoreAction(MVT::i32 , MVT::i8, Custom);
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setTruncStoreAction(MVT::i64 , MVT::i8, Custom);
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setTruncStoreAction(MVT::i128, MVT::i8, Custom);
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setLoadXAction(ISD::EXTLOAD, MVT::i16, Custom);
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setLoadXAction(ISD::SEXTLOAD, MVT::i16, Custom);
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setLoadXAction(ISD::ZEXTLOAD, MVT::i16, Custom);
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@ -174,7 +174,7 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM)
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// Expand the jumptable branches
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setOperationAction(ISD::BR_JT, MVT::Other, Expand);
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setOperationAction(ISD::BR_CC, MVT::Other, Expand);
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setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
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setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
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// SPU has no intrinsics for these particular operations:
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setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
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@ -184,7 +184,7 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM)
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setOperationAction(ISD::UREM, MVT::i32, Expand);
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setOperationAction(ISD::SREM, MVT::i64, Expand);
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setOperationAction(ISD::UREM, MVT::i64, Expand);
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// We don't support sin/cos/sqrt/fmod
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setOperationAction(ISD::FSIN , MVT::f64, Expand);
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setOperationAction(ISD::FCOS , MVT::f64, Expand);
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@ -192,11 +192,11 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM)
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setOperationAction(ISD::FSIN , MVT::f32, Expand);
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setOperationAction(ISD::FCOS , MVT::f32, Expand);
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setOperationAction(ISD::FREM , MVT::f32, Expand);
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// If we're enabling GP optimizations, use hardware square root
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setOperationAction(ISD::FSQRT, MVT::f64, Expand);
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setOperationAction(ISD::FSQRT, MVT::f32, Expand);
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setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
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setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
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@ -217,15 +217,16 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM)
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setOperationAction(ISD::SRL, MVT::i64, Custom);
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setOperationAction(ISD::SRA, MVT::i64, Custom);
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// Custom lower i32 multiplications
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// Custom lower i8, i32 and i64 multiplications
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setOperationAction(ISD::MUL, MVT::i8, Custom);
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setOperationAction(ISD::MUL, MVT::i32, Custom);
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setOperationAction(ISD::MUL, MVT::i64, Custom);
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// Need to custom handle (some) common i8, i64 math ops
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setOperationAction(ISD::ADD, MVT::i64, Custom);
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setOperationAction(ISD::SUB, MVT::i8, Custom);
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setOperationAction(ISD::SUB, MVT::i64, Custom);
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setOperationAction(ISD::MUL, MVT::i8, Custom);
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// SPU does not have BSWAP. It does have i32 support CTLZ.
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// CTPOP has to be custom lowered.
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setOperationAction(ISD::BSWAP, MVT::i32, Expand);
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@ -240,7 +241,7 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM)
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setOperationAction(ISD::CTTZ , MVT::i64, Expand);
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setOperationAction(ISD::CTLZ , MVT::i32, Legal);
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// SPU has a version of select that implements (a&~c)|(b&c), just like
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// select ought to work:
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setOperationAction(ISD::SELECT, MVT::i1, Promote);
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@ -260,7 +261,7 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM)
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setOperationAction(ISD::ZERO_EXTEND, MVT::i64, Custom);
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setOperationAction(ISD::SIGN_EXTEND, MVT::i64, Custom);
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setOperationAction(ISD::ANY_EXTEND, MVT::i64, Custom);
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// SPU has a legal FP -> signed INT instruction
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setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
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setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
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@ -288,12 +289,12 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM)
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// We cannot sextinreg(i1). Expand to shifts.
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
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// Support label based line numbers.
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setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
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setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
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// We want to legalize GlobalAddress and ConstantPool nodes into the
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// We want to legalize GlobalAddress and ConstantPool nodes into the
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// appropriate instructions to materialize the address.
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for (unsigned sctype = (unsigned) MVT::i1; sctype < (unsigned) MVT::f128;
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++sctype) {
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@ -306,15 +307,15 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM)
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// RET must be custom lowered, to meet ABI requirements
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setOperationAction(ISD::RET, MVT::Other, Custom);
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// VASTART needs to be custom lowered to use the VarArgsFrameIndex
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setOperationAction(ISD::VASTART , MVT::Other, Custom);
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// Use the default implementation.
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setOperationAction(ISD::VAARG , MVT::Other, Expand);
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setOperationAction(ISD::VACOPY , MVT::Other, Expand);
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setOperationAction(ISD::VAEND , MVT::Other, Expand);
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setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
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setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
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setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
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setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand);
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setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Expand);
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@ -322,7 +323,7 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM)
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// Cell SPU has instructions for converting between i64 and fp.
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setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
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setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
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// To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT
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setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote);
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@ -354,7 +355,7 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM)
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setOperationAction(ISD::LOAD , VT, Legal);
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setOperationAction(ISD::SELECT, VT, Legal);
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setOperationAction(ISD::STORE, VT, Legal);
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// These operations need to be expanded:
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setOperationAction(ISD::SDIV, VT, Expand);
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setOperationAction(ISD::SREM, VT, Expand);
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@ -380,15 +381,15 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM)
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setShiftAmountType(MVT::i32);
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setSetCCResultContents(ZeroOrOneSetCCResult);
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setStackPointerRegisterToSaveRestore(SPU::R1);
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// We have target-specific dag combine patterns for the following nodes:
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setTargetDAGCombine(ISD::ADD);
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setTargetDAGCombine(ISD::ZERO_EXTEND);
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setTargetDAGCombine(ISD::SIGN_EXTEND);
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setTargetDAGCombine(ISD::ANY_EXTEND);
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computeRegisterProperties();
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}
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@ -618,7 +619,7 @@ LowerLOAD(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
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if (VT == OpVT || ExtType == ISD::EXTLOAD) {
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SDVTList scalarvts;
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MVT vecVT = MVT::v16i8;
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// Convert the loaded v16i8 vector to the appropriate vector type
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// specified by the operand:
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if (OpVT == VT) {
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@ -698,7 +699,7 @@ LowerSTORE(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
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// The vector type we really want to load from the 16-byte chunk, except
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// in the case of MVT::i1, which has to be v16i8.
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MVT vecVT, stVecVT = MVT::v16i8;
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if (StVT != MVT::i1)
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stVecVT = MVT::getVectorVT(StVT, (128 / StVT.getSizeInBits()));
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vecVT = MVT::getVectorVT(VT, (128 / VT.getSizeInBits()));
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@ -721,7 +722,7 @@ LowerSTORE(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
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|| theValue.getOpcode() == ISD::AssertSext)) {
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// Drill down and get the value for zero- and sign-extended
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// quantities
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theValue = theValue.getOperand(0);
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theValue = theValue.getOperand(0);
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}
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chunk_offset &= 0xf;
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@ -831,7 +832,7 @@ LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
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SDOperand GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset());
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const TargetMachine &TM = DAG.getTarget();
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SDOperand Zero = DAG.getConstant(0, PtrVT);
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if (TM.getRelocationModel() == Reloc::Static) {
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if (!ST->usingLargeMem()) {
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return DAG.getNode(SPUISD::AFormAddr, PtrVT, GA, Zero);
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@ -923,13 +924,13 @@ LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, int &VarArgsFrameIndex)
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const unsigned *ArgRegs = SPURegisterInfo::getArgRegs();
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const unsigned NumArgRegs = SPURegisterInfo::getNumArgRegs();
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unsigned ArgOffset = SPUFrameInfo::minStackSize();
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unsigned ArgRegIdx = 0;
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unsigned StackSlotSize = SPUFrameInfo::stackSlotSize();
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MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
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// Add DAG nodes to load the arguments or copy them out of registers.
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for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) {
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SDOperand ArgVal;
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@ -1020,7 +1021,7 @@ LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, int &VarArgsFrameIndex)
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}
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break;
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}
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// We need to load the argument to a virtual register if we determined above
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// that we ran out of physical registers of the appropriate type
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if (needsLoad) {
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@ -1029,10 +1030,10 @@ LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, int &VarArgsFrameIndex)
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ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
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ArgOffset += StackSlotSize;
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}
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ArgValues.push_back(ArgVal);
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}
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// If the function takes variable number of arguments, make a frame index for
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// the start of the first vararg value... for expansion of llvm.va_start.
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if (isVarArg) {
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@ -1056,9 +1057,9 @@ LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, int &VarArgsFrameIndex)
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if (!MemOps.empty())
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Root = DAG.getNode(ISD::TokenFactor, MVT::Other,&MemOps[0],MemOps.size());
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}
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ArgValues.push_back(Root);
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// Return the new list of results.
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return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0],
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ArgValues.size());
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@ -1069,12 +1070,12 @@ LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, int &VarArgsFrameIndex)
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static SDNode *isLSAAddress(SDOperand Op, SelectionDAG &DAG) {
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ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
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if (!C) return 0;
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int Addr = C->getValue();
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if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
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(Addr << 14 >> 14) != Addr)
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return 0; // Top 14 bits have to be sext of immediate.
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return DAG.getConstant((int)C->getValue() >> 2, MVT::i32).Val;
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}
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@ -1094,17 +1095,17 @@ LowerCALL(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
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// Handy pointer type
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MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
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// Accumulate how many bytes are to be pushed on the stack, including the
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// linkage area, and parameter passing area. According to the SPU ABI,
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// we minimally need space for [LR] and [SP]
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unsigned NumStackBytes = SPUFrameInfo::minStackSize();
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// Set up a copy of the stack pointer for use loading and storing any
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// arguments that may not fit in the registers available for argument
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// passing.
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SDOperand StackPtr = DAG.getRegister(SPU::R1, MVT::i32);
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// Figure out which arguments are going to go in registers, and which in
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// memory.
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unsigned ArgOffset = SPUFrameInfo::minStackSize(); // Just below [LR]
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@ -1117,7 +1118,7 @@ LowerCALL(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
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for (unsigned i = 0; i != NumOps; ++i) {
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SDOperand Arg = Op.getOperand(5+2*i);
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// PtrOff will be used to store the current argument to the stack if a
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// register cannot be found for it.
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SDOperand PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
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@ -1167,7 +1168,7 @@ LowerCALL(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
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Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
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&MemOpChains[0], MemOpChains.size());
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}
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// Build a sequence of copy-to-reg nodes chained together with token chain
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// and flag operands which copy the outgoing args into the appropriate regs.
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SDOperand InFlag;
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@ -1176,10 +1177,10 @@ LowerCALL(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
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InFlag);
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InFlag = Chain.getValue(1);
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}
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SmallVector<SDOperand, 8> Ops;
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unsigned CallOpc = SPUISD::CALL;
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// If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
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// direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
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// node so that legalize doesn't hack it.
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@ -1218,13 +1219,13 @@ LowerCALL(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
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Ops.push_back(Chain);
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Ops.push_back(Callee);
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// Add argument registers to the end of the list so that they are known live
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// into the call.
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for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
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Ops.push_back(DAG.getRegister(RegsToPass[i].first,
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Ops.push_back(DAG.getRegister(RegsToPass[i].first,
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RegsToPass[i].second.getValueType()));
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if (InFlag.Val)
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Ops.push_back(InFlag);
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// Returns a chain and a flag for retval copy to use.
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@ -1241,7 +1242,7 @@ LowerCALL(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
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SDOperand ResultVals[3];
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unsigned NumResults = 0;
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// If the call has results, copy the values out of the ret val registers.
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switch (Op.Val->getValueType(0).getSimpleVT()) {
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default: assert(0 && "Unexpected ret value!");
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@ -1287,7 +1288,7 @@ LowerCALL(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
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// If the function returns void, just return the chain.
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if (NumResults == 0)
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return Chain;
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// Otherwise, merge everything together with a MERGE_VALUES node.
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ResultVals[NumResults++] = Chain;
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SDOperand Res = DAG.getMergeValues(ResultVals, NumResults);
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@ -1301,7 +1302,7 @@ LowerRET(SDOperand Op, SelectionDAG &DAG, TargetMachine &TM) {
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bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
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CCState CCInfo(CC, isVarArg, TM, RVLocs);
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CCInfo.AnalyzeReturn(Op.Val, RetCC_SPU);
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// If this is the first return lowered for this function, add the regs to the
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// liveout set for the function.
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if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
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@ -1311,7 +1312,7 @@ LowerRET(SDOperand Op, SelectionDAG &DAG, TargetMachine &TM) {
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SDOperand Chain = Op.getOperand(0);
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SDOperand Flag;
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// Copy the result values into the output registers.
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for (unsigned i = 0; i != RVLocs.size(); ++i) {
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CCValAssign &VA = RVLocs[i];
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@ -1334,7 +1335,7 @@ LowerRET(SDOperand Op, SelectionDAG &DAG, TargetMachine &TM) {
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static ConstantSDNode *
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getVecImm(SDNode *N) {
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SDOperand OpVal(0, 0);
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// Check to see if this buildvec has a single non-undef value in its elements.
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for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
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if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
|
||||
@ -1343,7 +1344,7 @@ getVecImm(SDNode *N) {
|
||||
else if (OpVal != N->getOperand(i))
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
if (OpVal.Val != 0) {
|
||||
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
|
||||
return CN;
|
||||
@ -1478,7 +1479,7 @@ SDOperand SPU::get_v2i64_imm(SDNode *N, SelectionDAG &DAG) {
|
||||
}
|
||||
|
||||
// If this is a vector of constants or undefs, get the bits. A bit in
|
||||
// UndefBits is set if the corresponding element of the vector is an
|
||||
// UndefBits is set if the corresponding element of the vector is an
|
||||
// ISD::UNDEF value. For undefs, the corresponding VectorBits values are
|
||||
// zero. Return true if this is not an array of constants, false if it is.
|
||||
//
|
||||
@ -1486,11 +1487,11 @@ static bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2],
|
||||
uint64_t UndefBits[2]) {
|
||||
// Start with zero'd results.
|
||||
VectorBits[0] = VectorBits[1] = UndefBits[0] = UndefBits[1] = 0;
|
||||
|
||||
|
||||
unsigned EltBitSize = BV->getOperand(0).getValueType().getSizeInBits();
|
||||
for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
|
||||
SDOperand OpVal = BV->getOperand(i);
|
||||
|
||||
|
||||
unsigned PartNo = i >= e/2; // In the upper 128 bits?
|
||||
unsigned SlotNo = e/2 - (i & (e/2-1))-1; // Which subpiece of the uint64_t.
|
||||
|
||||
@ -1510,20 +1511,20 @@ static bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2],
|
||||
// Nonconstant element.
|
||||
return true;
|
||||
}
|
||||
|
||||
|
||||
VectorBits[PartNo] |= EltBits << (SlotNo*EltBitSize);
|
||||
}
|
||||
|
||||
//printf("%llx %llx %llx %llx\n",
|
||||
|
||||
//printf("%llx %llx %llx %llx\n",
|
||||
// VectorBits[0], VectorBits[1], UndefBits[0], UndefBits[1]);
|
||||
return false;
|
||||
}
|
||||
|
||||
/// If this is a splat (repetition) of a value across the whole vector, return
|
||||
/// the smallest size that splats it. For example, "0x01010101010101..." is a
|
||||
/// splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
|
||||
/// splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
|
||||
/// SplatSize = 1 byte.
|
||||
static bool isConstantSplat(const uint64_t Bits128[2],
|
||||
static bool isConstantSplat(const uint64_t Bits128[2],
|
||||
const uint64_t Undef128[2],
|
||||
int MinSplatBits,
|
||||
uint64_t &SplatBits, uint64_t &SplatUndef,
|
||||
@ -1539,7 +1540,7 @@ static bool isConstantSplat(const uint64_t Bits128[2],
|
||||
|
||||
if ((Bits128[0] & ~Undef128[1]) == (Bits128[1] & ~Undef128[0])) {
|
||||
if (MinSplatBits < 64) {
|
||||
|
||||
|
||||
// Check that the top 32-bits are the same as the lower 32-bits, ignoring
|
||||
// undefs.
|
||||
if ((Bits64 & (~Undef64 >> 32)) == ((Bits64 >> 32) & ~Undef64)) {
|
||||
@ -1591,9 +1592,9 @@ static bool isConstantSplat(const uint64_t Bits128[2],
|
||||
static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
|
||||
MVT VT = Op.getValueType();
|
||||
// If this is a vector of constants or undefs, get the bits. A bit in
|
||||
// UndefBits is set if the corresponding element of the vector is an
|
||||
// UndefBits is set if the corresponding element of the vector is an
|
||||
// ISD::UNDEF value. For undefs, the corresponding VectorBits values are
|
||||
// zero.
|
||||
// zero.
|
||||
uint64_t VectorBits[2];
|
||||
uint64_t UndefBits[2];
|
||||
uint64_t SplatBits, SplatUndef;
|
||||
@ -1603,7 +1604,7 @@ static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
|
||||
VT.getVectorElementType().getSizeInBits(),
|
||||
SplatBits, SplatUndef, SplatSize))
|
||||
return SDOperand(); // Not a constant vector, not a splat.
|
||||
|
||||
|
||||
switch (VT.getSimpleVT()) {
|
||||
default:
|
||||
case MVT::v4f32: {
|
||||
@ -1637,7 +1638,7 @@ static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
|
||||
}
|
||||
case MVT::v8i16: {
|
||||
unsigned short Value16;
|
||||
if (SplatSize == 2)
|
||||
if (SplatSize == 2)
|
||||
Value16 = (unsigned short) (SplatBits & 0xffff);
|
||||
else
|
||||
Value16 = (unsigned short) (SplatBits | (SplatBits << 8));
|
||||
@ -1737,7 +1738,7 @@ static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
return SDOperand();
|
||||
}
|
||||
|
||||
@ -1758,9 +1759,9 @@ static SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
|
||||
SDOperand V1 = Op.getOperand(0);
|
||||
SDOperand V2 = Op.getOperand(1);
|
||||
SDOperand PermMask = Op.getOperand(2);
|
||||
|
||||
|
||||
if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
|
||||
|
||||
|
||||
// If we have a single element being moved from V1 to V2, this can be handled
|
||||
// using the C*[DX] compute mask instructions, but the vector elements have
|
||||
// to be monotonically increasing with one exception element.
|
||||
@ -1785,7 +1786,7 @@ static SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
|
||||
unsigned SrcElt;
|
||||
if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF)
|
||||
SrcElt = 0;
|
||||
else
|
||||
else
|
||||
SrcElt = cast<ConstantSDNode>(PermMask.getOperand(i))->getValue();
|
||||
|
||||
if (SrcElt >= V2EltIdx0) {
|
||||
@ -1817,21 +1818,21 @@ static SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
|
||||
} else {
|
||||
// Convert the SHUFFLE_VECTOR mask's input element units to the actual bytes.
|
||||
unsigned BytesPerElement = EltVT.getSizeInBits()/8;
|
||||
|
||||
|
||||
SmallVector<SDOperand, 16> ResultMask;
|
||||
for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) {
|
||||
unsigned SrcElt;
|
||||
if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF)
|
||||
SrcElt = 0;
|
||||
else
|
||||
else
|
||||
SrcElt = cast<ConstantSDNode>(PermMask.getOperand(i))->getValue();
|
||||
|
||||
|
||||
for (unsigned j = 0; j < BytesPerElement; ++j) {
|
||||
ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
|
||||
MVT::i8));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
SDOperand VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8,
|
||||
&ResultMask[0], ResultMask.size());
|
||||
return DAG.getNode(SPUISD::SHUFB, V1.getValueType(), V1, V2, VPermMask);
|
||||
@ -1979,7 +1980,7 @@ static SDOperand LowerVectorMUL(SDOperand Op, SelectionDAG &DAG) {
|
||||
|
||||
SDOperand LoProdMask = DAG.getConstant(0xffff, MVT::i32);
|
||||
|
||||
SDOperand LoProd =
|
||||
SDOperand LoProd =
|
||||
DAG.getNode(ISD::AND, MVT::v4i32,
|
||||
LoProdParts,
|
||||
DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32,
|
||||
@ -2047,24 +2048,24 @@ static SDOperand LowerFDIVf32(SDOperand Op, SelectionDAG &DAG) {
|
||||
// Computes BRcpl =
|
||||
// (Floating Interpolate (FP Reciprocal Estimate B))
|
||||
SDOperand BRcpl =
|
||||
DAG.getCopyToReg(DAG.getEntryNode(), VRegBR,
|
||||
DAG.getNode(SPUISD::FPInterp, VT, B,
|
||||
DAG.getCopyToReg(DAG.getEntryNode(), VRegBR,
|
||||
DAG.getNode(SPUISD::FPInterp, VT, B,
|
||||
DAG.getNode(SPUISD::FPRecipEst, VT, B)));
|
||||
|
||||
|
||||
// Computes A * BRcpl and stores in a temporary register
|
||||
SDOperand AxBRcpl =
|
||||
DAG.getCopyToReg(BRcpl, VRegC,
|
||||
DAG.getNode(ISD::FMUL, VT, A,
|
||||
DAG.getNode(ISD::FMUL, VT, A,
|
||||
DAG.getCopyFromReg(BRcpl, VRegBR, VT)));
|
||||
// What's the Chain variable do? It's magic!
|
||||
// TODO: set Chain = Op(0).getEntryNode()
|
||||
|
||||
return DAG.getNode(ISD::FADD, VT,
|
||||
|
||||
return DAG.getNode(ISD::FADD, VT,
|
||||
DAG.getCopyFromReg(AxBRcpl, VRegC, VT),
|
||||
DAG.getNode(ISD::FMUL, VT,
|
||||
DAG.getCopyFromReg(AxBRcpl, VRegBR, VT),
|
||||
DAG.getNode(ISD::FMUL, VT,
|
||||
DAG.getCopyFromReg(AxBRcpl, VRegBR, VT),
|
||||
DAG.getNode(ISD::FSUB, VT, A,
|
||||
DAG.getNode(ISD::FMUL, VT, B,
|
||||
DAG.getNode(ISD::FMUL, VT, B,
|
||||
DAG.getCopyFromReg(AxBRcpl, VRegC, VT)))));
|
||||
}
|
||||
|
||||
@ -2134,7 +2135,7 @@ static SDOperand LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
|
||||
: elt_byte + (i - prefslot_begin));
|
||||
|
||||
ShufMask[i] = DAG.getConstant(mask_val, MVT::i8);
|
||||
} else
|
||||
} else
|
||||
ShufMask[i] = ShufMask[i % (prefslot_end + 1)];
|
||||
}
|
||||
|
||||
@ -2146,7 +2147,7 @@ static SDOperand LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
|
||||
return DAG.getNode(SPUISD::EXTRACT_ELT0, VT,
|
||||
DAG.getNode(SPUISD::SHUFB, N.getValueType(),
|
||||
N, N, ShufMaskVec));
|
||||
|
||||
|
||||
}
|
||||
|
||||
static SDOperand LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
|
||||
@ -2195,9 +2196,9 @@ static SDOperand LowerI8Math(SDOperand Op, SelectionDAG &DAG, unsigned Opc)
|
||||
N1 = (N1.getOpcode() != ISD::Constant
|
||||
? DAG.getNode(ISD::SIGN_EXTEND, MVT::i16, N1)
|
||||
: DAG.getConstant(cast<ConstantSDNode>(N1)->getValue(), MVT::i16));
|
||||
return DAG.getNode(ISD::TRUNCATE, MVT::i8,
|
||||
return DAG.getNode(ISD::TRUNCATE, MVT::i8,
|
||||
DAG.getNode(Opc, MVT::i16, N0, N1));
|
||||
}
|
||||
}
|
||||
case ISD::ROTR:
|
||||
case ISD::ROTL: {
|
||||
SDOperand N1 = Op.getOperand(1);
|
||||
@ -2213,7 +2214,7 @@ static SDOperand LowerI8Math(SDOperand Op, SelectionDAG &DAG, unsigned Opc)
|
||||
DAG.getNode(ISD::OR, MVT::i16, N0,
|
||||
DAG.getNode(ISD::SHL, MVT::i16,
|
||||
N0, DAG.getConstant(8, MVT::i16)));
|
||||
return DAG.getNode(ISD::TRUNCATE, MVT::i8,
|
||||
return DAG.getNode(ISD::TRUNCATE, MVT::i8,
|
||||
DAG.getNode(Opc, MVT::i16, ExpandArg, N1));
|
||||
}
|
||||
case ISD::SRL:
|
||||
@ -2227,7 +2228,7 @@ static SDOperand LowerI8Math(SDOperand Op, SelectionDAG &DAG, unsigned Opc)
|
||||
N1 = (N1.getOpcode() != ISD::Constant
|
||||
? DAG.getNode(N1Opc, MVT::i16, N1)
|
||||
: DAG.getConstant(cast<ConstantSDNode>(N1)->getValue(), MVT::i16));
|
||||
return DAG.getNode(ISD::TRUNCATE, MVT::i8,
|
||||
return DAG.getNode(ISD::TRUNCATE, MVT::i8,
|
||||
DAG.getNode(Opc, MVT::i16, N0, N1));
|
||||
}
|
||||
case ISD::SRA: {
|
||||
@ -2240,7 +2241,7 @@ static SDOperand LowerI8Math(SDOperand Op, SelectionDAG &DAG, unsigned Opc)
|
||||
N1 = (N1.getOpcode() != ISD::Constant
|
||||
? DAG.getNode(N1Opc, MVT::i16, N1)
|
||||
: DAG.getConstant(cast<ConstantSDNode>(N1)->getValue(), MVT::i16));
|
||||
return DAG.getNode(ISD::TRUNCATE, MVT::i8,
|
||||
return DAG.getNode(ISD::TRUNCATE, MVT::i8,
|
||||
DAG.getNode(Opc, MVT::i16, N0, N1));
|
||||
}
|
||||
case ISD::MUL: {
|
||||
@ -2253,7 +2254,7 @@ static SDOperand LowerI8Math(SDOperand Op, SelectionDAG &DAG, unsigned Opc)
|
||||
N1 = (N1.getOpcode() != ISD::Constant
|
||||
? DAG.getNode(N1Opc, MVT::i16, N1)
|
||||
: DAG.getConstant(cast<ConstantSDNode>(N1)->getValue(), MVT::i16));
|
||||
return DAG.getNode(ISD::TRUNCATE, MVT::i8,
|
||||
return DAG.getNode(ISD::TRUNCATE, MVT::i8,
|
||||
DAG.getNode(Opc, MVT::i16, N0, N1));
|
||||
break;
|
||||
}
|
||||
@ -2551,7 +2552,7 @@ static SDOperand LowerCTPOP(SDOperand Op, SelectionDAG &DAG) {
|
||||
// CNTB_reg, SUM1_reg become associated:
|
||||
SDOperand CNTB_result =
|
||||
DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, CNTB, Elt0);
|
||||
|
||||
|
||||
SDOperand CNTB_rescopy =
|
||||
DAG.getCopyToReg(CNTB_result, CNTB_reg, CNTB_result);
|
||||
|
||||
@ -2585,7 +2586,7 @@ static SDOperand LowerCTPOP(SDOperand Op, SelectionDAG &DAG) {
|
||||
// CNTB_reg, SUM1_reg become associated:
|
||||
SDOperand CNTB_result =
|
||||
DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32, CNTB, Elt0);
|
||||
|
||||
|
||||
SDOperand CNTB_rescopy =
|
||||
DAG.getCopyToReg(CNTB_result, CNTB_reg, CNTB_result);
|
||||
|
||||
@ -2862,7 +2863,7 @@ SPUTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const
|
||||
// <arg>
|
||||
Result = Op0.getOperand(0);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
@ -2887,7 +2888,7 @@ SPUTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const
|
||||
|
||||
/// getConstraintType - Given a constraint letter, return the type of
|
||||
/// constraint it is for this target.
|
||||
SPUTargetLowering::ConstraintType
|
||||
SPUTargetLowering::ConstraintType
|
||||
SPUTargetLowering::getConstraintType(const std::string &ConstraintLetter) const {
|
||||
if (ConstraintLetter.size() == 1) {
|
||||
switch (ConstraintLetter[0]) {
|
||||
@ -2898,12 +2899,12 @@ SPUTargetLowering::getConstraintType(const std::string &ConstraintLetter) const
|
||||
case 'v':
|
||||
case 'y':
|
||||
return C_RegisterClass;
|
||||
}
|
||||
}
|
||||
}
|
||||
return TargetLowering::getConstraintType(ConstraintLetter);
|
||||
}
|
||||
|
||||
std::pair<unsigned, const TargetRegisterClass*>
|
||||
std::pair<unsigned, const TargetRegisterClass*>
|
||||
SPUTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
|
||||
MVT VT) const
|
||||
{
|
||||
@ -2921,11 +2922,11 @@ SPUTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
|
||||
else if (VT == MVT::f64)
|
||||
return std::make_pair(0U, SPU::R64FPRegisterClass);
|
||||
break;
|
||||
case 'v':
|
||||
case 'v':
|
||||
return std::make_pair(0U, SPU::GPRCRegisterClass);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
|
||||
}
|
||||
|
||||
@ -2933,7 +2934,7 @@ SPUTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
|
||||
void
|
||||
SPUTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
|
||||
const APInt &Mask,
|
||||
APInt &KnownZero,
|
||||
APInt &KnownZero,
|
||||
APInt &KnownOne,
|
||||
const SelectionDAG &DAG,
|
||||
unsigned Depth ) const {
|
||||
@ -2962,7 +2963,7 @@ SPUTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
|
||||
KnownOne |= APInt(Op0VTBits, InMask, false);
|
||||
break;
|
||||
}
|
||||
|
||||
|
||||
case SPUISD::LDRESULT:
|
||||
case SPUISD::EXTRACT_ELT0:
|
||||
case SPUISD::EXTRACT_ELT0_CHAINED: {
|
||||
@ -3022,5 +3023,5 @@ bool SPUTargetLowering::isLegalAddressImmediate(int64_t V, const Type *Ty) const
|
||||
}
|
||||
|
||||
bool SPUTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const {
|
||||
return false;
|
||||
return false;
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user