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[AArch64][SVE] Emit DWARF location expression for SVE stack objects.
Extend PEI to emit a DWARF expression for StackOffsets that have a fixed and scalable component. This means the expression that needs to be added is either: <base> + offset or: <base> + offset + scalable_offset * scalereg where for SVE, the scale reg is the Vector Granule Dwarf register, which encodes the number of 64bit 'granules' in an SVE vector and which the debugger can evaluate at runtime. Reviewed By: jmorse Differential Revision: https://reviews.llvm.org/D90020
This commit is contained in:
Sander de Smalen
parent
9a270624d8
commit
ba42c87c0b
@ -34,6 +34,7 @@
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namespace llvm {
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class BitVector;
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class DIExpression;
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class LiveRegMatrix;
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class MachineFunction;
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class MachineInstr;
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@ -923,6 +924,15 @@ public:
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llvm_unreachable("isFrameOffsetLegal does not exist on this target");
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}
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/// Gets the DWARF expression opcodes for \p Offset.
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virtual void getOffsetOpcodes(const StackOffset &Offset,
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SmallVectorImpl<uint64_t> &Ops) const;
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/// Prepends a DWARF expression for \p Offset to DIExpression \p Expr.
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DIExpression *
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prependOffsetExpression(const DIExpression *Expr, unsigned PrependFlags,
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const StackOffset &Offset) const;
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/// Spill the register so it can be used by the register scavenger.
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/// Return true if the register was spilled, false otherwise.
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/// If this function does not spill the register, the scavenger
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@ -1211,8 +1211,6 @@ void PEI::replaceFrameIndices(MachineBasicBlock *BB, MachineFunction &MF,
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StackOffset Offset =
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TFI->getFrameIndexReference(MF, FrameIdx, Reg);
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assert(!Offset.getScalable() &&
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"Frame offsets with a scalable component are not supported");
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MI.getOperand(0).ChangeToRegister(Reg, false /*isDef*/);
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MI.getOperand(0).setIsDebug();
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@ -1238,7 +1236,8 @@ void PEI::replaceFrameIndices(MachineBasicBlock *BB, MachineFunction &MF,
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// Make the DBG_VALUE direct.
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MI.getDebugOffset().ChangeToRegister(0, false);
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}
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DIExpr = DIExpression::prepend(DIExpr, PrependFlags, Offset.getFixed());
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DIExpr = TRI.prependOffsetExpression(DIExpr, PrependFlags, Offset);
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MI.getDebugExpressionOp().setMetadata(DIExpr);
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continue;
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}
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@ -26,6 +26,7 @@
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#include "llvm/CodeGen/VirtRegMap.h"
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#include "llvm/Config/llvm-config.h"
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#include "llvm/IR/Attributes.h"
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#include "llvm/IR/DebugInfoMetadata.h"
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#include "llvm/IR/Function.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/Support/CommandLine.h"
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@ -532,6 +533,31 @@ TargetRegisterInfo::lookThruCopyLike(Register SrcReg,
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}
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}
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void TargetRegisterInfo::getOffsetOpcodes(
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const StackOffset &Offset, SmallVectorImpl<uint64_t> &Ops) const {
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assert(!Offset.getScalable() && "Scalable offsets are not handled");
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DIExpression::appendOffset(Ops, Offset.getFixed());
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}
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DIExpression *
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TargetRegisterInfo::prependOffsetExpression(const DIExpression *Expr,
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unsigned PrependFlags,
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const StackOffset &Offset) const {
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assert((PrependFlags &
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~(DIExpression::DerefBefore | DIExpression::DerefAfter |
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DIExpression::StackValue | DIExpression::EntryValue)) == 0 &&
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"Unsupported prepend flag");
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SmallVector<uint64_t, 16> OffsetExpr;
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if (PrependFlags & DIExpression::DerefBefore)
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OffsetExpr.push_back(dwarf::DW_OP_deref);
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getOffsetOpcodes(Offset, OffsetExpr);
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if (PrependFlags & DIExpression::DerefAfter)
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OffsetExpr.push_back(dwarf::DW_OP_deref);
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return DIExpression::prependOpcodes(Expr, OffsetExpr,
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PrependFlags & DIExpression::StackValue,
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PrependFlags & DIExpression::EntryValue);
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}
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#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
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LLVM_DUMP_METHOD
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void TargetRegisterInfo::dumpReg(Register Reg, unsigned SubRegIndex,
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@ -24,6 +24,7 @@
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/CodeGen/TargetFrameLowering.h"
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#include "llvm/IR/DebugInfoMetadata.h"
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#include "llvm/IR/DiagnosticInfo.h"
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#include "llvm/IR/Function.h"
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#include "llvm/Support/raw_ostream.h"
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@ -592,6 +593,33 @@ createScratchRegisterForInstruction(MachineInstr &MI,
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}
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}
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void AArch64RegisterInfo::getOffsetOpcodes(
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const StackOffset &Offset, SmallVectorImpl<uint64_t> &Ops) const {
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// The smallest scalable element supported by scaled SVE addressing
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// modes are predicates, which are 2 scalable bytes in size. So the scalable
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// byte offset must always be a multiple of 2.
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assert(Offset.getScalable() % 2 == 0 && "Invalid frame offset");
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// Add fixed-sized offset using existing DIExpression interface.
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DIExpression::appendOffset(Ops, Offset.getFixed());
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unsigned VG = getDwarfRegNum(AArch64::VG, true);
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int64_t VGSized = Offset.getScalable() / 2;
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if (VGSized > 0) {
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Ops.push_back(dwarf::DW_OP_constu);
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Ops.push_back(VGSized);
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Ops.append({dwarf::DW_OP_bregx, VG, 0ULL});
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Ops.push_back(dwarf::DW_OP_mul);
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Ops.push_back(dwarf::DW_OP_plus);
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} else if (VGSized < 0) {
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Ops.push_back(dwarf::DW_OP_constu);
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Ops.push_back(-VGSized);
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Ops.append({dwarf::DW_OP_bregx, VG, 0ULL});
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Ops.push_back(dwarf::DW_OP_mul);
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Ops.push_back(dwarf::DW_OP_minus);
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}
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}
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void AArch64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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int SPAdj, unsigned FIOperandNum,
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RegScavenger *RS) const {
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@ -610,7 +638,7 @@ void AArch64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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Register FrameReg;
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// Special handling of dbg_value, stackmap patchpoint statepoint instructions.
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if (MI.isDebugValue() || MI.getOpcode() == TargetOpcode::STACKMAP ||
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if (MI.getOpcode() == TargetOpcode::STACKMAP ||
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MI.getOpcode() == TargetOpcode::PATCHPOINT ||
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MI.getOpcode() == TargetOpcode::STATEPOINT) {
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StackOffset Offset =
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@ -135,6 +135,9 @@ public:
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unsigned SubReg, const TargetRegisterClass *DstRC,
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unsigned DstSubReg, const TargetRegisterClass *NewRC,
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LiveIntervals &LIS) const override;
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void getOffsetOpcodes(const StackOffset &Offset,
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SmallVectorImpl<uint64_t> &Ops) const override;
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};
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} // end namespace llvm
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126
test/CodeGen/AArch64/debug-info-sve-dbg-value.mir
Normal file
126
test/CodeGen/AArch64/debug-info-sve-dbg-value.mir
Normal file
@ -0,0 +1,126 @@
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# RUN: llc -o %t -filetype=obj -start-before=prologepilog %s
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# RUN: llvm-dwarfdump --name="value0" %t | FileCheck %s --check-prefix=CHECK0
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# RUN: llvm-dwarfdump --name="value1" %t | FileCheck %s --check-prefix=CHECK1
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# RUN: llvm-dwarfdump --name="value2" %t | FileCheck %s --check-prefix=CHECK2
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# RUN: llvm-dwarfdump --name="value3" %t | FileCheck %s --check-prefix=CHECK3
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# RUN: llvm-dwarfdump --name="value4" %t | FileCheck %s --check-prefix=CHECK4
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# RUN: llvm-dwarfdump --name="value5" %t | FileCheck %s --check-prefix=CHECK5
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# CHECK0: : DW_OP_breg31 WSP+8, DW_OP_lit16, DW_OP_plus)
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# CHECK0: DW_AT_type {{.*}}ty32
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#
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# CHECK1: : DW_OP_breg31 WSP+16)
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# CHECK1: DW_AT_type {{.*}}ty32
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#
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# CHECK2: : DW_OP_breg31 WSP+16, DW_OP_lit16, DW_OP_bregx VG+0, DW_OP_mul, DW_OP_plus)
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# CHECK2: DW_AT_type {{.*}}svint32_t
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#
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# CHECK3: : DW_OP_breg31 WSP+16, DW_OP_lit8, DW_OP_bregx VG+0, DW_OP_mul, DW_OP_plus)
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# CHECK3: DW_AT_type {{.*}}svint32_t
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#
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# CHECK4: : DW_OP_breg31 WSP+16, DW_OP_lit7, DW_OP_bregx VG+0, DW_OP_mul, DW_OP_plus)
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# CHECK4: DW_AT_type {{.*}}svbool_t
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#
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# CHECK5: : DW_OP_breg31 WSP+16, DW_OP_lit6, DW_OP_bregx VG+0, DW_OP_mul, DW_OP_plus)
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# CHECK5: DW_AT_type {{.*}}svbool_t
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--- |
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; ModuleID = 'bla.mir'
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source_filename = "bla.mir"
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target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
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define void @foo() #0 !dbg !5 {
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entry:
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unreachable, !dbg !8
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}
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; Function Attrs: nounwind readnone speculatable willreturn
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declare void @llvm.dbg.value(metadata, metadata, metadata)
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attributes #0 = { "target-features"="+sve" }
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!llvm.dbg.cu = !{!0}
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!llvm.debugify = !{!3, !3}
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!llvm.module.flags = !{!4}
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!0 = distinct !DICompileUnit(language: DW_LANG_C, file: !1, producer: "debugify", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2)
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!1 = !DIFile(filename: "bla.mir", directory: "/")
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!2 = !{}
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!3 = !{i32 1}
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!4 = !{i32 2, !"Debug Info Version", i32 3}
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!5 = distinct !DISubprogram(name: "foo", linkageName: "foo", scope: null, file: !1, line: 1, type: !6, scopeLine: 1, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !9)
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!6 = !DISubroutineType(types: !2)
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!7 = !DIBasicType(name: "ty32", size: 32, encoding: DW_ATE_signed)
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!8 = !DILocation(line: 1, column: 1, scope: !5)
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!9 = !{!10, !11, !12, !13, !14, !15}
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!10 = !DILocalVariable(name: "value0", scope: !5, file: !1, line: 1, type: !7)
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!11 = !DILocalVariable(name: "value1", scope: !5, file: !1, line: 1, type: !7)
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!12 = !DILocalVariable(name: "value2", scope: !5, file: !1, line: 1, type: !16)
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!13 = !DILocalVariable(name: "value3", scope: !5, file: !1, line: 1, type: !16)
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!14 = !DILocalVariable(name: "value4", scope: !5, file: !1, line: 1, type: !21)
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!15 = !DILocalVariable(name: "value5", scope: !5, file: !1, line: 1, type: !21)
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!16 = !DIDerivedType(tag: DW_TAG_typedef, name: "svint32_t", file: !1, line: 1, baseType: !17)
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!17 = !DIDerivedType(tag: DW_TAG_typedef, name: "__SVInt32_t", file: !1, baseType: !18)
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!18 = !DICompositeType(tag: DW_TAG_array_type, baseType: !7, flags: DIFlagVector, elements: !19)
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!19 = !{!20}
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!20 = !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_constu, 2, DW_OP_bregx, 46, 0, DW_OP_mul, DW_OP_constu, 1, DW_OP_minus))
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!21 = !DIDerivedType(tag: DW_TAG_typedef, name: "svbool_t", file: !1, line: 90, baseType: !22)
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!22 = !DIDerivedType(tag: DW_TAG_typedef, name: "__SVBool_t", file: !1, baseType: !23)
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!23 = !DICompositeType(tag: DW_TAG_array_type, baseType: !24, flags: DIFlagVector, elements: !25)
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!24 = !DIBasicType(name: "unsigned char", size: 8, encoding: DW_ATE_unsigned_char)
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!25 = !{!26}
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!26 = !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_constu, 1, DW_OP_bregx, 46, 0, DW_OP_mul, DW_OP_constu, 1, DW_OP_minus))
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...
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---
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name: foo
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alignment: 4
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tracksRegLiveness: true
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liveins:
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- { reg: '$z0' }
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- { reg: '$z1' }
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- { reg: '$p0' }
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- { reg: '$p1' }
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- { reg: '$x0' }
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- { reg: '$x1' }
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frameInfo:
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maxAlignment: 16
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adjustsStack: true
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hasCalls: true
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maxCallFrameSize: 0
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localFrameSize: 4
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stack:
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- { id: 0, size: 8, alignment: 8 }
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- { id: 1, size: 8, alignment: 8 }
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- { id: 2, size: 16, alignment: 16, stack-id: sve-vec }
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- { id: 3, size: 16, alignment: 16, stack-id: sve-vec }
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- { id: 4, size: 2, alignment: 2, stack-id: sve-vec }
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- { id: 5, size: 2, alignment: 2, stack-id: sve-vec }
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machineFunctionInfo: {}
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body: |
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bb.0.entry:
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liveins: $p0, $p1, $w0, $x1, $z0, $z1
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; Avoid stack slot scavenging.
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$lr = IMPLICIT_DEF
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STRXui killed renamable $x0, %stack.0, 0, debug-location !8
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DBG_VALUE %stack.0, $noreg, !10, !DIExpression(DW_OP_constu, 16, DW_OP_plus, DW_OP_deref), debug-location !8
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STRXui killed renamable $x1, %stack.1, 0, debug-location !8
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DBG_VALUE %stack.1, $noreg, !11, !DIExpression(DW_OP_constu, 16, DW_OP_plus, DW_OP_deref), debug-location !8
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renamable $p2 = PTRUE_S 31, debug-location !DILocation(line: 4, column: 1, scope: !5)
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ST1W_IMM renamable $z0, renamable $p2, %stack.2, 0, debug-location !DILocation(line: 5, column: 1, scope: !5)
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DBG_VALUE %stack.2, $noreg, !12, !DIExpression(DW_OP_deref), debug-location !DILocation(line: 5, column: 1, scope: !5)
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ST1W_IMM renamable $z1, killed renamable $p2, %stack.3, 0, debug-location !DILocation(line: 6, column: 1, scope: !5)
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DBG_VALUE %stack.3, $noreg, !13, !DIExpression(DW_OP_deref), debug-location !DILocation(line: 6, column: 1, scope: !5)
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STR_PXI killed renamable $p0, %stack.4, 0, debug-location !DILocation(line: 2, column: 1, scope: !5)
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DBG_VALUE %stack.4, $noreg, !14, !DIExpression(DW_OP_deref), debug-location !DILocation(line: 2, column: 1, scope: !5)
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STR_PXI killed renamable $p1, %stack.5, 0, debug-location !DILocation(line: 3, column: 1, scope: !5)
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DBG_VALUE %stack.5, $noreg, !15, !DIExpression(DW_OP_deref), debug-location !DILocation(line: 3, column: 1, scope: !5)
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RET_ReallyLR implicit $z0, implicit $z1, debug-location !DILocation(line: 7, column: 1, scope: !5)
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...
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