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[PowerPC][NFC] Sorting out Pseudo related classes to avoid confusion

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There are several Pseudo in PowerPC backend. 
eg:

* ISel Pseudo-instructions , which has let usesCustomInserter=1 in td 
ExpandISelPseudos -> EmitInstrWithCustomInserter will deal with them.
* Post-RA pseudo instruction, which has let isPseudo = 1 in td, or Standard pseudo (SUBREG_TO_REG,COPY etc.) 
ExpandPostRAPseudos -> expandPostRAPseudo will expand them
* Multi-instruction pseudo operations will expand them PPCAsmPrinter::EmitInstruction
* Pseudo instruction in CodeEmitter, which has encoding of 0.

Currently, in td files, especially PPCInstrVSX.td, 
we did not distinguish Post-RA pseudo instruction and Pseudo instruction in CodeEmitter very clearly.

This patch is to

* Rename Pseudo<> class to PPCEmitTimePseudo, which means encoding of 0 in CodeEmitter
* Introduce new class PPCPostRAExpPseudo <> for previous PostRA Pseudo
* Introduce new class PPCCustomInserterPseudo <> for previous Isel Pseudo

Differential Revision: https://reviews.llvm.org/D55143

llvm-svn: 349044
This commit is contained in:
Jinsong Ji 2018-12-13 15:12:57 +00:00
parent d7ebd4dbc1
commit ba49832db6
7 changed files with 341 additions and 347 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

138
lib/Target/PowerPC/PPCInstr64Bit.td
View File

@ -94,7 +94,7 @@ let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
} }
let Defs = [LR8] in let Defs = [LR8] in
def MovePCtoLR8 : Pseudo<(outs), (ins), "#MovePCtoLR8", []>, def MovePCtoLR8 : PPCEmitTimePseudo<(outs), (ins), "#MovePCtoLR8", []>,
PPC970_Unit_BRU; PPC970_Unit_BRU;
let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in { let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
@ -199,47 +199,45 @@ def : Pat<(PPCcall_nop (i64 texternalsym:$dst)),
// clean this up in PPCMIPeephole with calls to // clean this up in PPCMIPeephole with calls to
// PPCInstrInfo::convertToImmediateForm() but we should probably not emit them // PPCInstrInfo::convertToImmediateForm() but we should probably not emit them
// in the first place. // in the first place.
let usesCustomInserter = 1 in { let Defs = [CR0] in {
let Defs = [CR0] in { def ATOMIC_LOAD_ADD_I64 : PPCCustomInserterPseudo<
def ATOMIC_LOAD_ADD_I64 : Pseudo< (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_ADD_I64",
(outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_ADD_I64", [(set i64:$dst, (atomic_load_add_64 xoaddr:$ptr, i64:$incr))]>;
[(set i64:$dst, (atomic_load_add_64 xoaddr:$ptr, i64:$incr))]>; def ATOMIC_LOAD_SUB_I64 : PPCCustomInserterPseudo<
def ATOMIC_LOAD_SUB_I64 : Pseudo< (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_SUB_I64",
(outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_SUB_I64", [(set i64:$dst, (atomic_load_sub_64 xoaddr:$ptr, i64:$incr))]>;
[(set i64:$dst, (atomic_load_sub_64 xoaddr:$ptr, i64:$incr))]>; def ATOMIC_LOAD_OR_I64 : PPCCustomInserterPseudo<
def ATOMIC_LOAD_OR_I64 : Pseudo< (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_OR_I64",
(outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_OR_I64", [(set i64:$dst, (atomic_load_or_64 xoaddr:$ptr, i64:$incr))]>;
[(set i64:$dst, (atomic_load_or_64 xoaddr:$ptr, i64:$incr))]>; def ATOMIC_LOAD_XOR_I64 : PPCCustomInserterPseudo<
def ATOMIC_LOAD_XOR_I64 : Pseudo< (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_XOR_I64",
(outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_XOR_I64", [(set i64:$dst, (atomic_load_xor_64 xoaddr:$ptr, i64:$incr))]>;
[(set i64:$dst, (atomic_load_xor_64 xoaddr:$ptr, i64:$incr))]>; def ATOMIC_LOAD_AND_I64 : PPCCustomInserterPseudo<
def ATOMIC_LOAD_AND_I64 : Pseudo< (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_AND_i64",
(outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_AND_i64", [(set i64:$dst, (atomic_load_and_64 xoaddr:$ptr, i64:$incr))]>;
[(set i64:$dst, (atomic_load_and_64 xoaddr:$ptr, i64:$incr))]>; def ATOMIC_LOAD_NAND_I64 : PPCCustomInserterPseudo<
def ATOMIC_LOAD_NAND_I64 : Pseudo< (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_NAND_I64",
(outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_NAND_I64", [(set i64:$dst, (atomic_load_nand_64 xoaddr:$ptr, i64:$incr))]>;
[(set i64:$dst, (atomic_load_nand_64 xoaddr:$ptr, i64:$incr))]>; def ATOMIC_LOAD_MIN_I64 : PPCCustomInserterPseudo<
def ATOMIC_LOAD_MIN_I64 : Pseudo< (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_MIN_I64",
(outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_MIN_I64", [(set i64:$dst, (atomic_load_min_64 xoaddr:$ptr, i64:$incr))]>;
[(set i64:$dst, (atomic_load_min_64 xoaddr:$ptr, i64:$incr))]>; def ATOMIC_LOAD_MAX_I64 : PPCCustomInserterPseudo<
def ATOMIC_LOAD_MAX_I64 : Pseudo< (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_MAX_I64",
(outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_MAX_I64", [(set i64:$dst, (atomic_load_max_64 xoaddr:$ptr, i64:$incr))]>;
[(set i64:$dst, (atomic_load_max_64 xoaddr:$ptr, i64:$incr))]>; def ATOMIC_LOAD_UMIN_I64 : PPCCustomInserterPseudo<
def ATOMIC_LOAD_UMIN_I64 : Pseudo< (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_UMIN_I64",
(outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_UMIN_I64", [(set i64:$dst, (atomic_load_umin_64 xoaddr:$ptr, i64:$incr))]>;
[(set i64:$dst, (atomic_load_umin_64 xoaddr:$ptr, i64:$incr))]>; def ATOMIC_LOAD_UMAX_I64 : PPCCustomInserterPseudo<
def ATOMIC_LOAD_UMAX_I64 : Pseudo< (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_UMAX_I64",
(outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_UMAX_I64", [(set i64:$dst, (atomic_load_umax_64 xoaddr:$ptr, i64:$incr))]>;
[(set i64:$dst, (atomic_load_umax_64 xoaddr:$ptr, i64:$incr))]>;
def ATOMIC_CMP_SWAP_I64 : Pseudo< def ATOMIC_CMP_SWAP_I64 : PPCCustomInserterPseudo<
(outs g8rc:$dst), (ins memrr:$ptr, g8rc:$old, g8rc:$new), "#ATOMIC_CMP_SWAP_I64", (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$old, g8rc:$new), "#ATOMIC_CMP_SWAP_I64",
[(set i64:$dst, (atomic_cmp_swap_64 xoaddr:$ptr, i64:$old, i64:$new))]>; [(set i64:$dst, (atomic_cmp_swap_64 xoaddr:$ptr, i64:$old, i64:$new))]>;
def ATOMIC_SWAP_I64 : Pseudo< def ATOMIC_SWAP_I64 : PPCCustomInserterPseudo<
(outs g8rc:$dst), (ins memrr:$ptr, g8rc:$new), "#ATOMIC_SWAP_I64", (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$new), "#ATOMIC_SWAP_I64",
[(set i64:$dst, (atomic_swap_64 xoaddr:$ptr, i64:$new))]>; [(set i64:$dst, (atomic_swap_64 xoaddr:$ptr, i64:$new))]>;
}
} }
// Instructions to support atomic operations // Instructions to support atomic operations
@ -269,18 +267,18 @@ def STDAT : X_RD5_RS5_IM5<31, 742, (outs), (ins g8rc:$rS, g8rc:$rA, u5imm:$FC),
let Interpretation64Bit = 1, isCodeGenOnly = 1 in { let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
def TCRETURNdi8 :Pseudo< (outs), def TCRETURNdi8 :PPCEmitTimePseudo< (outs),
(ins calltarget:$dst, i32imm:$offset), (ins calltarget:$dst, i32imm:$offset),
"#TC_RETURNd8 $dst $offset", "#TC_RETURNd8 $dst $offset",
[]>; []>;
let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
def TCRETURNai8 :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset), def TCRETURNai8 :PPCEmitTimePseudo<(outs), (ins abscalltarget:$func, i32imm:$offset),
"#TC_RETURNa8 $func $offset", "#TC_RETURNa8 $func $offset",
[(PPCtc_return (i64 imm:$func), imm:$offset)]>; [(PPCtc_return (i64 imm:$func), imm:$offset)]>;
let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset), def TCRETURNri8 : PPCEmitTimePseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset),
"#TC_RETURNr8 $dst $offset", "#TC_RETURNr8 $dst $offset",
[]>; []>;
@ -349,17 +347,17 @@ def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$rT), (ins),
// While longjmp is a control-flow barrier (fallthrough isn't allowed), setjmp // While longjmp is a control-flow barrier (fallthrough isn't allowed), setjmp
// is not. // is not.
let hasSideEffects = 1, usesCustomInserter = 1 in { let hasSideEffects = 1 in {
let Defs = [CTR8] in let Defs = [CTR8] in
def EH_SjLj_SetJmp64 : Pseudo<(outs gprc:$dst), (ins memr:$buf), def EH_SjLj_SetJmp64 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins memr:$buf),
"#EH_SJLJ_SETJMP64", "#EH_SJLJ_SETJMP64",
[(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>, [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
Requires<[In64BitMode]>; Requires<[In64BitMode]>;
} }
let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in { let hasSideEffects = 1, isBarrier = 1 in {
let isTerminator = 1 in let isTerminator = 1 in
def EH_SjLj_LongJmp64 : Pseudo<(outs), (ins memr:$buf), def EH_SjLj_LongJmp64 : PPCCustomInserterPseudo<(outs), (ins memr:$buf),
"#EH_SJLJ_LONGJMP64", "#EH_SJLJ_LONGJMP64",
[(PPCeh_sjlj_longjmp addr:$buf)]>, [(PPCeh_sjlj_longjmp addr:$buf)]>,
Requires<[In64BitMode]>; Requires<[In64BitMode]>;
@ -401,10 +399,10 @@ def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$rT), (ins),
// the POWER3. // the POWER3.
let Defs = [X1], Uses = [X1] in let Defs = [X1], Uses = [X1] in
def DYNALLOC8 : Pseudo<(outs g8rc:$result), (ins g8rc:$negsize, memri:$fpsi),"#DYNALLOC8", def DYNALLOC8 : PPCEmitTimePseudo<(outs g8rc:$result), (ins g8rc:$negsize, memri:$fpsi),"#DYNALLOC8",
[(set i64:$result, [(set i64:$result,
(PPCdynalloc i64:$negsize, iaddr:$fpsi))]>; (PPCdynalloc i64:$negsize, iaddr:$fpsi))]>;
def DYNAREAOFFSET8 : Pseudo<(outs i64imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET8", def DYNAREAOFFSET8 : PPCEmitTimePseudo<(outs i64imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET8",
[(set i64:$result, (PPCdynareaoffset iaddr:$fpsi))]>; [(set i64:$result, (PPCdynareaoffset iaddr:$fpsi))]>;
let Defs = [LR8] in { let Defs = [LR8] in {
@ -1024,19 +1022,19 @@ def LD : DSForm_1<58, 0, (outs g8rc:$rD), (ins memrix:$src),
// The following four definitions are selected for small code model only. // The following four definitions are selected for small code model only.
// Otherwise, we need to create two instructions to form a 32-bit offset, // Otherwise, we need to create two instructions to form a 32-bit offset,
// so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select(). // so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select().
def LDtoc: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), def LDtoc: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
"#LDtoc", "#LDtoc",
[(set i64:$rD, [(set i64:$rD,
(PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64; (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64;
def LDtocJTI: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), def LDtocJTI: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
"#LDtocJTI", "#LDtocJTI",
[(set i64:$rD, [(set i64:$rD,
(PPCtoc_entry tjumptable:$disp, i64:$reg))]>, isPPC64; (PPCtoc_entry tjumptable:$disp, i64:$reg))]>, isPPC64;
def LDtocCPT: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), def LDtocCPT: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
"#LDtocCPT", "#LDtocCPT",
[(set i64:$rD, [(set i64:$rD,
(PPCtoc_entry tconstpool:$disp, i64:$reg))]>, isPPC64; (PPCtoc_entry tconstpool:$disp, i64:$reg))]>, isPPC64;
def LDtocBA: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), def LDtocBA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
"#LDtocCPT", "#LDtocCPT",
[(set i64:$rD, [(set i64:$rD,
(PPCtoc_entry tblockaddress:$disp, i64:$reg))]>, isPPC64; (PPCtoc_entry tblockaddress:$disp, i64:$reg))]>, isPPC64;
@ -1077,40 +1075,40 @@ def LDMX : XForm_1<31, 309, (outs g8rc:$rD), (ins memrr:$src),
// Support for medium and large code model. // Support for medium and large code model.
let hasSideEffects = 0 in { let hasSideEffects = 0 in {
let isReMaterializable = 1 in { let isReMaterializable = 1 in {
def ADDIStocHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), def ADDIStocHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp),
"#ADDIStocHA", []>, isPPC64; "#ADDIStocHA", []>, isPPC64;
def ADDItocL: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), def ADDItocL: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp),
"#ADDItocL", []>, isPPC64; "#ADDItocL", []>, isPPC64;
} }
let mayLoad = 1 in let mayLoad = 1 in
def LDtocL: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg), def LDtocL: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg),
"#LDtocL", []>, isPPC64; "#LDtocL", []>, isPPC64;
} }
// Support for thread-local storage. // Support for thread-local storage.
def ADDISgotTprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), def ADDISgotTprelHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
"#ADDISgotTprelHA", "#ADDISgotTprelHA",
[(set i64:$rD, [(set i64:$rD,
(PPCaddisGotTprelHA i64:$reg, (PPCaddisGotTprelHA i64:$reg,
tglobaltlsaddr:$disp))]>, tglobaltlsaddr:$disp))]>,
isPPC64; isPPC64;
def LDgotTprelL: Pseudo<(outs g8rc:$rD), (ins s16imm64:$disp, g8rc_nox0:$reg), def LDgotTprelL: PPCEmitTimePseudo<(outs g8rc:$rD), (ins s16imm64:$disp, g8rc_nox0:$reg),
"#LDgotTprelL", "#LDgotTprelL",
[(set i64:$rD, [(set i64:$rD,
(PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>, (PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>,
isPPC64; isPPC64;
let isPseudo = 1, Defs = [CR7], Itinerary = IIC_LdStSync in let Defs = [CR7], Itinerary = IIC_LdStSync in
def CFENCE8 : Pseudo<(outs), (ins g8rc:$cr), "#CFENCE8", []>; def CFENCE8 : PPCPostRAExpPseudo<(outs), (ins g8rc:$cr), "#CFENCE8", []>;
def : Pat<(PPCaddTls i64:$in, tglobaltlsaddr:$g), def : Pat<(PPCaddTls i64:$in, tglobaltlsaddr:$g),
(ADD8TLS $in, tglobaltlsaddr:$g)>; (ADD8TLS $in, tglobaltlsaddr:$g)>;
def ADDIStlsgdHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), def ADDIStlsgdHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
"#ADDIStlsgdHA", "#ADDIStlsgdHA",
[(set i64:$rD, [(set i64:$rD,
(PPCaddisTlsgdHA i64:$reg, tglobaltlsaddr:$disp))]>, (PPCaddisTlsgdHA i64:$reg, tglobaltlsaddr:$disp))]>,
isPPC64; isPPC64;
def ADDItlsgdL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), def ADDItlsgdL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
"#ADDItlsgdL", "#ADDItlsgdL",
[(set i64:$rD, [(set i64:$rD,
(PPCaddiTlsgdL i64:$reg, tglobaltlsaddr:$disp))]>, (PPCaddiTlsgdL i64:$reg, tglobaltlsaddr:$disp))]>,
@ -1121,7 +1119,7 @@ def ADDItlsgdL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
// correct because the branch select pass is relying on it. // correct because the branch select pass is relying on it.
let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, Size = 8, let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, Size = 8,
Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in
def GETtlsADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), def GETtlsADDR : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym),
"#GETtlsADDR", "#GETtlsADDR",
[(set i64:$rD, [(set i64:$rD,
(PPCgetTlsAddr i64:$reg, tglobaltlsaddr:$sym))]>, (PPCgetTlsAddr i64:$reg, tglobaltlsaddr:$sym))]>,
@ -1131,7 +1129,7 @@ def GETtlsADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym),
let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7]
in in
def ADDItlsgdLADDR : Pseudo<(outs g8rc:$rD), def ADDItlsgdLADDR : PPCEmitTimePseudo<(outs g8rc:$rD),
(ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym), (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym),
"#ADDItlsgdLADDR", "#ADDItlsgdLADDR",
[(set i64:$rD, [(set i64:$rD,
@ -1139,12 +1137,12 @@ def ADDItlsgdLADDR : Pseudo<(outs g8rc:$rD),
tglobaltlsaddr:$disp, tglobaltlsaddr:$disp,
tglobaltlsaddr:$sym))]>, tglobaltlsaddr:$sym))]>,
isPPC64; isPPC64;
def ADDIStlsldHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), def ADDIStlsldHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
"#ADDIStlsldHA", "#ADDIStlsldHA",
[(set i64:$rD, [(set i64:$rD,
(PPCaddisTlsldHA i64:$reg, tglobaltlsaddr:$disp))]>, (PPCaddisTlsldHA i64:$reg, tglobaltlsaddr:$disp))]>,
isPPC64; isPPC64;
def ADDItlsldL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), def ADDItlsldL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
"#ADDItlsldL", "#ADDItlsldL",
[(set i64:$rD, [(set i64:$rD,
(PPCaddiTlsldL i64:$reg, tglobaltlsaddr:$disp))]>, (PPCaddiTlsldL i64:$reg, tglobaltlsaddr:$disp))]>,
@ -1153,7 +1151,7 @@ def ADDItlsldL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
// explicitly defined when this op is created, so not mentioned here. // explicitly defined when this op is created, so not mentioned here.
let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in
def GETtlsldADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), def GETtlsldADDR : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym),
"#GETtlsldADDR", "#GETtlsldADDR",
[(set i64:$rD, [(set i64:$rD,
(PPCgetTlsldAddr i64:$reg, tglobaltlsaddr:$sym))]>, (PPCgetTlsldAddr i64:$reg, tglobaltlsaddr:$sym))]>,
@ -1163,7 +1161,7 @@ def GETtlsldADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym),
let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7]
in in
def ADDItlsldLADDR : Pseudo<(outs g8rc:$rD), def ADDItlsldLADDR : PPCEmitTimePseudo<(outs g8rc:$rD),
(ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym), (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym),
"#ADDItlsldLADDR", "#ADDItlsldLADDR",
[(set i64:$rD, [(set i64:$rD,
@ -1171,13 +1169,13 @@ def ADDItlsldLADDR : Pseudo<(outs g8rc:$rD),
tglobaltlsaddr:$disp, tglobaltlsaddr:$disp,
tglobaltlsaddr:$sym))]>, tglobaltlsaddr:$sym))]>,
isPPC64; isPPC64;
def ADDISdtprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), def ADDISdtprelHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
"#ADDISdtprelHA", "#ADDISdtprelHA",
[(set i64:$rD, [(set i64:$rD,
(PPCaddisDtprelHA i64:$reg, (PPCaddisDtprelHA i64:$reg,
tglobaltlsaddr:$disp))]>, tglobaltlsaddr:$disp))]>,
isPPC64; isPPC64;
def ADDIdtprelL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), def ADDIdtprelL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
"#ADDIdtprelL", "#ADDIdtprelL",
[(set i64:$rD, [(set i64:$rD,
(PPCaddiDtprelL i64:$reg, tglobaltlsaddr:$disp))]>, (PPCaddiDtprelL i64:$reg, tglobaltlsaddr:$disp))]>,

23
lib/Target/PowerPC/PPCInstrFormats.td
View File

@ -2153,7 +2153,9 @@ class Z23Form_8<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class Pseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern> // EmitTimePseudo won't have encoding information for the [MC]CodeEmitter
// stuff
class PPCEmitTimePseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern>
: I<0, OOL, IOL, asmstr, NoItinerary> { : I<0, OOL, IOL, asmstr, NoItinerary> {
let isCodeGenOnly = 1; let isCodeGenOnly = 1;
let PPC64 = 0; let PPC64 = 0;
@ -2162,6 +2164,21 @@ class Pseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern>
let hasNoSchedulingInfo = 1; let hasNoSchedulingInfo = 1;
} }
class PseudoXFormMemOp<dag OOL, dag IOL, string asmstr, list<dag> pattern> // Instruction that require custom insertion support
: Pseudo<OOL, IOL, asmstr, pattern>, XFormMemOp; // a.k.a. ISelPseudos, however, these won't have isPseudo set
class PPCCustomInserterPseudo<dag OOL, dag IOL, string asmstr,
list<dag> pattern>
: PPCEmitTimePseudo<OOL, IOL, asmstr, pattern> {
let usesCustomInserter = 1;
}
// PostRAPseudo will be expanded in expandPostRAPseudo, isPseudo flag in td
// files is set only for PostRAPseudo
class PPCPostRAExpPseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern>
: PPCEmitTimePseudo<OOL, IOL, asmstr, pattern> {
let isPseudo = 1;
}
class PseudoXFormMemOp<dag OOL, dag IOL, string asmstr, list<dag> pattern>
: PPCPostRAExpPseudo<OOL, IOL, asmstr, pattern>, XFormMemOp;

4
lib/Target/PowerPC/PPCInstrHTM.td
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@ -20,8 +20,8 @@ def HTM_get_imm : SDNodeXForm<imm, [{
return getI32Imm (N->getZExtValue(), SDLoc(N)); return getI32Imm (N->getZExtValue(), SDLoc(N));
}]>; }]>;
let hasSideEffects = 1, usesCustomInserter = 1 in { let hasSideEffects = 1 in {
def TCHECK_RET : Pseudo<(outs crrc:$out), (ins), "#TCHECK_RET", []>; def TCHECK_RET : PPCCustomInserterPseudo<(outs crrc:$out), (ins), "#TCHECK_RET", []>;
} }

337
lib/Target/PowerPC/PPCInstrInfo.td
View File

@ -1195,77 +1195,76 @@ multiclass AForm_3r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// PowerPC Instruction Definitions. // PowerPC Instruction Definitions.
// Pseudo-instructions: // Pseudo instructions:
let hasCtrlDep = 1 in { let hasCtrlDep = 1 in {
let Defs = [R1], Uses = [R1] in { let Defs = [R1], Uses = [R1] in {
def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), def ADJCALLSTACKDOWN : PPCEmitTimePseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2),
"#ADJCALLSTACKDOWN $amt1 $amt2", "#ADJCALLSTACKDOWN $amt1 $amt2",
[(callseq_start timm:$amt1, timm:$amt2)]>; [(callseq_start timm:$amt1, timm:$amt2)]>;
def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), def ADJCALLSTACKUP : PPCEmitTimePseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2),
"#ADJCALLSTACKUP $amt1 $amt2", "#ADJCALLSTACKUP $amt1 $amt2",
[(callseq_end timm:$amt1, timm:$amt2)]>; [(callseq_end timm:$amt1, timm:$amt2)]>;
} }
def UPDATE_VRSAVE : Pseudo<(outs gprc:$rD), (ins gprc:$rS), def UPDATE_VRSAVE : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$rS),
"UPDATE_VRSAVE $rD, $rS", []>; "UPDATE_VRSAVE $rD, $rS", []>;
} }
let Defs = [R1], Uses = [R1] in let Defs = [R1], Uses = [R1] in
def DYNALLOC : Pseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC", def DYNALLOC : PPCEmitTimePseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC",
[(set i32:$result, [(set i32:$result,
(PPCdynalloc i32:$negsize, iaddr:$fpsi))]>; (PPCdynalloc i32:$negsize, iaddr:$fpsi))]>;
def DYNAREAOFFSET : Pseudo<(outs i32imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET", def DYNAREAOFFSET : PPCEmitTimePseudo<(outs i32imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET",
[(set i32:$result, (PPCdynareaoffset iaddr:$fpsi))]>; [(set i32:$result, (PPCdynareaoffset iaddr:$fpsi))]>;
// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
// instruction selection into a branch sequence. // instruction selection into a branch sequence.
let usesCustomInserter = 1, // Expanded after instruction selection. let PPC970_Single = 1 in {
PPC970_Single = 1 in {
// Note that SELECT_CC_I4 and SELECT_CC_I8 use the no-r0 register classes // Note that SELECT_CC_I4 and SELECT_CC_I8 use the no-r0 register classes
// because either operand might become the first operand in an isel, and // because either operand might become the first operand in an isel, and
// that operand cannot be r0. // that operand cannot be r0.
def SELECT_CC_I4 : Pseudo<(outs gprc:$dst), (ins crrc:$cond, def SELECT_CC_I4 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins crrc:$cond,
gprc_nor0:$T, gprc_nor0:$F, gprc_nor0:$T, gprc_nor0:$F,
i32imm:$BROPC), "#SELECT_CC_I4", i32imm:$BROPC), "#SELECT_CC_I4",
[]>; []>;
def SELECT_CC_I8 : Pseudo<(outs g8rc:$dst), (ins crrc:$cond, def SELECT_CC_I8 : PPCCustomInserterPseudo<(outs g8rc:$dst), (ins crrc:$cond,
g8rc_nox0:$T, g8rc_nox0:$F, g8rc_nox0:$T, g8rc_nox0:$F,
i32imm:$BROPC), "#SELECT_CC_I8", i32imm:$BROPC), "#SELECT_CC_I8",
[]>; []>;
def SELECT_CC_F4 : Pseudo<(outs f4rc:$dst), (ins crrc:$cond, f4rc:$T, f4rc:$F, def SELECT_CC_F4 : PPCCustomInserterPseudo<(outs f4rc:$dst), (ins crrc:$cond, f4rc:$T, f4rc:$F,
i32imm:$BROPC), "#SELECT_CC_F4", i32imm:$BROPC), "#SELECT_CC_F4",
[]>; []>;
def SELECT_CC_F8 : Pseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F, def SELECT_CC_F8 : PPCCustomInserterPseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F,
i32imm:$BROPC), "#SELECT_CC_F8", i32imm:$BROPC), "#SELECT_CC_F8",
[]>; []>;
def SELECT_CC_F16 : Pseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F, def SELECT_CC_F16 : PPCCustomInserterPseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F,
i32imm:$BROPC), "#SELECT_CC_F16", i32imm:$BROPC), "#SELECT_CC_F16",
[]>; []>;
def SELECT_CC_VRRC: Pseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F, def SELECT_CC_VRRC: PPCCustomInserterPseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F,
i32imm:$BROPC), "#SELECT_CC_VRRC", i32imm:$BROPC), "#SELECT_CC_VRRC",
[]>; []>;
// SELECT_* pseudo instructions, like SELECT_CC_* but taking condition // SELECT_* pseudo instructions, like SELECT_CC_* but taking condition
// register bit directly. // register bit directly.
def SELECT_I4 : Pseudo<(outs gprc:$dst), (ins crbitrc:$cond, def SELECT_I4 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins crbitrc:$cond,
gprc_nor0:$T, gprc_nor0:$F), "#SELECT_I4", gprc_nor0:$T, gprc_nor0:$F), "#SELECT_I4",
[(set i32:$dst, (select i1:$cond, i32:$T, i32:$F))]>; [(set i32:$dst, (select i1:$cond, i32:$T, i32:$F))]>;
def SELECT_I8 : Pseudo<(outs g8rc:$dst), (ins crbitrc:$cond, def SELECT_I8 : PPCCustomInserterPseudo<(outs g8rc:$dst), (ins crbitrc:$cond,
g8rc_nox0:$T, g8rc_nox0:$F), "#SELECT_I8", g8rc_nox0:$T, g8rc_nox0:$F), "#SELECT_I8",
[(set i64:$dst, (select i1:$cond, i64:$T, i64:$F))]>; [(set i64:$dst, (select i1:$cond, i64:$T, i64:$F))]>;
let Predicates = [HasFPU] in { let Predicates = [HasFPU] in {
def SELECT_F4 : Pseudo<(outs f4rc:$dst), (ins crbitrc:$cond, def SELECT_F4 : PPCCustomInserterPseudo<(outs f4rc:$dst), (ins crbitrc:$cond,
f4rc:$T, f4rc:$F), "#SELECT_F4", f4rc:$T, f4rc:$F), "#SELECT_F4",
[(set f32:$dst, (select i1:$cond, f32:$T, f32:$F))]>; [(set f32:$dst, (select i1:$cond, f32:$T, f32:$F))]>;
def SELECT_F8 : Pseudo<(outs f8rc:$dst), (ins crbitrc:$cond, def SELECT_F8 : PPCCustomInserterPseudo<(outs f8rc:$dst), (ins crbitrc:$cond,
f8rc:$T, f8rc:$F), "#SELECT_F8", f8rc:$T, f8rc:$F), "#SELECT_F8",
[(set f64:$dst, (select i1:$cond, f64:$T, f64:$F))]>; [(set f64:$dst, (select i1:$cond, f64:$T, f64:$F))]>;
def SELECT_F16 : Pseudo<(outs vrrc:$dst), (ins crbitrc:$cond, def SELECT_F16 : PPCCustomInserterPseudo<(outs vrrc:$dst), (ins crbitrc:$cond,
vrrc:$T, vrrc:$F), "#SELECT_F16", vrrc:$T, vrrc:$F), "#SELECT_F16",
[(set f128:$dst, (select i1:$cond, f128:$T, f128:$F))]>; [(set f128:$dst, (select i1:$cond, f128:$T, f128:$F))]>;
} }
def SELECT_VRRC: Pseudo<(outs vrrc:$dst), (ins crbitrc:$cond, def SELECT_VRRC: PPCCustomInserterPseudo<(outs vrrc:$dst), (ins crbitrc:$cond,
vrrc:$T, vrrc:$F), "#SELECT_VRRC", vrrc:$T, vrrc:$F), "#SELECT_VRRC",
[(set v4i32:$dst, [(set v4i32:$dst,
(select i1:$cond, v4i32:$T, v4i32:$F))]>; (select i1:$cond, v4i32:$T, v4i32:$F))]>;
@ -1274,18 +1273,18 @@ let Predicates = [HasFPU] in {
// SPILL_CR - Indicate that we're dumping the CR register, so we'll need to // SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
// scavenge a register for it. // scavenge a register for it.
let mayStore = 1 in { let mayStore = 1 in {
def SPILL_CR : Pseudo<(outs), (ins crrc:$cond, memri:$F), def SPILL_CR : PPCEmitTimePseudo<(outs), (ins crrc:$cond, memri:$F),
"#SPILL_CR", []>; "#SPILL_CR", []>;
def SPILL_CRBIT : Pseudo<(outs), (ins crbitrc:$cond, memri:$F), def SPILL_CRBIT : PPCEmitTimePseudo<(outs), (ins crbitrc:$cond, memri:$F),
"#SPILL_CRBIT", []>; "#SPILL_CRBIT", []>;
} }
// RESTORE_CR - Indicate that we're restoring the CR register (previously // RESTORE_CR - Indicate that we're restoring the CR register (previously
// spilled), so we'll need to scavenge a register for it. // spilled), so we'll need to scavenge a register for it.
let mayLoad = 1 in { let mayLoad = 1 in {
def RESTORE_CR : Pseudo<(outs crrc:$cond), (ins memri:$F), def RESTORE_CR : PPCEmitTimePseudo<(outs crrc:$cond), (ins memri:$F),
"#RESTORE_CR", []>; "#RESTORE_CR", []>;
def RESTORE_CRBIT : Pseudo<(outs crbitrc:$cond), (ins memri:$F), def RESTORE_CRBIT : PPCEmitTimePseudo<(outs crbitrc:$cond), (ins memri:$F),
"#RESTORE_CRBIT", []>; "#RESTORE_CRBIT", []>;
} }
@ -1311,10 +1310,10 @@ let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
} }
let Defs = [LR] in let Defs = [LR] in
def MovePCtoLR : Pseudo<(outs), (ins), "#MovePCtoLR", []>, def MovePCtoLR : PPCEmitTimePseudo<(outs), (ins), "#MovePCtoLR", []>,
PPC970_Unit_BRU; PPC970_Unit_BRU;
let Defs = [LR] in let Defs = [LR] in
def MoveGOTtoLR : Pseudo<(outs), (ins), "#MoveGOTtoLR", []>, def MoveGOTtoLR : PPCEmitTimePseudo<(outs), (ins), "#MoveGOTtoLR", []>,
PPC970_Unit_BRU; PPC970_Unit_BRU;
let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in { let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
@ -1512,19 +1511,19 @@ let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
} }
let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
def TCRETURNdi :Pseudo< (outs), def TCRETURNdi :PPCEmitTimePseudo< (outs),
(ins calltarget:$dst, i32imm:$offset), (ins calltarget:$dst, i32imm:$offset),
"#TC_RETURNd $dst $offset", "#TC_RETURNd $dst $offset",
[]>; []>;
let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
def TCRETURNai :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset), def TCRETURNai :PPCEmitTimePseudo<(outs), (ins abscalltarget:$func, i32imm:$offset),
"#TC_RETURNa $func $offset", "#TC_RETURNa $func $offset",
[(PPCtc_return (i32 imm:$func), imm:$offset)]>; [(PPCtc_return (i32 imm:$func), imm:$offset)]>;
let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset), def TCRETURNri : PPCEmitTimePseudo<(outs), (ins CTRRC:$dst, i32imm:$offset),
"#TC_RETURNr $dst $offset", "#TC_RETURNr $dst $offset",
[]>; []>;
@ -1552,17 +1551,17 @@ def TAILBA : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst),
// While longjmp is a control-flow barrier (fallthrough isn't allowed), setjmp // While longjmp is a control-flow barrier (fallthrough isn't allowed), setjmp
// is not. // is not.
let hasSideEffects = 1, usesCustomInserter = 1 in { let hasSideEffects = 1 in {
let Defs = [CTR] in let Defs = [CTR] in
def EH_SjLj_SetJmp32 : Pseudo<(outs gprc:$dst), (ins memr:$buf), def EH_SjLj_SetJmp32 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins memr:$buf),
"#EH_SJLJ_SETJMP32", "#EH_SJLJ_SETJMP32",
[(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>, [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
Requires<[In32BitMode]>; Requires<[In32BitMode]>;
} }
let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in { let hasSideEffects = 1, isBarrier = 1 in {
let isTerminator = 1 in let isTerminator = 1 in
def EH_SjLj_LongJmp32 : Pseudo<(outs), (ins memr:$buf), def EH_SjLj_LongJmp32 : PPCCustomInserterPseudo<(outs), (ins memr:$buf),
"#EH_SJLJ_LONGJMP32", "#EH_SJLJ_LONGJMP32",
[(PPCeh_sjlj_longjmp addr:$buf)]>, [(PPCeh_sjlj_longjmp addr:$buf)]>,
Requires<[In32BitMode]>; Requires<[In32BitMode]>;
@ -1572,7 +1571,7 @@ let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
// a terminator. Size is set to 0 to prevent the builtin assembler // a terminator. Size is set to 0 to prevent the builtin assembler
// from emitting it. // from emitting it.
let isBranch = 1, isTerminator = 1, Size = 0 in { let isBranch = 1, isTerminator = 1, Size = 0 in {
def EH_SjLj_Setup : Pseudo<(outs), (ins directbrtarget:$dst), def EH_SjLj_Setup : PPCEmitTimePseudo<(outs), (ins directbrtarget:$dst),
"#EH_SjLj_Setup\t$dst", []>; "#EH_SjLj_Setup\t$dst", []>;
} }
@ -1659,119 +1658,117 @@ def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 0)),
// clean this up in PPCMIPeephole with calls to // clean this up in PPCMIPeephole with calls to
// PPCInstrInfo::convertToImmediateForm() but we should probably not emit them // PPCInstrInfo::convertToImmediateForm() but we should probably not emit them
// in the first place. // in the first place.
let usesCustomInserter = 1 in { let Defs = [CR0] in {
let Defs = [CR0] in { def ATOMIC_LOAD_ADD_I8 : PPCCustomInserterPseudo<
def ATOMIC_LOAD_ADD_I8 : Pseudo< (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I8",
(outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I8", [(set i32:$dst, (atomic_load_add_8 xoaddr:$ptr, i32:$incr))]>;
[(set i32:$dst, (atomic_load_add_8 xoaddr:$ptr, i32:$incr))]>; def ATOMIC_LOAD_SUB_I8 : PPCCustomInserterPseudo<
def ATOMIC_LOAD_SUB_I8 : Pseudo< (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I8",
(outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I8", [(set i32:$dst, (atomic_load_sub_8 xoaddr:$ptr, i32:$incr))]>;
[(set i32:$dst, (atomic_load_sub_8 xoaddr:$ptr, i32:$incr))]>; def ATOMIC_LOAD_AND_I8 : PPCCustomInserterPseudo<
def ATOMIC_LOAD_AND_I8 : Pseudo< (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I8",
(outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I8", [(set i32:$dst, (atomic_load_and_8 xoaddr:$ptr, i32:$incr))]>;
[(set i32:$dst, (atomic_load_and_8 xoaddr:$ptr, i32:$incr))]>; def ATOMIC_LOAD_OR_I8 : PPCCustomInserterPseudo<
def ATOMIC_LOAD_OR_I8 : Pseudo< (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I8",
(outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I8", [(set i32:$dst, (atomic_load_or_8 xoaddr:$ptr, i32:$incr))]>;
[(set i32:$dst, (atomic_load_or_8 xoaddr:$ptr, i32:$incr))]>; def ATOMIC_LOAD_XOR_I8 : PPCCustomInserterPseudo<
def ATOMIC_LOAD_XOR_I8 : Pseudo< (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "ATOMIC_LOAD_XOR_I8",
(outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "ATOMIC_LOAD_XOR_I8", [(set i32:$dst, (atomic_load_xor_8 xoaddr:$ptr, i32:$incr))]>;
[(set i32:$dst, (atomic_load_xor_8 xoaddr:$ptr, i32:$incr))]>; def ATOMIC_LOAD_NAND_I8 : PPCCustomInserterPseudo<
def ATOMIC_LOAD_NAND_I8 : Pseudo< (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I8",
(outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I8", [(set i32:$dst, (atomic_load_nand_8 xoaddr:$ptr, i32:$incr))]>;
[(set i32:$dst, (atomic_load_nand_8 xoaddr:$ptr, i32:$incr))]>; def ATOMIC_LOAD_MIN_I8 : PPCCustomInserterPseudo<
def ATOMIC_LOAD_MIN_I8 : Pseudo< (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I8",
(outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I8", [(set i32:$dst, (atomic_load_min_8 xoaddr:$ptr, i32:$incr))]>;
[(set i32:$dst, (atomic_load_min_8 xoaddr:$ptr, i32:$incr))]>; def ATOMIC_LOAD_MAX_I8 : PPCCustomInserterPseudo<
def ATOMIC_LOAD_MAX_I8 : Pseudo< (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I8",
(outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I8", [(set i32:$dst, (atomic_load_max_8 xoaddr:$ptr, i32:$incr))]>;
[(set i32:$dst, (atomic_load_max_8 xoaddr:$ptr, i32:$incr))]>; def ATOMIC_LOAD_UMIN_I8 : PPCCustomInserterPseudo<
def ATOMIC_LOAD_UMIN_I8 : Pseudo< (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I8",
(outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I8", [(set i32:$dst, (atomic_load_umin_8 xoaddr:$ptr, i32:$incr))]>;
[(set i32:$dst, (atomic_load_umin_8 xoaddr:$ptr, i32:$incr))]>; def ATOMIC_LOAD_UMAX_I8 : PPCCustomInserterPseudo<
def ATOMIC_LOAD_UMAX_I8 : Pseudo< (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I8",
(outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I8", [(set i32:$dst, (atomic_load_umax_8 xoaddr:$ptr, i32:$incr))]>;
[(set i32:$dst, (atomic_load_umax_8 xoaddr:$ptr, i32:$incr))]>; def ATOMIC_LOAD_ADD_I16 : PPCCustomInserterPseudo<
def ATOMIC_LOAD_ADD_I16 : Pseudo< (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I16",
(outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I16", [(set i32:$dst, (atomic_load_add_16 xoaddr:$ptr, i32:$incr))]>;
[(set i32:$dst, (atomic_load_add_16 xoaddr:$ptr, i32:$incr))]>; def ATOMIC_LOAD_SUB_I16 : PPCCustomInserterPseudo<
def ATOMIC_LOAD_SUB_I16 : Pseudo< (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I16",
(outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I16", [(set i32:$dst, (atomic_load_sub_16 xoaddr:$ptr, i32:$incr))]>;
[(set i32:$dst, (atomic_load_sub_16 xoaddr:$ptr, i32:$incr))]>; def ATOMIC_LOAD_AND_I16 : PPCCustomInserterPseudo<
def ATOMIC_LOAD_AND_I16 : Pseudo< (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I16",
(outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I16", [(set i32:$dst, (atomic_load_and_16 xoaddr:$ptr, i32:$incr))]>;
[(set i32:$dst, (atomic_load_and_16 xoaddr:$ptr, i32:$incr))]>; def ATOMIC_LOAD_OR_I16 : PPCCustomInserterPseudo<
def ATOMIC_LOAD_OR_I16 : Pseudo< (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I16",
(outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I16", [(set i32:$dst, (atomic_load_or_16 xoaddr:$ptr, i32:$incr))]>;
[(set i32:$dst, (atomic_load_or_16 xoaddr:$ptr, i32:$incr))]>; def ATOMIC_LOAD_XOR_I16 : PPCCustomInserterPseudo<
def ATOMIC_LOAD_XOR_I16 : Pseudo< (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I16",
(outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I16", [(set i32:$dst, (atomic_load_xor_16 xoaddr:$ptr, i32:$incr))]>;
[(set i32:$dst, (atomic_load_xor_16 xoaddr:$ptr, i32:$incr))]>; def ATOMIC_LOAD_NAND_I16 : PPCCustomInserterPseudo<
def ATOMIC_LOAD_NAND_I16 : Pseudo< (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I16",
(outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I16", [(set i32:$dst, (atomic_load_nand_16 xoaddr:$ptr, i32:$incr))]>;
[(set i32:$dst, (atomic_load_nand_16 xoaddr:$ptr, i32:$incr))]>; def ATOMIC_LOAD_MIN_I16 : PPCCustomInserterPseudo<
def ATOMIC_LOAD_MIN_I16 : Pseudo< (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I16",
(outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I16", [(set i32:$dst, (atomic_load_min_16 xoaddr:$ptr, i32:$incr))]>;
[(set i32:$dst, (atomic_load_min_16 xoaddr:$ptr, i32:$incr))]>; def ATOMIC_LOAD_MAX_I16 : PPCCustomInserterPseudo<
def ATOMIC_LOAD_MAX_I16 : Pseudo< (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I16",
(outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I16", [(set i32:$dst, (atomic_load_max_16 xoaddr:$ptr, i32:$incr))]>;
[(set i32:$dst, (atomic_load_max_16 xoaddr:$ptr, i32:$incr))]>; def ATOMIC_LOAD_UMIN_I16 : PPCCustomInserterPseudo<
def ATOMIC_LOAD_UMIN_I16 : Pseudo< (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I16",
(outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I16", [(set i32:$dst, (atomic_load_umin_16 xoaddr:$ptr, i32:$incr))]>;
[(set i32:$dst, (atomic_load_umin_16 xoaddr:$ptr, i32:$incr))]>; def ATOMIC_LOAD_UMAX_I16 : PPCCustomInserterPseudo<
def ATOMIC_LOAD_UMAX_I16 : Pseudo< (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I16",
(outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I16", [(set i32:$dst, (atomic_load_umax_16 xoaddr:$ptr, i32:$incr))]>;
[(set i32:$dst, (atomic_load_umax_16 xoaddr:$ptr, i32:$incr))]>; def ATOMIC_LOAD_ADD_I32 : PPCCustomInserterPseudo<
def ATOMIC_LOAD_ADD_I32 : Pseudo< (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I32",
(outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I32", [(set i32:$dst, (atomic_load_add_32 xoaddr:$ptr, i32:$incr))]>;
[(set i32:$dst, (atomic_load_add_32 xoaddr:$ptr, i32:$incr))]>; def ATOMIC_LOAD_SUB_I32 : PPCCustomInserterPseudo<
def ATOMIC_LOAD_SUB_I32 : Pseudo< (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I32",
(outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I32", [(set i32:$dst, (atomic_load_sub_32 xoaddr:$ptr, i32:$incr))]>;
[(set i32:$dst, (atomic_load_sub_32 xoaddr:$ptr, i32:$incr))]>; def ATOMIC_LOAD_AND_I32 : PPCCustomInserterPseudo<
def ATOMIC_LOAD_AND_I32 : Pseudo< (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I32",
(outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I32", [(set i32:$dst, (atomic_load_and_32 xoaddr:$ptr, i32:$incr))]>;
[(set i32:$dst, (atomic_load_and_32 xoaddr:$ptr, i32:$incr))]>; def ATOMIC_LOAD_OR_I32 : PPCCustomInserterPseudo<
def ATOMIC_LOAD_OR_I32 : Pseudo< (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I32",
(outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I32", [(set i32:$dst, (atomic_load_or_32 xoaddr:$ptr, i32:$incr))]>;
[(set i32:$dst, (atomic_load_or_32 xoaddr:$ptr, i32:$incr))]>; def ATOMIC_LOAD_XOR_I32 : PPCCustomInserterPseudo<
def ATOMIC_LOAD_XOR_I32 : Pseudo< (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I32",
(outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I32", [(set i32:$dst, (atomic_load_xor_32 xoaddr:$ptr, i32:$incr))]>;
[(set i32:$dst, (atomic_load_xor_32 xoaddr:$ptr, i32:$incr))]>; def ATOMIC_LOAD_NAND_I32 : PPCCustomInserterPseudo<
def ATOMIC_LOAD_NAND_I32 : Pseudo< (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I32",
(outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I32", [(set i32:$dst, (atomic_load_nand_32 xoaddr:$ptr, i32:$incr))]>;
[(set i32:$dst, (atomic_load_nand_32 xoaddr:$ptr, i32:$incr))]>; def ATOMIC_LOAD_MIN_I32 : PPCCustomInserterPseudo<
def ATOMIC_LOAD_MIN_I32 : Pseudo< (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I32",
(outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I32", [(set i32:$dst, (atomic_load_min_32 xoaddr:$ptr, i32:$incr))]>;
[(set i32:$dst, (atomic_load_min_32 xoaddr:$ptr, i32:$incr))]>; def ATOMIC_LOAD_MAX_I32 : PPCCustomInserterPseudo<
def ATOMIC_LOAD_MAX_I32 : Pseudo< (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I32",
(outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I32", [(set i32:$dst, (atomic_load_max_32 xoaddr:$ptr, i32:$incr))]>;
[(set i32:$dst, (atomic_load_max_32 xoaddr:$ptr, i32:$incr))]>; def ATOMIC_LOAD_UMIN_I32 : PPCCustomInserterPseudo<
def ATOMIC_LOAD_UMIN_I32 : Pseudo< (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I32",
(outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I32", [(set i32:$dst, (atomic_load_umin_32 xoaddr:$ptr, i32:$incr))]>;
[(set i32:$dst, (atomic_load_umin_32 xoaddr:$ptr, i32:$incr))]>; def ATOMIC_LOAD_UMAX_I32 : PPCCustomInserterPseudo<
def ATOMIC_LOAD_UMAX_I32 : Pseudo< (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I32",
(outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I32", [(set i32:$dst, (atomic_load_umax_32 xoaddr:$ptr, i32:$incr))]>;
[(set i32:$dst, (atomic_load_umax_32 xoaddr:$ptr, i32:$incr))]>;
def ATOMIC_CMP_SWAP_I8 : Pseudo< def ATOMIC_CMP_SWAP_I8 : PPCCustomInserterPseudo<
(outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I8", (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I8",
[(set i32:$dst, (atomic_cmp_swap_8 xoaddr:$ptr, i32:$old, i32:$new))]>; [(set i32:$dst, (atomic_cmp_swap_8 xoaddr:$ptr, i32:$old, i32:$new))]>;
def ATOMIC_CMP_SWAP_I16 : Pseudo< def ATOMIC_CMP_SWAP_I16 : PPCCustomInserterPseudo<
(outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new", (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new",
[(set i32:$dst, (atomic_cmp_swap_16 xoaddr:$ptr, i32:$old, i32:$new))]>; [(set i32:$dst, (atomic_cmp_swap_16 xoaddr:$ptr, i32:$old, i32:$new))]>;
def ATOMIC_CMP_SWAP_I32 : Pseudo< def ATOMIC_CMP_SWAP_I32 : PPCCustomInserterPseudo<
(outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new", (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new",
[(set i32:$dst, (atomic_cmp_swap_32 xoaddr:$ptr, i32:$old, i32:$new))]>; [(set i32:$dst, (atomic_cmp_swap_32 xoaddr:$ptr, i32:$old, i32:$new))]>;
def ATOMIC_SWAP_I8 : Pseudo< def ATOMIC_SWAP_I8 : PPCCustomInserterPseudo<
(outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_i8", (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_i8",
[(set i32:$dst, (atomic_swap_8 xoaddr:$ptr, i32:$new))]>; [(set i32:$dst, (atomic_swap_8 xoaddr:$ptr, i32:$new))]>;
def ATOMIC_SWAP_I16 : Pseudo< def ATOMIC_SWAP_I16 : PPCCustomInserterPseudo<
(outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I16", (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I16",
[(set i32:$dst, (atomic_swap_16 xoaddr:$ptr, i32:$new))]>; [(set i32:$dst, (atomic_swap_16 xoaddr:$ptr, i32:$new))]>;
def ATOMIC_SWAP_I32 : Pseudo< def ATOMIC_SWAP_I32 : PPCCustomInserterPseudo<
(outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I32", (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I32",
[(set i32:$dst, (atomic_swap_32 xoaddr:$ptr, i32:$new))]>; [(set i32:$dst, (atomic_swap_32 xoaddr:$ptr, i32:$new))]>;
}
} }
def : Pat<(PPCatomicCmpSwap_8 xoaddr:$ptr, i32:$old, i32:$new), def : Pat<(PPCatomicCmpSwap_8 xoaddr:$ptr, i32:$old, i32:$new),
@ -2554,8 +2551,8 @@ def MTPMR : XFXForm_1<31, 462, (outs), (ins i32imm:$SPR, gprc:$RT),
// A pseudo-instruction used to implement the read of the 64-bit cycle counter // A pseudo-instruction used to implement the read of the 64-bit cycle counter
// on a 32-bit target. // on a 32-bit target.
let hasSideEffects = 1, usesCustomInserter = 1 in let hasSideEffects = 1 in
def ReadTB : Pseudo<(outs gprc:$lo, gprc:$hi), (ins), def ReadTB : PPCCustomInserterPseudo<(outs gprc:$lo, gprc:$hi), (ins),
"#ReadTB", []>; "#ReadTB", []>;
let Uses = [CTR] in { let Uses = [CTR] in {
@ -2614,13 +2611,13 @@ def : InstAlias<"mfvrsave $rS", (MFVRSAVE gprc:$rS)>;
// SPILL_VRSAVE - Indicate that we're dumping the VRSAVE register, // SPILL_VRSAVE - Indicate that we're dumping the VRSAVE register,
// so we'll need to scavenge a register for it. // so we'll need to scavenge a register for it.
let mayStore = 1 in let mayStore = 1 in
def SPILL_VRSAVE : Pseudo<(outs), (ins VRSAVERC:$vrsave, memri:$F), def SPILL_VRSAVE : PPCEmitTimePseudo<(outs), (ins VRSAVERC:$vrsave, memri:$F),
"#SPILL_VRSAVE", []>; "#SPILL_VRSAVE", []>;
// RESTORE_VRSAVE - Indicate that we're restoring the VRSAVE register (previously // RESTORE_VRSAVE - Indicate that we're restoring the VRSAVE register (previously
// spilled), so we'll need to scavenge a register for it. // spilled), so we'll need to scavenge a register for it.
let mayLoad = 1 in let mayLoad = 1 in
def RESTORE_VRSAVE : Pseudo<(outs VRSAVERC:$vrsave), (ins memri:$F), def RESTORE_VRSAVE : PPCEmitTimePseudo<(outs VRSAVERC:$vrsave), (ins memri:$F),
"#RESTORE_VRSAVE", []>; "#RESTORE_VRSAVE", []>;
let hasSideEffects = 0 in { let hasSideEffects = 0 in {
@ -2659,9 +2656,9 @@ def MCRXRX : X_BF3<31, 576, (outs crrc:$BF), (ins),
} // hasSideEffects = 0 } // hasSideEffects = 0
let Predicates = [HasFPU] in { let Predicates = [HasFPU] in {
// Pseudo instruction to perform FADD in round-to-zero mode. // Custom inserter instruction to perform FADD in round-to-zero mode.
let usesCustomInserter = 1, Uses = [RM] in { let Uses = [RM] in {
def FADDrtz: Pseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "", def FADDrtz: PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "",
[(set f64:$FRT, (PPCfaddrtz f64:$FRA, f64:$FRB))]>; [(set f64:$FRT, (PPCfaddrtz f64:$FRA, f64:$FRB))]>;
} }
@ -3033,23 +3030,23 @@ def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)),
(ADDIS $in, tblockaddress:$g)>; (ADDIS $in, tblockaddress:$g)>;
// Support for thread-local storage. // Support for thread-local storage.
def PPC32GOT: Pseudo<(outs gprc:$rD), (ins), "#PPC32GOT", def PPC32GOT: PPCEmitTimePseudo<(outs gprc:$rD), (ins), "#PPC32GOT",
[(set i32:$rD, (PPCppc32GOT))]>; [(set i32:$rD, (PPCppc32GOT))]>;
// Get the _GLOBAL_OFFSET_TABLE_ in PIC mode. // Get the _GLOBAL_OFFSET_TABLE_ in PIC mode.
// This uses two output registers, the first as the real output, the second as a // This uses two output registers, the first as the real output, the second as a
// temporary register, used internally in code generation. // temporary register, used internally in code generation.
def PPC32PICGOT: Pseudo<(outs gprc:$rD, gprc:$rT), (ins), "#PPC32PICGOT", def PPC32PICGOT: PPCEmitTimePseudo<(outs gprc:$rD, gprc:$rT), (ins), "#PPC32PICGOT",
[]>, NoEncode<"$rT">; []>, NoEncode<"$rT">;
def LDgotTprelL32: Pseudo<(outs gprc:$rD), (ins s16imm:$disp, gprc_nor0:$reg), def LDgotTprelL32: PPCEmitTimePseudo<(outs gprc:$rD), (ins s16imm:$disp, gprc_nor0:$reg),
"#LDgotTprelL32", "#LDgotTprelL32",
[(set i32:$rD, [(set i32:$rD,
(PPCldGotTprelL tglobaltlsaddr:$disp, i32:$reg))]>; (PPCldGotTprelL tglobaltlsaddr:$disp, i32:$reg))]>;
def : Pat<(PPCaddTls i32:$in, tglobaltlsaddr:$g), def : Pat<(PPCaddTls i32:$in, tglobaltlsaddr:$g),
(ADD4TLS $in, tglobaltlsaddr:$g)>; (ADD4TLS $in, tglobaltlsaddr:$g)>;
def ADDItlsgdL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), def ADDItlsgdL32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
"#ADDItlsgdL32", "#ADDItlsgdL32",
[(set i32:$rD, [(set i32:$rD,
(PPCaddiTlsgdL i32:$reg, tglobaltlsaddr:$disp))]>; (PPCaddiTlsgdL i32:$reg, tglobaltlsaddr:$disp))]>;
@ -3057,7 +3054,7 @@ def ADDItlsgdL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
// explicitly defined when this op is created, so not mentioned here. // explicitly defined when this op is created, so not mentioned here.
let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
def GETtlsADDR32 : Pseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym), def GETtlsADDR32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym),
"GETtlsADDR32", "GETtlsADDR32",
[(set i32:$rD, [(set i32:$rD,
(PPCgetTlsAddr i32:$reg, tglobaltlsaddr:$sym))]>; (PPCgetTlsAddr i32:$reg, tglobaltlsaddr:$sym))]>;
@ -3065,14 +3062,14 @@ def GETtlsADDR32 : Pseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym),
// are true defines while the rest of the Defs are clobbers. // are true defines while the rest of the Defs are clobbers.
let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
def ADDItlsgdLADDR32 : Pseudo<(outs gprc:$rD), def ADDItlsgdLADDR32 : PPCEmitTimePseudo<(outs gprc:$rD),
(ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym), (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym),
"#ADDItlsgdLADDR32", "#ADDItlsgdLADDR32",
[(set i32:$rD, [(set i32:$rD,
(PPCaddiTlsgdLAddr i32:$reg, (PPCaddiTlsgdLAddr i32:$reg,
tglobaltlsaddr:$disp, tglobaltlsaddr:$disp,
tglobaltlsaddr:$sym))]>; tglobaltlsaddr:$sym))]>;
def ADDItlsldL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), def ADDItlsldL32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
"#ADDItlsldL32", "#ADDItlsldL32",
[(set i32:$rD, [(set i32:$rD,
(PPCaddiTlsldL i32:$reg, tglobaltlsaddr:$disp))]>; (PPCaddiTlsldL i32:$reg, tglobaltlsaddr:$disp))]>;
@ -3080,7 +3077,7 @@ def ADDItlsldL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
// explicitly defined when this op is created, so not mentioned here. // explicitly defined when this op is created, so not mentioned here.
let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
def GETtlsldADDR32 : Pseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym), def GETtlsldADDR32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym),
"GETtlsldADDR32", "GETtlsldADDR32",
[(set i32:$rD, [(set i32:$rD,
(PPCgetTlsldAddr i32:$reg, (PPCgetTlsldAddr i32:$reg,
@ -3089,31 +3086,31 @@ def GETtlsldADDR32 : Pseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym),
// are true defines while the rest of the Defs are clobbers. // are true defines while the rest of the Defs are clobbers.
let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
def ADDItlsldLADDR32 : Pseudo<(outs gprc:$rD), def ADDItlsldLADDR32 : PPCEmitTimePseudo<(outs gprc:$rD),
(ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym), (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym),
"#ADDItlsldLADDR32", "#ADDItlsldLADDR32",
[(set i32:$rD, [(set i32:$rD,
(PPCaddiTlsldLAddr i32:$reg, (PPCaddiTlsldLAddr i32:$reg,
tglobaltlsaddr:$disp, tglobaltlsaddr:$disp,
tglobaltlsaddr:$sym))]>; tglobaltlsaddr:$sym))]>;
def ADDIdtprelL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), def ADDIdtprelL32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
"#ADDIdtprelL32", "#ADDIdtprelL32",
[(set i32:$rD, [(set i32:$rD,
(PPCaddiDtprelL i32:$reg, tglobaltlsaddr:$disp))]>; (PPCaddiDtprelL i32:$reg, tglobaltlsaddr:$disp))]>;
def ADDISdtprelHA32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), def ADDISdtprelHA32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
"#ADDISdtprelHA32", "#ADDISdtprelHA32",
[(set i32:$rD, [(set i32:$rD,
(PPCaddisDtprelHA i32:$reg, (PPCaddisDtprelHA i32:$reg,
tglobaltlsaddr:$disp))]>; tglobaltlsaddr:$disp))]>;
// Support for Position-independent code // Support for Position-independent code
def LWZtoc : Pseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc:$reg), def LWZtoc : PPCEmitTimePseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc:$reg),
"#LWZtoc", "#LWZtoc",
[(set i32:$rD, [(set i32:$rD,
(PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>; (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>;
// Get Global (GOT) Base Register offset, from the word immediately preceding // Get Global (GOT) Base Register offset, from the word immediately preceding
// the function label. // the function label.
def UpdateGBR : Pseudo<(outs gprc:$rD, gprc:$rT), (ins gprc:$rI), "#UpdateGBR", []>; def UpdateGBR : PPCEmitTimePseudo<(outs gprc:$rD, gprc:$rT), (ins gprc:$rI), "#UpdateGBR", []>;
// Standard shifts. These are represented separately from the real shifts above // Standard shifts. These are represented separately from the real shifts above
@ -3941,21 +3938,19 @@ def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETUGT)),
def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETNE)), def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETNE)),
(SELECT_VRRC (CRXOR $lhs, $rhs), $tval, $fval)>; (SELECT_VRRC (CRXOR $lhs, $rhs), $tval, $fval)>;
let usesCustomInserter = 1 in { def ANDIo_1_EQ_BIT : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins gprc:$in),
def ANDIo_1_EQ_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in),
"#ANDIo_1_EQ_BIT", "#ANDIo_1_EQ_BIT",
[(set i1:$dst, (trunc (not i32:$in)))]>; [(set i1:$dst, (trunc (not i32:$in)))]>;
def ANDIo_1_GT_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in), def ANDIo_1_GT_BIT : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins gprc:$in),
"#ANDIo_1_GT_BIT", "#ANDIo_1_GT_BIT",
[(set i1:$dst, (trunc i32:$in))]>; [(set i1:$dst, (trunc i32:$in))]>;
def ANDIo_1_EQ_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in), def ANDIo_1_EQ_BIT8 : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins g8rc:$in),
"#ANDIo_1_EQ_BIT8", "#ANDIo_1_EQ_BIT8",
[(set i1:$dst, (trunc (not i64:$in)))]>; [(set i1:$dst, (trunc (not i64:$in)))]>;
def ANDIo_1_GT_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in), def ANDIo_1_GT_BIT8 : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins g8rc:$in),
"#ANDIo_1_GT_BIT8", "#ANDIo_1_GT_BIT8",
[(set i1:$dst, (trunc i64:$in))]>; [(set i1:$dst, (trunc i64:$in))]>;
}
def : Pat<(i1 (not (trunc i32:$in))), def : Pat<(i1 (not (trunc i32:$in))),
(ANDIo_1_EQ_BIT $in)>; (ANDIo_1_EQ_BIT $in)>;

48
lib/Target/PowerPC/PPCInstrQPX.td
View File

@ -245,32 +245,30 @@ let Uses = [RM] in {
// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
// instruction selection into a branch sequence. // instruction selection into a branch sequence.
let usesCustomInserter = 1 in { def SELECT_CC_QFRC: PPCCustomInserterPseudo<(outs qfrc:$dst), (ins crrc:$cond, qfrc:$T, qfrc:$F,
def SELECT_CC_QFRC: Pseudo<(outs qfrc:$dst), (ins crrc:$cond, qfrc:$T, qfrc:$F, i32imm:$BROPC), "#SELECT_CC_QFRC",
i32imm:$BROPC), "#SELECT_CC_QFRC", []>;
[]>; def SELECT_CC_QSRC: PPCCustomInserterPseudo<(outs qsrc:$dst), (ins crrc:$cond, qsrc:$T, qsrc:$F,
def SELECT_CC_QSRC: Pseudo<(outs qsrc:$dst), (ins crrc:$cond, qsrc:$T, qsrc:$F, i32imm:$BROPC), "#SELECT_CC_QSRC",
i32imm:$BROPC), "#SELECT_CC_QSRC", []>;
[]>; def SELECT_CC_QBRC: PPCCustomInserterPseudo<(outs qbrc:$dst), (ins crrc:$cond, qbrc:$T, qbrc:$F,
def SELECT_CC_QBRC: Pseudo<(outs qbrc:$dst), (ins crrc:$cond, qbrc:$T, qbrc:$F, i32imm:$BROPC), "#SELECT_CC_QBRC",
i32imm:$BROPC), "#SELECT_CC_QBRC", []>;
[]>;
// SELECT_* pseudo instructions, like SELECT_CC_* but taking condition // SELECT_* pseudo instructions, like SELECT_CC_* but taking condition
// register bit directly. // register bit directly.
def SELECT_QFRC: Pseudo<(outs qfrc:$dst), (ins crbitrc:$cond, def SELECT_QFRC: PPCCustomInserterPseudo<(outs qfrc:$dst), (ins crbitrc:$cond,
qfrc:$T, qfrc:$F), "#SELECT_QFRC", qfrc:$T, qfrc:$F), "#SELECT_QFRC",
[(set v4f64:$dst, [(set v4f64:$dst,
(select i1:$cond, v4f64:$T, v4f64:$F))]>; (select i1:$cond, v4f64:$T, v4f64:$F))]>;
def SELECT_QSRC: Pseudo<(outs qsrc:$dst), (ins crbitrc:$cond, def SELECT_QSRC: PPCCustomInserterPseudo<(outs qsrc:$dst), (ins crbitrc:$cond,
qsrc:$T, qsrc:$F), "#SELECT_QSRC", qsrc:$T, qsrc:$F), "#SELECT_QSRC",
[(set v4f32:$dst, [(set v4f32:$dst,
(select i1:$cond, v4f32:$T, v4f32:$F))]>; (select i1:$cond, v4f32:$T, v4f32:$F))]>;
def SELECT_QBRC: Pseudo<(outs qbrc:$dst), (ins crbitrc:$cond, def SELECT_QBRC: PPCCustomInserterPseudo<(outs qbrc:$dst), (ins crbitrc:$cond,
qbrc:$T, qbrc:$F), "#SELECT_QBRC", qbrc:$T, qbrc:$F), "#SELECT_QBRC",
[(set v4i1:$dst, [(set v4i1:$dst,
(select i1:$cond, v4i1:$T, v4i1:$F))]>; (select i1:$cond, v4i1:$T, v4i1:$F))]>;
}
// Convert and Round Instructions // Convert and Round Instructions
def QVFCTID : QPXX19_Int<4, 814, "qvfctid", int_ppc_qpx_qvfctid>; def QVFCTID : QPXX19_Int<4, 814, "qvfctid", int_ppc_qpx_qvfctid>;

10
lib/Target/PowerPC/PPCInstrSPE.td
View File

@ -831,22 +831,20 @@ def : Pat<(f64 (fpextend f32:$src)),
} }
let Predicates = [HasSPE] in { let Predicates = [HasSPE] in {
let usesCustomInserter = 1 in { def SELECT_CC_SPE4 : PPCCustomInserterPseudo<(outs spe4rc:$dst),
def SELECT_CC_SPE4 : Pseudo<(outs spe4rc:$dst),
(ins crrc:$cond, spe4rc:$T, spe4rc:$F, (ins crrc:$cond, spe4rc:$T, spe4rc:$F,
i32imm:$BROPC), "#SELECT_CC_SPE4", i32imm:$BROPC), "#SELECT_CC_SPE4",
[]>; []>;
def SELECT_CC_SPE : Pseudo<(outs sperc:$dst), def SELECT_CC_SPE : PPCCustomInserterPseudo<(outs sperc:$dst),
(ins crrc:$cond, sperc:$T, sperc:$F, i32imm:$BROPC), (ins crrc:$cond, sperc:$T, sperc:$F, i32imm:$BROPC),
"#SELECT_CC_SPE", "#SELECT_CC_SPE",
[]>; []>;
def SELECT_SPE4 : Pseudo<(outs spe4rc:$dst), (ins crbitrc:$cond, def SELECT_SPE4 : PPCCustomInserterPseudo<(outs spe4rc:$dst), (ins crbitrc:$cond,
spe4rc:$T, spe4rc:$F), "#SELECT_SPE4", spe4rc:$T, spe4rc:$F), "#SELECT_SPE4",
[(set f32:$dst, (select i1:$cond, f32:$T, f32:$F))]>; [(set f32:$dst, (select i1:$cond, f32:$T, f32:$F))]>;
def SELECT_SPE : Pseudo<(outs sperc:$dst), (ins crbitrc:$cond, def SELECT_SPE : PPCCustomInserterPseudo<(outs sperc:$dst), (ins crbitrc:$cond,
sperc:$T, sperc:$F), "#SELECT_SPE", sperc:$T, sperc:$F), "#SELECT_SPE",
[(set f64:$dst, (select i1:$cond, f64:$T, f64:$F))]>; [(set f64:$dst, (select i1:$cond, f64:$T, f64:$F))]>;
}
def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)), def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)),
(SELECT_SPE4 (CRANDC $lhs, $rhs), $tval, $fval)>; (SELECT_SPE4 (CRANDC $lhs, $rhs), $tval, $fval)>;

128
lib/Target/PowerPC/PPCInstrVSX.td
View File

@ -132,7 +132,7 @@ let Uses = [RM] in {
[]>; []>;
// Pseudo instruction XFLOADf64 will be expanded to LXSDX or LFDX later // Pseudo instruction XFLOADf64 will be expanded to LXSDX or LFDX later
let isPseudo = 1, CodeSize = 3 in let CodeSize = 3 in
def XFLOADf64 : PseudoXFormMemOp<(outs vsfrc:$XT), (ins memrr:$src), def XFLOADf64 : PseudoXFormMemOp<(outs vsfrc:$XT), (ins memrr:$src),
"#XFLOADf64", "#XFLOADf64",
[(set f64:$XT, (load xoaddr:$src))]>; [(set f64:$XT, (load xoaddr:$src))]>;
@ -163,7 +163,7 @@ let Uses = [RM] in {
[]>; []>;
// Pseudo instruction XFSTOREf64 will be expanded to STXSDX or STFDX later // Pseudo instruction XFSTOREf64 will be expanded to STXSDX or STFDX later
let isPseudo = 1, CodeSize = 3 in let CodeSize = 3 in
def XFSTOREf64 : PseudoXFormMemOp<(outs), (ins vsfrc:$XT, memrr:$dst), def XFSTOREf64 : PseudoXFormMemOp<(outs), (ins vsfrc:$XT, memrr:$dst),
"#XFSTOREf64", "#XFSTOREf64",
[(store f64:$XT, xoaddr:$dst)]>; [(store f64:$XT, xoaddr:$dst)]>;
@ -898,37 +898,36 @@ let Uses = [RM] in {
// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
// instruction selection into a branch sequence. // instruction selection into a branch sequence.
let usesCustomInserter = 1, // Expanded after instruction selection. let PPC970_Single = 1 in {
PPC970_Single = 1 in {
def SELECT_CC_VSRC: Pseudo<(outs vsrc:$dst), def SELECT_CC_VSRC: PPCCustomInserterPseudo<(outs vsrc:$dst),
(ins crrc:$cond, vsrc:$T, vsrc:$F, i32imm:$BROPC), (ins crrc:$cond, vsrc:$T, vsrc:$F, i32imm:$BROPC),
"#SELECT_CC_VSRC", "#SELECT_CC_VSRC",
[]>; []>;
def SELECT_VSRC: Pseudo<(outs vsrc:$dst), def SELECT_VSRC: PPCCustomInserterPseudo<(outs vsrc:$dst),
(ins crbitrc:$cond, vsrc:$T, vsrc:$F), (ins crbitrc:$cond, vsrc:$T, vsrc:$F),
"#SELECT_VSRC", "#SELECT_VSRC",
[(set v2f64:$dst, [(set v2f64:$dst,
(select i1:$cond, v2f64:$T, v2f64:$F))]>; (select i1:$cond, v2f64:$T, v2f64:$F))]>;
def SELECT_CC_VSFRC: Pseudo<(outs f8rc:$dst), def SELECT_CC_VSFRC: PPCCustomInserterPseudo<(outs f8rc:$dst),
(ins crrc:$cond, f8rc:$T, f8rc:$F, (ins crrc:$cond, f8rc:$T, f8rc:$F,
i32imm:$BROPC), "#SELECT_CC_VSFRC", i32imm:$BROPC), "#SELECT_CC_VSFRC",
[]>; []>;
def SELECT_VSFRC: Pseudo<(outs f8rc:$dst), def SELECT_VSFRC: PPCCustomInserterPseudo<(outs f8rc:$dst),
(ins crbitrc:$cond, f8rc:$T, f8rc:$F), (ins crbitrc:$cond, f8rc:$T, f8rc:$F),
"#SELECT_VSFRC", "#SELECT_VSFRC",
[(set f64:$dst, [(set f64:$dst,
(select i1:$cond, f64:$T, f64:$F))]>; (select i1:$cond, f64:$T, f64:$F))]>;
def SELECT_CC_VSSRC: Pseudo<(outs f4rc:$dst), def SELECT_CC_VSSRC: PPCCustomInserterPseudo<(outs f4rc:$dst),
(ins crrc:$cond, f4rc:$T, f4rc:$F, (ins crrc:$cond, f4rc:$T, f4rc:$F,
i32imm:$BROPC), "#SELECT_CC_VSSRC", i32imm:$BROPC), "#SELECT_CC_VSSRC",
[]>; []>;
def SELECT_VSSRC: Pseudo<(outs f4rc:$dst), def SELECT_VSSRC: PPCCustomInserterPseudo<(outs f4rc:$dst),
(ins crbitrc:$cond, f4rc:$T, f4rc:$F), (ins crbitrc:$cond, f4rc:$T, f4rc:$F),
"#SELECT_VSSRC", "#SELECT_VSSRC",
[(set f32:$dst, [(set f32:$dst,
(select i1:$cond, f32:$T, f32:$F))]>; (select i1:$cond, f32:$T, f32:$F))]>;
} // usesCustomInserter }
} // AddedComplexity } // AddedComplexity
def : InstAlias<"xvmovdp $XT, $XB", def : InstAlias<"xvmovdp $XT, $XB",
@ -1254,23 +1253,19 @@ let AddedComplexity = 400 in { // Prefer VSX patterns over non-VSX patterns.
def LXSIWZX : XX1Form_memOp<31, 12, (outs vsfrc:$XT), (ins memrr:$src), def LXSIWZX : XX1Form_memOp<31, 12, (outs vsfrc:$XT), (ins memrr:$src),
"lxsiwzx $XT, $src", IIC_LdStLFD, []>; "lxsiwzx $XT, $src", IIC_LdStLFD, []>;
// Please note let isPseudo = 1 is not part of class Pseudo<>. Missing it // Pseudo instruction XFLOADf32 will be expanded to LXSSPX or LFSX later
// would cause these Pseudos are not expanded in expandPostRAPseudos() let CodeSize = 3 in
let isPseudo = 1 in { def XFLOADf32 : PseudoXFormMemOp<(outs vssrc:$XT), (ins memrr:$src),
// Pseudo instruction XFLOADf32 will be expanded to LXSSPX or LFSX later "#XFLOADf32",
let CodeSize = 3 in [(set f32:$XT, (load xoaddr:$src))]>;
def XFLOADf32 : PseudoXFormMemOp<(outs vssrc:$XT), (ins memrr:$src), // Pseudo instruction LIWAX will be expanded to LXSIWAX or LFIWAX later
"#XFLOADf32", def LIWAX : PseudoXFormMemOp<(outs vsfrc:$XT), (ins memrr:$src),
[(set f32:$XT, (load xoaddr:$src))]>; "#LIWAX",
// Pseudo instruction LIWAX will be expanded to LXSIWAX or LFIWAX later [(set f64:$XT, (PPClfiwax xoaddr:$src))]>;
def LIWAX : PseudoXFormMemOp<(outs vsfrc:$XT), (ins memrr:$src), // Pseudo instruction LIWZX will be expanded to LXSIWZX or LFIWZX later
"#LIWAX", def LIWZX : PseudoXFormMemOp<(outs vsfrc:$XT), (ins memrr:$src),
[(set f64:$XT, (PPClfiwax xoaddr:$src))]>; "#LIWZX",
// Pseudo instruction LIWZX will be expanded to LXSIWZX or LFIWZX later [(set f64:$XT, (PPClfiwzx xoaddr:$src))]>;
def LIWZX : PseudoXFormMemOp<(outs vsfrc:$XT), (ins memrr:$src),
"#LIWZX",
[(set f64:$XT, (PPClfiwzx xoaddr:$src))]>;
}
} // mayLoad } // mayLoad
// VSX scalar stores introduced in ISA 2.07 // VSX scalar stores introduced in ISA 2.07
@ -1281,19 +1276,15 @@ let AddedComplexity = 400 in { // Prefer VSX patterns over non-VSX patterns.
def STXSIWX : XX1Form_memOp<31, 140, (outs), (ins vsfrc:$XT, memrr:$dst), def STXSIWX : XX1Form_memOp<31, 140, (outs), (ins vsfrc:$XT, memrr:$dst),
"stxsiwx $XT, $dst", IIC_LdStSTFD, []>; "stxsiwx $XT, $dst", IIC_LdStSTFD, []>;
// Please note let isPseudo = 1 is not part of class Pseudo<>. Missing it // Pseudo instruction XFSTOREf32 will be expanded to STXSSPX or STFSX later
// would cause these Pseudos are not expanded in expandPostRAPseudos() let CodeSize = 3 in
let isPseudo = 1 in { def XFSTOREf32 : PseudoXFormMemOp<(outs), (ins vssrc:$XT, memrr:$dst),
// Pseudo instruction XFSTOREf32 will be expanded to STXSSPX or STFSX later "#XFSTOREf32",
let CodeSize = 3 in [(store f32:$XT, xoaddr:$dst)]>;
def XFSTOREf32 : PseudoXFormMemOp<(outs), (ins vssrc:$XT, memrr:$dst), // Pseudo instruction STIWX will be expanded to STXSIWX or STFIWX later
"#XFSTOREf32", def STIWX : PseudoXFormMemOp<(outs), (ins vsfrc:$XT, memrr:$dst),
[(store f32:$XT, xoaddr:$dst)]>; "#STIWX",
// Pseudo instruction STIWX will be expanded to STXSIWX or STFIWX later [(PPCstfiwx f64:$XT, xoaddr:$dst)]>;
def STIWX : PseudoXFormMemOp<(outs), (ins vsfrc:$XT, memrr:$dst),
"#STIWX",
[(PPCstfiwx f64:$XT, xoaddr:$dst)]>;
}
} // mayStore } // mayStore
} // UseVSXReg = 1 } // UseVSXReg = 1
@ -3262,20 +3253,19 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in {
def : Pat<(f64 (PPCVexts f64:$A, 2)), def : Pat<(f64 (PPCVexts f64:$A, 2)),
(f64 (COPY_TO_REGCLASS (VEXTSH2Ds $A), VSFRC))>; (f64 (COPY_TO_REGCLASS (VEXTSH2Ds $A), VSFRC))>;
let isPseudo = 1 in { def DFLOADf32 : PPCPostRAExpPseudo<(outs vssrc:$XT), (ins memrix:$src),
def DFLOADf32 : Pseudo<(outs vssrc:$XT), (ins memrix:$src), "#DFLOADf32",
"#DFLOADf32", [(set f32:$XT, (load ixaddr:$src))]>;
[(set f32:$XT, (load ixaddr:$src))]>; def DFLOADf64 : PPCPostRAExpPseudo<(outs vsfrc:$XT), (ins memrix:$src),
def DFLOADf64 : Pseudo<(outs vsfrc:$XT), (ins memrix:$src), "#DFLOADf64",
"#DFLOADf64", [(set f64:$XT, (load ixaddr:$src))]>;
[(set f64:$XT, (load ixaddr:$src))]>; def DFSTOREf32 : PPCPostRAExpPseudo<(outs), (ins vssrc:$XT, memrix:$dst),
def DFSTOREf32 : Pseudo<(outs), (ins vssrc:$XT, memrix:$dst), "#DFSTOREf32",
"#DFSTOREf32", [(store f32:$XT, ixaddr:$dst)]>;
[(store f32:$XT, ixaddr:$dst)]>; def DFSTOREf64 : PPCPostRAExpPseudo<(outs), (ins vsfrc:$XT, memrix:$dst),
def DFSTOREf64 : Pseudo<(outs), (ins vsfrc:$XT, memrix:$dst), "#DFSTOREf64",
"#DFSTOREf64", [(store f64:$XT, ixaddr:$dst)]>;
[(store f64:$XT, ixaddr:$dst)]>;
}
def : Pat<(f64 (extloadf32 ixaddr:$src)), def : Pat<(f64 (extloadf32 ixaddr:$src)),
(COPY_TO_REGCLASS (DFLOADf32 ixaddr:$src), VSFRC)>; (COPY_TO_REGCLASS (DFLOADf32 ixaddr:$src), VSFRC)>;
def : Pat<(f32 (fpround (f64 (extloadf32 ixaddr:$src)))), def : Pat<(f32 (fpround (f64 (extloadf32 ixaddr:$src)))),
@ -3557,22 +3547,20 @@ let AddedComplexity = 400 in {
} }
let Predicates = [HasP9Vector] in { let Predicates = [HasP9Vector] in {
let isPseudo = 1 in { let mayStore = 1 in {
let mayStore = 1 in { def SPILLTOVSR_STX : PseudoXFormMemOp<(outs),
def SPILLTOVSR_STX : PseudoXFormMemOp<(outs), (ins spilltovsrrc:$XT, memrr:$dst),
(ins spilltovsrrc:$XT, memrr:$dst), "#SPILLTOVSR_STX", []>;
"#SPILLTOVSR_STX", []>; def SPILLTOVSR_ST : PPCPostRAExpPseudo<(outs), (ins spilltovsrrc:$XT, memrix:$dst),
def SPILLTOVSR_ST : Pseudo<(outs), (ins spilltovsrrc:$XT, memrix:$dst), "#SPILLTOVSR_ST", []>;
"#SPILLTOVSR_ST", []>; }
} let mayLoad = 1 in {
let mayLoad = 1 in { def SPILLTOVSR_LDX : PseudoXFormMemOp<(outs spilltovsrrc:$XT),
def SPILLTOVSR_LDX : PseudoXFormMemOp<(outs spilltovsrrc:$XT), (ins memrr:$src),
(ins memrr:$src), "#SPILLTOVSR_LDX", []>;
"#SPILLTOVSR_LDX", []>; def SPILLTOVSR_LD : PPCPostRAExpPseudo<(outs spilltovsrrc:$XT), (ins memrix:$src),
def SPILLTOVSR_LD : Pseudo<(outs spilltovsrrc:$XT), (ins memrix:$src), "#SPILLTOVSR_LD", []>;
"#SPILLTOVSR_LD", []>;
}
} }
} }
// Integer extend helper dags 32 -> 64 // Integer extend helper dags 32 -> 64