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[x86] Replace some duplicated logic reasoning about whether particular
vector lanes can be modeled as zero with a call to the new function that computes a bit-vector representing that information. No functionality changed here, but will allow doing more clever things with the zero-test. llvm-svn: 218174
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@ -7556,10 +7556,16 @@ static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
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static SDValue lowerIntegerElementInsertionVectorShuffle(
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MVT VT, SDLoc DL, SDValue V1, SDValue V2, ArrayRef<int> Mask,
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const X86Subtarget *Subtarget, SelectionDAG &DAG) {
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SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
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int V2Index = std::find_if(Mask.begin(), Mask.end(),
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[&Mask](int M) { return M >= (int)Mask.size(); }) -
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Mask.begin();
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for (int i = 0, Size = Mask.size(); i < Size; ++i)
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if (i != V2Index && !Zeroable[i])
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return SDValue(); // Not inserting into a zero vector.
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// Check for a single input from a SCALAR_TO_VECTOR node.
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// FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
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// all the smarts here sunk into that routine. However, the current
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@ -7572,19 +7578,6 @@ static SDValue lowerIntegerElementInsertionVectorShuffle(
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SDValue V2S = V2.getOperand(Mask[V2Index] - Mask.size());
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if (V1.getOpcode() == ISD::BUILD_VECTOR) {
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for (int M : Mask) {
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if (M < 0 || M >= (int)Mask.size())
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continue;
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SDValue Input = V1.getOperand(M);
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if (Input.getOpcode() != ISD::UNDEF && !X86::isZeroNode(Input))
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// A non-zero input!
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return SDValue();
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}
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} else if (!ISD::isBuildVectorAllZeros(V1.getNode())) {
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return SDValue();
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}
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// First, we need to zext the scalar if it is smaller than an i32.
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MVT EltVT = VT.getVectorElementType();
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assert(EltVT == V2S.getSimpleValueType() &&
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