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AMDGPU/SI: Teach SIInstrInfo::FoldImmediate() to fold immediates into copies
Summary: I put this code here, because I want to re-use it in a few other places. This supersedes some of the immediate folding code we have in SIFoldOperands. I think the peephole optimizers is probably a better place for folding immediates into copies, since it does some register coalescing in the same time. This will also make it easier to transition SIFoldOperands into a smarter pass, where it looks at all uses of instruction at once to determine the optimal way to fold operands. Right now, the pass just considers one operand at a time. Reviewers: arsenm Subscribers: wdng, nhaehnle, arsenm, llvm-commits, kzhuravl Differential Revision: https://reviews.llvm.org/D23402 llvm-svn: 280744
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@ -1184,14 +1184,39 @@ static void removeModOperands(MachineInstr &MI) {
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MI.RemoveOperand(Src0ModIdx);
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}
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// TODO: Maybe this should be removed this and custom fold everything in
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// SIFoldOperands?
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bool SIInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
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unsigned Reg, MachineRegisterInfo *MRI) const {
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if (!MRI->hasOneNonDBGUse(Reg))
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return false;
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unsigned Opc = UseMI.getOpcode();
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if (Opc == AMDGPU::COPY) {
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bool isVGPRCopy = RI.isVGPR(*MRI, UseMI.getOperand(0).getReg());
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switch (DefMI.getOpcode()) {
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default:
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return false;
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case AMDGPU::S_MOV_B64:
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// TODO: We could fold 64-bit immediates, but this get compilicated
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// when there are sub-registers.
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return false;
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case AMDGPU::V_MOV_B32_e32:
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case AMDGPU::S_MOV_B32:
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break;
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}
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unsigned NewOpc = isVGPRCopy ? AMDGPU::V_MOV_B32_e32 : AMDGPU::S_MOV_B32;
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const MachineOperand *ImmOp = getNamedOperand(DefMI, AMDGPU::OpName::src0);
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assert(ImmOp);
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// FIXME: We could handle FrameIndex values here.
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if (!ImmOp->isImm()) {
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return false;
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}
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UseMI.setDesc(get(NewOpc));
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UseMI.getOperand(1).ChangeToImmediate(ImmOp->getImm());
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UseMI.addImplicitDefUseOperands(*UseMI.getParent()->getParent());
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return true;
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}
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if (Opc == AMDGPU::V_MAD_F32 || Opc == AMDGPU::V_MAC_F32_e64) {
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// Don't fold if we are using source modifiers. The new VOP2 instructions
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// don't have them.
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@ -25,6 +25,7 @@ class SOP1_Pseudo <string opName, dag outs, dag ins,
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let SALU = 1;
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let SOP1 = 1;
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let SchedRW = [WriteSALU];
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let UseNamedOperandTable = 1;
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string Mnemonic = opName;
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string AsmOperands = asmOps;
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@ -1100,4 +1101,4 @@ def S_GETREG_B32_vi : SOPK_Real_vi <0x11, S_GETREG_B32>;
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def S_SETREG_B32_vi : SOPK_Real_vi <0x12, S_SETREG_B32>;
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//def S_GETREG_REGRD_B32_vi : SOPK_Real_vi <0x13, S_GETREG_REGRD_B32>; // see pseudo for comments
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def S_SETREG_IMM32_B32_vi : SOPK_Real64<0x14, S_SETREG_IMM32_B32>,
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Select_vi<S_SETREG_IMM32_B32.Mnemonic>;
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Select_vi<S_SETREG_IMM32_B32.Mnemonic>;
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