mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-20 19:42:54 +02:00
[DAG] Don't increase SDNodeOrder for dbg.value/declare.
Summary: The SDNodeOrder is saved in the IROrder field in the SDNode, and this field may affects scheduling. Thus, letting dbg.value/declare increase the order numbers may in turn affect scheduling. Because of this change we also need to update the code deciding when dbg values should be output, in ScheduleDAGSDNodes.cpp/ProcessSDDbgValues. Dbg values now have the same order as the SDNode they are connected to, not the following orders. Test cases provided by Florian Hahn. Reviewers: bogner, aprantl, sunfish, atrick Reviewed By: atrick Subscribers: fhahn, probinson, andreadb, llvm-commits, MatzeB Differential Revision: https://reviews.llvm.org/D25318 llvm-svn: 292485
This commit is contained in:
Mikael Holmen
parent
a0ed49e2c8
commit
ba88ebaa68
@ -704,8 +704,8 @@ ProcessSDDbgValues(SDNode *N, SelectionDAG *DAG, InstrEmitter &Emitter,
|
||||
if (!N->getHasDebugValue())
|
||||
return;
|
||||
|
||||
// Opportunistically insert immediate dbg_value uses, i.e. those with source
|
||||
// order number right after the N.
|
||||
// Opportunistically insert immediate dbg_value uses, i.e. those with the same
|
||||
// source order number as N.
|
||||
MachineBasicBlock *BB = Emitter.getBlock();
|
||||
MachineBasicBlock::iterator InsertPos = Emitter.getInsertPos();
|
||||
ArrayRef<SDDbgValue*> DVs = DAG->GetDbgValues(N);
|
||||
@ -713,7 +713,7 @@ ProcessSDDbgValues(SDNode *N, SelectionDAG *DAG, InstrEmitter &Emitter,
|
||||
if (DVs[i]->isInvalidated())
|
||||
continue;
|
||||
unsigned DVOrder = DVs[i]->getOrder();
|
||||
if (!Order || DVOrder == ++Order) {
|
||||
if (!Order || DVOrder == Order) {
|
||||
MachineInstr *DbgMI = Emitter.EmitDbgValue(DVs[i], VRBaseMap);
|
||||
if (DbgMI) {
|
||||
Orders.push_back(std::make_pair(DVOrder, DbgMI));
|
||||
|
||||
@ -937,7 +937,9 @@ void SelectionDAGBuilder::visit(const Instruction &I) {
|
||||
HandlePHINodesInSuccessorBlocks(I.getParent());
|
||||
}
|
||||
|
||||
++SDNodeOrder;
|
||||
// Increase the SDNodeOrder if dealing with a non-debug instruction.
|
||||
if (!isa<DbgInfoIntrinsic>(I))
|
||||
++SDNodeOrder;
|
||||
|
||||
CurInst = &I;
|
||||
|
||||
|
||||
96
test/CodeGen/AArch64/selectiondag-order.ll
Normal file
96
test/CodeGen/AArch64/selectiondag-order.ll
Normal file
@ -0,0 +1,96 @@
|
||||
; Check that debug intrinsics do not affect code generation.
|
||||
|
||||
; RUN: llc < %s -mtriple=aarch64-unknown-unknown -mattr=+avx | FileCheck --check-prefix=AARCH64-CHECK %s
|
||||
|
||||
define i64 @simulate(<2 x i32> %a) {
|
||||
entry:
|
||||
%rand = tail call i64 @lrand48()
|
||||
br label %body
|
||||
|
||||
body: ; preds = %body, %entry
|
||||
%0 = phi <2 x i32> [ %add, %body ], [ zeroinitializer, %entry ]
|
||||
%add = add <2 x i32> %0, %a
|
||||
%rand1 = tail call i64 @lrand48() #3
|
||||
%cmp = icmp eq i64 %rand1, 0
|
||||
br i1 %cmp, label %end, label %body
|
||||
|
||||
end: ; preds = %body
|
||||
%c = bitcast <2 x i32> %add to i64
|
||||
%res = add i64 %rand, %c
|
||||
ret i64 %res
|
||||
}
|
||||
|
||||
; AARCH64-CHECK: simulate:
|
||||
; AARCH64-CHECK: movi d9, #0000000000000000
|
||||
; AARCH64-CHECK: bl lrand48
|
||||
; AARCH64-CHECK: mov x19, x0
|
||||
; AARCH64-CHECK: BB0_1:
|
||||
|
||||
|
||||
define i64 @simulateWithDebugIntrinsic(<2 x i32> %a) local_unnamed_addr {
|
||||
entry:
|
||||
%rand = tail call i64 @lrand48() #3
|
||||
tail call void @llvm.dbg.value(metadata i64 %rand, i64 0, metadata !6, metadata !7), !dbg !8
|
||||
br label %body
|
||||
|
||||
body: ; preds = %body, %entry
|
||||
%0 = phi <2 x i32> [ %add, %body ], [ zeroinitializer, %entry ]
|
||||
%add = add <2 x i32> %0, %a
|
||||
%rand1 = tail call i64 @lrand48() #3
|
||||
%cmp = icmp eq i64 %rand1, 0
|
||||
br i1 %cmp, label %end, label %body
|
||||
|
||||
end: ; preds = %body
|
||||
%c = bitcast <2 x i32> %add to i64
|
||||
%res = add i64 %rand, %c
|
||||
ret i64 %res
|
||||
}
|
||||
|
||||
; AARCH64-CHECK: simulateWithDebugIntrinsic
|
||||
; AARCH64-CHECK: movi d9, #0000000000000000
|
||||
; AARCH64-CHECK: bl lrand48
|
||||
; AARCH64-CHECK: mov x19, x0
|
||||
; AARCH64-CHECK: BB1_1:
|
||||
|
||||
|
||||
define i64 @simulateWithDbgDeclare(<2 x i32> %a) local_unnamed_addr {
|
||||
entry:
|
||||
%rand = tail call i64 @lrand48() #3
|
||||
tail call void @llvm.dbg.declare(metadata i64 %rand, metadata !6, metadata !7), !dbg !8
|
||||
br label %body
|
||||
|
||||
body: ; preds = %body, %entry
|
||||
%0 = phi <2 x i32> [ %add, %body ], [ zeroinitializer, %entry ]
|
||||
%add = add <2 x i32> %0, %a
|
||||
%rand1 = tail call i64 @lrand48() #3
|
||||
%cmp = icmp eq i64 %rand1, 0
|
||||
br i1 %cmp, label %end, label %body
|
||||
|
||||
end: ; preds = %body
|
||||
%c = bitcast <2 x i32> %add to i64
|
||||
%res = add i64 %rand, %c
|
||||
ret i64 %res
|
||||
}
|
||||
|
||||
; AARCH64-CHECK: simulateWithDbgDeclare:
|
||||
; AARCH64-CHECK: movi d9, #0000000000000000
|
||||
; AARCH64-CHECK: bl lrand48
|
||||
; AARCH64-CHECK: mov x19, x0
|
||||
; AARCH64-CHECK: BB2_1:
|
||||
|
||||
declare i64 @lrand48()
|
||||
|
||||
declare void @llvm.dbg.value(metadata, i64, metadata, metadata)
|
||||
declare void @llvm.dbg.declare(metadata, metadata, metadata)
|
||||
|
||||
!llvm.dbg.cu = !{!1}
|
||||
!llvm.module.flags = !{!3, !4}
|
||||
|
||||
!1 = distinct !DICompileUnit(language: DW_LANG_C99, file: !2, runtimeVersion: 0, emissionKind: FullDebug)
|
||||
!2 = !DIFile(filename: "test.ll", directory: ".")
|
||||
!3 = !{i32 2, !"Dwarf Version", i32 4}
|
||||
!4 = !{i32 2, !"Debug Info Version", i32 3}
|
||||
!5 = distinct !DISubprogram(name: "simulateWithDebugIntrinsic", scope: !2, file: !2, line: 64, isLocal: false, isDefinition: true, scopeLine: 65, unit: !1)
|
||||
!6 = !DILocalVariable(name: "randv", scope: !5, file: !2, line: 69)
|
||||
!7 = !DIExpression()
|
||||
!8 = !DILocation(line: 132, column: 2, scope: !5)
|
||||
97
test/CodeGen/X86/selectiondag-order.ll
Normal file
97
test/CodeGen/X86/selectiondag-order.ll
Normal file
@ -0,0 +1,97 @@
|
||||
; Check that debug intrinsics do not affect code generation.
|
||||
|
||||
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck --check-prefix=X86-CHECK %s
|
||||
|
||||
define i64 @simulate(<2 x i32> %a) {
|
||||
entry:
|
||||
%rand = tail call i64 @lrand48()
|
||||
br label %body
|
||||
|
||||
body: ; preds = %body, %entry
|
||||
%0 = phi <2 x i32> [ %add, %body ], [ zeroinitializer, %entry ]
|
||||
%add = add <2 x i32> %0, %a
|
||||
%rand1 = tail call i64 @lrand48() #3
|
||||
%cmp = icmp eq i64 %rand1, 0
|
||||
br i1 %cmp, label %end, label %body
|
||||
|
||||
end: ; preds = %body
|
||||
%c = bitcast <2 x i32> %add to i64
|
||||
%res = add i64 %rand, %c
|
||||
ret i64 %res
|
||||
}
|
||||
|
||||
; X86-CHECK: simulate:
|
||||
; X86-CHECK: movdqa %xmm0, 16(%rsp)
|
||||
; X86-CHECK: pxor %xmm0, %xmm0
|
||||
; X86-CHECK: movdqa %xmm0, (%rsp)
|
||||
; X86-CHECK: callq lrand48
|
||||
; X86-CHECK: movq %rax, %rbx
|
||||
|
||||
define i64 @simulateWithDebugIntrinsic(<2 x i32> %a) local_unnamed_addr {
|
||||
entry:
|
||||
%rand = tail call i64 @lrand48() #3
|
||||
tail call void @llvm.dbg.value(metadata i64 %rand, i64 0, metadata !6, metadata !7), !dbg !8
|
||||
br label %body
|
||||
|
||||
body: ; preds = %body, %entry
|
||||
%0 = phi <2 x i32> [ %add, %body ], [ zeroinitializer, %entry ]
|
||||
%add = add <2 x i32> %0, %a
|
||||
%rand1 = tail call i64 @lrand48() #3
|
||||
%cmp = icmp eq i64 %rand1, 0
|
||||
br i1 %cmp, label %end, label %body
|
||||
|
||||
end: ; preds = %body
|
||||
%c = bitcast <2 x i32> %add to i64
|
||||
%res = add i64 %rand, %c
|
||||
ret i64 %res
|
||||
}
|
||||
|
||||
; X86-CHECK: simulateWithDebugIntrinsic:
|
||||
; X86-CHECK: movdqa %xmm0, 16(%rsp)
|
||||
; X86-CHECK: pxor %xmm0, %xmm0
|
||||
; X86-CHECK: movdqa %xmm0, (%rsp)
|
||||
; X86-CHECK: callq lrand48
|
||||
; X86-CHECK: movq %rax, %rbx
|
||||
|
||||
define i64 @simulateWithDbgDeclare(<2 x i32> %a) local_unnamed_addr {
|
||||
entry:
|
||||
%rand = tail call i64 @lrand48() #3
|
||||
tail call void @llvm.dbg.declare(metadata i64 %rand, metadata !6, metadata !7), !dbg !8
|
||||
br label %body
|
||||
|
||||
body: ; preds = %body, %entry
|
||||
%0 = phi <2 x i32> [ %add, %body ], [ zeroinitializer, %entry ]
|
||||
%add = add <2 x i32> %0, %a
|
||||
%rand1 = tail call i64 @lrand48() #3
|
||||
%cmp = icmp eq i64 %rand1, 0
|
||||
br i1 %cmp, label %end, label %body
|
||||
|
||||
end: ; preds = %body
|
||||
%c = bitcast <2 x i32> %add to i64
|
||||
%res = add i64 %rand, %c
|
||||
ret i64 %res
|
||||
}
|
||||
|
||||
; X86-CHECK: simulateWithDbgDeclare:
|
||||
; X86-CHECK: movdqa %xmm0, 16(%rsp)
|
||||
; X86-CHECK: pxor %xmm0, %xmm0
|
||||
; X86-CHECK: movdqa %xmm0, (%rsp)
|
||||
; X86-CHECK: callq lrand48
|
||||
; X86-CHECK: movq %rax, %rbx
|
||||
|
||||
declare i64 @lrand48()
|
||||
|
||||
declare void @llvm.dbg.value(metadata, i64, metadata, metadata)
|
||||
declare void @llvm.dbg.declare(metadata, metadata, metadata)
|
||||
|
||||
!llvm.dbg.cu = !{!1}
|
||||
!llvm.module.flags = !{!3, !4}
|
||||
|
||||
!1 = distinct !DICompileUnit(language: DW_LANG_C99, file: !2, runtimeVersion: 0, emissionKind: FullDebug)
|
||||
!2 = !DIFile(filename: "test.ll", directory: ".")
|
||||
!3 = !{i32 2, !"Dwarf Version", i32 4}
|
||||
!4 = !{i32 2, !"Debug Info Version", i32 3}
|
||||
!5 = distinct !DISubprogram(name: "simulateWithDebugIntrinsic", scope: !2, file: !2, line: 64, isLocal: false, isDefinition: true, scopeLine: 65, unit: !1)
|
||||
!6 = !DILocalVariable(name: "randv", scope: !5, file: !2, line: 69)
|
||||
!7 = !DIExpression()
|
||||
!8 = !DILocation(line: 132, column: 2, scope: !5)
|
||||
Loading…
Reference in New Issue
Block a user