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[AArch64][GlobalISel] Add some vector support for fp <-> int conversions.

Browse Source 
Some unrelated, but benign, test changes as well due to the test update script.

llvm-svn: 352337
This commit is contained in:
Amara Emerson 2019-01-28 02:27:59 +00:00
parent b5f68065fb
commit ba9fd8068d
5 changed files with 160 additions and 12 deletions
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4
lib/Target/AArch64/AArch64LegalizerInfo.cpp
View File

@ -270,14 +270,14 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) {
// Conversions
getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI})
.legalForCartesianProduct({s32, s64})
.legalForCartesianProduct({s32, s64, v2s64, v4s32, v2s32})
.clampScalar(0, s32, s64)
.widenScalarToNextPow2(0)
.clampScalar(1, s32, s64)
.widenScalarToNextPow2(1);
getActionDefinitionsBuilder({G_SITOFP, G_UITOFP})
.legalForCartesianProduct({s32, s64})
.legalForCartesianProduct({s32, s64, v2s64, v4s32, v2s32})
.clampScalar(1, s32, s64)
.widenScalarToNextPow2(1)
.clampScalar(0, s32, s64)

4
lib/Target/AArch64/AArch64RegisterBankInfo.cpp
View File

@ -565,10 +565,14 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
switch (Opc) {
case TargetOpcode::G_SITOFP:
case TargetOpcode::G_UITOFP:
if (MRI.getType(MI.getOperand(0).getReg()).isVector())
break;
OpRegBankIdx = {PMI_FirstFPR, PMI_FirstGPR};
break;
case TargetOpcode::G_FPTOSI:
case TargetOpcode::G_FPTOUI:
if (MRI.getType(MI.getOperand(0).getReg()).isVector())
break;
OpRegBankIdx = {PMI_FirstGPR, PMI_FirstFPR};
break;
case TargetOpcode::G_FCMP:

31
test/CodeGen/AArch64/GlobalISel/legalize-fptoi.mir
View File

@ -23,6 +23,9 @@
define void @test_fptosi_s16_s32() { ret void }
define void @test_fptoui_s16_s32() { ret void }
define void @test_fptoui_v4s32() { ret void }
define void @test_fptosi_v4s32() { ret void }
...
---
@ -234,3 +237,31 @@ body: |
%2:_(s32) = G_ANYEXT %1
$w0 = COPY %2
...
---
name: test_fptoui_v4s32
body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: test_fptoui_v4s32
; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
; CHECK: [[FPTOUI:%[0-9]+]]:_(<4 x s32>) = G_FPTOUI [[COPY]](<4 x s32>)
; CHECK: $q0 = COPY [[FPTOUI]](<4 x s32>)
%0:_(<4 x s32>) = COPY $q0
%1:_(<4 x s32>) = G_FPTOUI %0
$q0 = COPY %1
...
---
name: test_fptosi_v4s32
body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: test_fptosi_v4s32
; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
; CHECK: [[FPTOSI:%[0-9]+]]:_(<4 x s32>) = G_FPTOSI [[COPY]](<4 x s32>)
; CHECK: $q0 = COPY [[FPTOSI]](<4 x s32>)
%0:_(<4 x s32>) = COPY $q0
%1:_(<4 x s32>) = G_FPTOSI %0
$q0 = COPY %1
...

57
test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir
View File

@ -21,6 +21,9 @@
define void @test_sitofp_s64_s8() { ret void }
define void @test_uitofp_s64_s8() { ret void }
define void @test_sitofp_v4s32() { ret void }
define void @test_uitofp_v4s32() { ret void }
define void @test_sitofp_s32_s16() { ret void }
define void @test_uitofp_s32_s16() { ret void }
...
@ -33,6 +36,7 @@ body: |
; CHECK-LABEL: name: test_sitofp_s32_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[COPY]](s32)
; CHECK: $w0 = COPY [[SITOFP]](s32)
%0:_(s32) = COPY $w0
%1:_(s32) = G_SITOFP %0
$w0 = COPY %1
@ -46,6 +50,7 @@ body: |
; CHECK-LABEL: name: test_uitofp_s32_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[COPY]](s32)
; CHECK: $w0 = COPY [[UITOFP]](s32)
%0:_(s32) = COPY $w0
%1:_(s32) = G_UITOFP %0
$w0 = COPY %1
@ -59,6 +64,7 @@ body: |
; CHECK-LABEL: name: test_sitofp_s32_s64
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[COPY]](s64)
; CHECK: $w0 = COPY [[SITOFP]](s32)
%0:_(s64) = COPY $x0
%1:_(s32) = G_SITOFP %0
$w0 = COPY %1
@ -72,6 +78,7 @@ body: |
; CHECK-LABEL: name: test_uitofp_s32_s64
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[COPY]](s64)
; CHECK: $w0 = COPY [[UITOFP]](s32)
%0:_(s64) = COPY $x0
%1:_(s32) = G_UITOFP %0
$w0 = COPY %1
@ -85,6 +92,7 @@ body: |
; CHECK-LABEL: name: test_sitofp_s64_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[COPY]](s32)
; CHECK: $x0 = COPY [[SITOFP]](s64)
%0:_(s32) = COPY $w0
%1:_(s64) = G_SITOFP %0
$x0 = COPY %1
@ -98,6 +106,7 @@ body: |
; CHECK-LABEL: name: test_uitofp_s64_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[UITOFP:%[0-9]+]]:_(s64) = G_UITOFP [[COPY]](s32)
; CHECK: $x0 = COPY [[UITOFP]](s64)
%0:_(s32) = COPY $w0
%1:_(s64) = G_UITOFP %0
$x0 = COPY %1
@ -111,6 +120,7 @@ body: |
; CHECK-LABEL: name: test_sitofp_s64_s64
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[COPY]](s64)
; CHECK: $x0 = COPY [[SITOFP]](s64)
%0:_(s64) = COPY $x0
%1:_(s64) = G_SITOFP %0
$x0 = COPY %1
@ -124,6 +134,7 @@ body: |
; CHECK-LABEL: name: test_uitofp_s64_s64
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[UITOFP:%[0-9]+]]:_(s64) = G_UITOFP [[COPY]](s64)
; CHECK: $x0 = COPY [[UITOFP]](s64)
%0:_(s64) = COPY $x0
%1:_(s64) = G_UITOFP %0
$x0 = COPY %1
@ -139,9 +150,10 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]]
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; CHECK: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[ASHR]](s32)
; CHECK: $w0 = COPY [[SITOFP]](s32)
%0:_(s32) = COPY $w0
%1:_(s1) = G_TRUNC %0
%2:_(s32) = G_SITOFP %1
@ -159,6 +171,7 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND]](s32)
; CHECK: $w0 = COPY [[UITOFP]](s32)
%0:_(s32) = COPY $w0
%1:_(s1) = G_TRUNC %0
%2:_(s32) = G_UITOFP %1
@ -174,15 +187,44 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]]
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; CHECK: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[ASHR]](s32)
; CHECK: $x0 = COPY [[SITOFP]](s64)
%0:_(s32) = COPY $w0
%1:_(s8) = G_TRUNC %0
%2:_(s64) = G_SITOFP %1
$x0 = COPY %2
...
---
name: test_sitofp_v4s32
body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: test_sitofp_v4s32
; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
; CHECK: [[SITOFP:%[0-9]+]]:_(<4 x s32>) = G_SITOFP [[SITOFP]](<4 x s32>)
; CHECK: $q0 = COPY [[SITOFP]](<4 x s32>)
%0:_(<4 x s32>) = COPY $q0
%1:_(<4 x s32>) = G_SITOFP %1
$q0 = COPY %1
...
---
name: test_uitofp_v4s32
body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: test_uitofp_v4s32
; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
; CHECK: [[UITOFP:%[0-9]+]]:_(<4 x s32>) = G_UITOFP [[UITOFP]](<4 x s32>)
; CHECK: $q0 = COPY [[UITOFP]](<4 x s32>)
%0:_(<4 x s32>) = COPY $q0
%1:_(<4 x s32>) = G_UITOFP %1
$q0 = COPY %1
...
---
name: test_uitofp_s64_s8
body: |
@ -194,6 +236,7 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: [[UITOFP:%[0-9]+]]:_(s64) = G_UITOFP [[AND]](s32)
; CHECK: $x0 = COPY [[UITOFP]](s64)
%0:_(s32) = COPY $w0
%1:_(s8) = G_TRUNC %0
%2:_(s64) = G_UITOFP %1
@ -209,9 +252,10 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]]
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; CHECK: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[ASHR]](s32)
; CHECK: $w0 = COPY [[SITOFP]](s32)
%0:_(s32) = COPY $w0
%1:_(s16) = G_TRUNC %0
%2:_(s32) = G_SITOFP %1
@ -229,6 +273,7 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND]](s32)
; CHECK: $w0 = COPY [[UITOFP]](s32)
%0:_(s32) = COPY $w0
%1:_(s16) = G_TRUNC %0
%2:_(s32) = G_UITOFP %1

76
test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir
View File

@ -63,10 +63,14 @@
define void @test_fcmp_s32() { ret void }
define void @test_sitofp_s64_s32() { ret void }
define void @test_sitofp_v4s32() { ret void }
define void @test_uitofp_s32_s64() { ret void }
define void @test_uitofp_v4s32() { ret void }
define void @test_fptosi_s64_s32() { ret void }
define void @test_fptosi_v4s32() { ret void }
define void @test_fptoui_s32_s64() { ret void }
define void @test_fptoui_v4s32() { ret void }
define void @test_gphi_ptr() { ret void }
@ -275,7 +279,7 @@ body: |
liveins: $w0
; CHECK-LABEL: name: test_shl_s32
; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
; CHECK: [[SHL:%[0-9]+]]:gpr(s32) = G_SHL [[COPY]], [[COPY]]
; CHECK: [[SHL:%[0-9]+]]:gpr(s32) = G_SHL [[COPY]], [[COPY]](s32)
%0(s32) = COPY $w0
%1(s32) = G_SHL %0, %0
...
@ -291,7 +295,7 @@ body: |
liveins: $q0
; CHECK-LABEL: name: test_shl_v4s32
; CHECK: [[COPY:%[0-9]+]]:fpr(<4 x s32>) = COPY $q0
; CHECK: [[SHL:%[0-9]+]]:fpr(<4 x s32>) = G_SHL [[COPY]], [[COPY]]
; CHECK: [[SHL:%[0-9]+]]:fpr(<4 x s32>) = G_SHL [[COPY]], [[COPY]](<4 x s32>)
%0(<4 x s32>) = COPY $q0
%1(<4 x s32>) = G_SHL %0, %0
...
@ -307,7 +311,7 @@ body: |
liveins: $w0
; CHECK-LABEL: name: test_lshr_s32
; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
; CHECK: [[LSHR:%[0-9]+]]:gpr(s32) = G_LSHR [[COPY]], [[COPY]]
; CHECK: [[LSHR:%[0-9]+]]:gpr(s32) = G_LSHR [[COPY]], [[COPY]](s32)
%0(s32) = COPY $w0
%1(s32) = G_LSHR %0, %0
...
@ -323,7 +327,7 @@ body: |
liveins: $w0
; CHECK-LABEL: name: test_ashr_s32
; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
; CHECK: [[ASHR:%[0-9]+]]:gpr(s32) = G_ASHR [[COPY]], [[COPY]]
; CHECK: [[ASHR:%[0-9]+]]:gpr(s32) = G_ASHR [[COPY]], [[COPY]](s32)
%0(s32) = COPY $w0
%1(s32) = G_ASHR %0, %0
...
@ -709,6 +713,22 @@ body: |
%1(s64) = G_SITOFP %0
...
---
name: test_sitofp_v4s32
legalized: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: test_sitofp_v4s32
; CHECK: [[COPY:%[0-9]+]]:fpr(<4 x s32>) = COPY $q0
; CHECK: [[SITOFP:%[0-9]+]]:fpr(<4 x s32>) = G_SITOFP [[COPY]](<4 x s32>)
%0(<4 x s32>) = COPY $q0
%1(<4 x s32>) = G_SITOFP %0
...
---
name: test_uitofp_s32_s64
legalized: true
@ -725,6 +745,22 @@ body: |
%1(s32) = G_UITOFP %0
...
---
name: test_uitofp_v4s32
legalized: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: test_uitofp_v4s32
; CHECK: [[COPY:%[0-9]+]]:fpr(<4 x s32>) = COPY $q0
; CHECK: [[UITOFP:%[0-9]+]]:fpr(<4 x s32>) = G_UITOFP [[COPY]](<4 x s32>)
%0(<4 x s32>) = COPY $q0
%1(<4 x s32>) = G_UITOFP %0
...
---
name: test_fptosi_s64_s32
legalized: true
@ -741,6 +777,22 @@ body: |
%1(s64) = G_FPTOSI %0
...
---
name: test_fptosi_v4s32
legalized: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: test_fptosi_v4s32
; CHECK: [[COPY:%[0-9]+]]:fpr(<4 x s32>) = COPY $q0
; CHECK: [[FPTOSI:%[0-9]+]]:fpr(<4 x s32>) = G_FPTOSI [[COPY]](<4 x s32>)
%0(<4 x s32>) = COPY $q0
%1(<4 x s32>) = G_FPTOSI %0
...
---
name: test_fptoui_s32_s64
legalized: true
@ -757,6 +809,22 @@ body: |
%1(s32) = G_FPTOUI %0
...
---
name: test_fptoui_v4s32
legalized: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: test_fptoui_v4s32
; CHECK: [[COPY:%[0-9]+]]:fpr(<4 x s32>) = COPY $q0
; CHECK: [[FPTOUI:%[0-9]+]]:fpr(<4 x s32>) = G_FPTOUI [[COPY]](<4 x s32>)
%0(<4 x s32>) = COPY $q0
%1(<4 x s32>) = G_FPTOUI %0
...
---
name: test_gphi_ptr
legalized: true