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R600/SI: Move all fabs / fneg handling to patterns
llvm-svn: 215749
This commit is contained in:
Matt Arsenault
parent
134b10c2db
commit
babc0fbd04
@ -644,95 +644,6 @@ MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
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MI->eraseFromParent();
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break;
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}
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case AMDGPU::FABS_SI: {
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MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
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const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(
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getTargetMachine().getSubtargetImpl()->getInstrInfo());
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DebugLoc DL = MI->getDebugLoc();
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unsigned DestReg = MI->getOperand(0).getReg();
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unsigned Reg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
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BuildMI(*BB, I, DL, TII->get(AMDGPU::V_MOV_B32_e32), Reg)
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.addImm(0x7fffffff);
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BuildMI(*BB, I, DL, TII->get(AMDGPU::V_AND_B32_e32), DestReg)
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.addReg(MI->getOperand(1).getReg())
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.addReg(Reg);
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MI->eraseFromParent();
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break;
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}
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case AMDGPU::FABS64_SI: {
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MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
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const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(
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getTargetMachine().getSubtargetImpl()->getInstrInfo());
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DebugLoc DL = MI->getDebugLoc();
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unsigned SuperReg = MI->getOperand(0).getReg();
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unsigned SrcReg = MI->getOperand(1).getReg();
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unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
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// Copy the subregister to make sure it is the right register class.
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unsigned VReg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
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BuildMI(*BB, I, DL, TII->get(AMDGPU::COPY), VReg)
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.addReg(SrcReg, 0, AMDGPU::sub1);
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// We only need to mask the upper half of the register pair.
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BuildMI(*BB, I, DL, TII->get(AMDGPU::V_AND_B32_e32), TmpReg)
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.addImm(0x7fffffff)
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.addReg(VReg);
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BuildMI(*BB, I, DL, TII->get(AMDGPU::REG_SEQUENCE), SuperReg)
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.addReg(SrcReg, 0, AMDGPU::sub0)
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.addImm(AMDGPU::sub0)
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.addReg(TmpReg)
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.addImm(AMDGPU::sub1);
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MI->eraseFromParent();
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break;
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}
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case AMDGPU::FNEG_SI: {
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MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
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const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(
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getTargetMachine().getSubtargetImpl()->getInstrInfo());
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DebugLoc DL = MI->getDebugLoc();
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unsigned DestReg = MI->getOperand(0).getReg();
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unsigned Reg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
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// FIXME: Should use SALU instructions
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BuildMI(*BB, I, DL, TII->get(AMDGPU::V_MOV_B32_e32), Reg)
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.addImm(0x80000000);
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BuildMI(*BB, I, DL, TII->get(AMDGPU::V_XOR_B32_e32), DestReg)
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.addReg(MI->getOperand(1).getReg())
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.addReg(Reg);
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MI->eraseFromParent();
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break;
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}
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case AMDGPU::FNEG64_SI: {
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MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
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const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(
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getTargetMachine().getSubtargetImpl()->getInstrInfo());
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DebugLoc DL = MI->getDebugLoc();
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unsigned SrcReg = MI->getOperand(1).getReg();
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unsigned DestReg = MI->getOperand(0).getReg();
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unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
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unsigned ImmReg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
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// FIXME: Should use SALU instructions
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BuildMI(*BB, I, DL, TII->get(AMDGPU::V_MOV_B32_e32), ImmReg)
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.addImm(0x80000000);
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BuildMI(*BB, I, DL, TII->get(AMDGPU::V_XOR_B32_e32), TmpReg)
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.addReg(SrcReg, 0, AMDGPU::sub1)
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.addReg(ImmReg);
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BuildMI(*BB, I, DL, TII->get(AMDGPU::REG_SEQUENCE), DestReg)
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.addReg(SrcReg, 0, AMDGPU::sub0)
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.addImm(AMDGPU::sub0)
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.addReg(TmpReg)
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.addImm(AMDGPU::sub1);
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MI->eraseFromParent();
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break;
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}
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case AMDGPU::FCLAMP_SI: {
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const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(
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getTargetMachine().getSubtargetImpl()->getInstrInfo());
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@ -2322,48 +2322,51 @@ def : Pat <
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/********** Floating point absolute/negative **********/
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/********** ================================ **********/
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// Manipulate the sign bit directly, as e.g. using the source negation modifier
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// in V_ADD_F32_e64 $src, 0, [...] does not result in -0.0 for $src == +0.0,
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// breaking the piglit *s-floatBitsToInt-neg* tests
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// Prevent expanding both fneg and fabs.
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// TODO: Look into not implementing isFNegFree/isFAbsFree for SI, and possibly
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// removing these patterns
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// FIXME: Should use S_OR_B32
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def : Pat <
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(fneg (fabs f32:$src)),
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(V_OR_B32_e32 $src, (V_MOV_B32_e32 0x80000000)) /* Set sign bit */
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>;
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// FIXME: Should use S_OR_B32
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def : Pat <
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(fneg (fabs f64:$src)),
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(f64 (INSERT_SUBREG
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(INSERT_SUBREG (f64 (IMPLICIT_DEF)),
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(i32 (EXTRACT_SUBREG f64:$src, sub0)), sub0),
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(V_OR_B32_e32 (S_MOV_B32 0x80000000),
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(EXTRACT_SUBREG f64:$src, sub1)), sub1)) // Set sign bit.
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(V_OR_B32_e32 (EXTRACT_SUBREG f64:$src, sub1),
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(V_MOV_B32_e32 0x80000000)), sub1)) // Set sign bit.
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>;
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class SIUnaryCustomInsertInst<string name, SDPatternOperator node,
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ValueType vt,
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RegisterClass dstrc,
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RegisterClass srcrc> :
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AMDGPUShaderInst<
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(outs dstrc:$dst),
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(ins srcrc:$src0),
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name#" $dst, $src0",
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[(set vt:$dst, (node vt:$src0))]> {
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let usesCustomInserter = 1;
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}
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def : Pat <
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(fabs f32:$src),
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(V_AND_B32_e32 $src, (V_MOV_B32_e32 0x7fffffff))
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>;
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def FABS_SI : SIUnaryCustomInsertInst<"FABS_SI", fabs,
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f32, VReg_32, VSrc_32>;
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def FNEG_SI : SIUnaryCustomInsertInst<"FNEG_SI", fneg,
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f32, VReg_32, VSrc_32>;
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def : Pat <
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(fneg f32:$src),
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(V_XOR_B32_e32 $src, (V_MOV_B32_e32 0x80000000))
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>;
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def FABS64_SI : SIUnaryCustomInsertInst<"FABS64_SI", fabs,
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f64, VReg_64, VSrc_64>;
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def FNEG64_SI : SIUnaryCustomInsertInst<"FNEG64_SI", fneg,
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f64, VReg_64, VSrc_64>;
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def : Pat <
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(fabs f64:$src),
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(f64 (INSERT_SUBREG
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(INSERT_SUBREG (f64 (IMPLICIT_DEF)),
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(i32 (EXTRACT_SUBREG f64:$src, sub0)), sub0),
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(V_AND_B32_e32 (EXTRACT_SUBREG f64:$src, sub1),
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(V_MOV_B32_e32 0x7fffffff)), sub1)) // Set sign bit.
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>;
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def : Pat <
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(fneg f64:$src),
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(f64 (INSERT_SUBREG
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(INSERT_SUBREG (f64 (IMPLICIT_DEF)),
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(i32 (EXTRACT_SUBREG f64:$src, sub0)), sub0),
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(V_XOR_B32_e32 (EXTRACT_SUBREG f64:$src, sub1),
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(V_MOV_B32_e32 0x80000000)), sub1))
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>;
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/********** ================== **********/
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/********** Immediate Patterns **********/
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@ -72,7 +72,7 @@ define void @fabs_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %in) {
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; SI-LABEL: @fabs_fn_fold
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; SI: S_LOAD_DWORD [[ABS_VALUE:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xb
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; SI-NOT: V_AND_B32_e32
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; SI-NOT: AND
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; SI: V_MUL_F32_e64 v{{[0-9]+}}, |[[ABS_VALUE]]|, v{{[0-9]+}}
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define void @fabs_fn_fold(float addrspace(1)* %out, float %in0, float %in1) {
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%fabs = call float @fabs(float %in0)
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@ -83,7 +83,7 @@ define void @fabs_fn_fold(float addrspace(1)* %out, float %in0, float %in1) {
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; SI-LABEL: @fabs_fold
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; SI: S_LOAD_DWORD [[ABS_VALUE:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xb
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; SI-NOT: V_AND_B32_e32
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; SI-NOT: AND
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; SI: V_MUL_F32_e64 v{{[0-9]+}}, |[[ABS_VALUE]]|, v{{[0-9]+}}
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define void @fabs_fold(float addrspace(1)* %out, float %in0, float %in1) {
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%fabs = call float @llvm.fabs.f32(float %in0)
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@ -4,7 +4,8 @@
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; into 2 modifiers, although theoretically that should work.
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; FUNC-LABEL: @fneg_fabs_fadd_f64
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; SI: V_AND_B32_e32 v[[FABS:[0-9]+]], 0x7fffffff, {{v[0-9]+}}
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; SI: V_MOV_B32_e32 [[IMMREG:v[0-9]+]], 0x7fffffff
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; SI: V_AND_B32_e32 v[[FABS:[0-9]+]], {{s[0-9]+}}, [[IMMREG]]
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; SI: V_ADD_F64 {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, -v{{\[[0-9]+}}:[[FABS]]{{\]}}
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define void @fneg_fabs_fadd_f64(double addrspace(1)* %out, double %x, double %y) {
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%fabs = call double @llvm.fabs.f64(double %x)
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@ -44,7 +45,8 @@ define void @fneg_fabs_free_f64(double addrspace(1)* %out, i64 %in) {
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}
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; FUNC-LABEL: @fneg_fabs_fn_free_f64
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; SI: V_OR_B32_e32 v{{[0-9]+}}, 0x80000000, v{{[0-9]+}}
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; SI: V_MOV_B32_e32 [[IMMREG:v[0-9]+]], 0x80000000
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; SI: V_OR_B32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
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define void @fneg_fabs_fn_free_f64(double addrspace(1)* %out, i64 %in) {
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%bc = bitcast i64 %in to double
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%fabs = call double @fabs(double %bc)
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@ -54,6 +56,12 @@ define void @fneg_fabs_fn_free_f64(double addrspace(1)* %out, i64 %in) {
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}
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; FUNC-LABEL: @fneg_fabs_f64
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; SI: S_LOAD_DWORDX2
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; SI: S_LOAD_DWORDX2 s{{\[}}[[LO_X:[0-9]+]]:[[HI_X:[0-9]+]]{{\]}}
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; SI: V_MOV_B32_e32 [[IMMREG:v[0-9]+]], 0x80000000
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; SI-DAG: V_OR_B32_e32 v[[HI_V:[0-9]+]], s[[HI_X]], [[IMMREG]]
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; SI-DAG: V_MOV_B32_e32 v[[LO_V:[0-9]+]], s[[LO_X]]
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; SI: BUFFER_STORE_DWORDX2 v{{\[}}[[LO_V]]:[[HI_V]]{{\]}}
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define void @fneg_fabs_f64(double addrspace(1)* %out, double %in) {
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%fabs = call double @llvm.fabs.f64(double %in)
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%fsub = fsub double -0.000000e+00, %fabs
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@ -62,8 +70,10 @@ define void @fneg_fabs_f64(double addrspace(1)* %out, double %in) {
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}
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; FUNC-LABEL: @fneg_fabs_v2f64
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; SI: V_OR_B32_e32 v{{[0-9]+}}, 0x80000000, v{{[0-9]+}}
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; SI: V_OR_B32_e32 v{{[0-9]+}}, 0x80000000, v{{[0-9]+}}
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; SI: V_MOV_B32_e32 [[IMMREG:v[0-9]+]], 0x80000000
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; SI-NOT: 0x80000000
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; SI: V_OR_B32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
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; SI: V_OR_B32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
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define void @fneg_fabs_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %in) {
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%fabs = call <2 x double> @llvm.fabs.v2f64(<2 x double> %in)
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%fsub = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %fabs
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@ -72,10 +82,12 @@ define void @fneg_fabs_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %in)
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}
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; FUNC-LABEL: @fneg_fabs_v4f64
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; SI: V_OR_B32_e32 v{{[0-9]+}}, 0x80000000, v{{[0-9]+}}
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; SI: V_OR_B32_e32 v{{[0-9]+}}, 0x80000000, v{{[0-9]+}}
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; SI: V_OR_B32_e32 v{{[0-9]+}}, 0x80000000, v{{[0-9]+}}
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; SI: V_OR_B32_e32 v{{[0-9]+}}, 0x80000000, v{{[0-9]+}}
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; SI: V_MOV_B32_e32 [[IMMREG:v[0-9]+]], 0x80000000
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; SI-NOT: 0x80000000
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; SI: V_OR_B32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
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; SI: V_OR_B32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
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; SI: V_OR_B32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
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; SI: V_OR_B32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
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define void @fneg_fabs_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %in) {
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%fabs = call <4 x double> @llvm.fabs.v4f64(<4 x double> %in)
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%fsub = fsub <4 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>, %fabs
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@ -1,6 +1,28 @@
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; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
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; FUNC-LABEL: @fneg_fabs_fadd_f32
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; SI-NOT: AND
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; SI: V_SUB_F32_e64 {{v[0-9]+}}, {{s[0-9]+}}, |{{v[0-9]+}}|
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define void @fneg_fabs_fadd_f32(float addrspace(1)* %out, float %x, float %y) {
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%fabs = call float @llvm.fabs.f32(float %x)
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%fsub = fsub float -0.000000e+00, %fabs
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%fadd = fadd float %y, %fsub
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store float %fadd, float addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @fneg_fabs_fmul_f32
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; SI-NOT: AND
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; SI: V_MUL_F32_e64 {{v[0-9]+}}, {{s[0-9]+}}, -|{{v[0-9]+}}|
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; SI-NOT: AND
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define void @fneg_fabs_fmul_f32(float addrspace(1)* %out, float %x, float %y) {
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%fabs = call float @llvm.fabs.f32(float %x)
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%fsub = fsub float -0.000000e+00, %fabs
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%fmul = fmul float %y, %fsub
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store float %fmul, float addrspace(1)* %out, align 4
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ret void
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}
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; DAGCombiner will transform:
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; (fabs (f32 bitcast (i32 a))) => (f32 bitcast (and (i32 a), 0x7FFFFFFF))
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@ -11,7 +33,8 @@
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; R600: |PV.{{[XYZW]}}|
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; R600: -PV
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; SI: V_OR_B32
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; SI: V_MOV_B32_e32 [[IMMREG:v[0-9]+]], 0x80000000
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; SI: V_OR_B32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
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define void @fneg_fabs_free_f32(float addrspace(1)* %out, i32 %in) {
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%bc = bitcast i32 %in to float
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%fabs = call float @llvm.fabs.f32(float %bc)
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@ -25,7 +48,8 @@ define void @fneg_fabs_free_f32(float addrspace(1)* %out, i32 %in) {
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; R600: |PV.{{[XYZW]}}|
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; R600: -PV
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; SI: V_OR_B32
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; SI: V_MOV_B32_e32 [[IMMREG:v[0-9]+]], 0x80000000
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; SI: V_OR_B32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
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define void @fneg_fabs_fn_free_f32(float addrspace(1)* %out, i32 %in) {
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%bc = bitcast i32 %in to float
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%fabs = call float @fabs(float %bc)
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@ -34,14 +58,37 @@ define void @fneg_fabs_fn_free_f32(float addrspace(1)* %out, i32 %in) {
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ret void
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}
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; FUNC-LABEL: @fneg_fabs_f32
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; SI: V_MOV_B32_e32 [[IMMREG:v[0-9]+]], 0x80000000
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; SI: V_OR_B32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
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define void @fneg_fabs_f32(float addrspace(1)* %out, float %in) {
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%fabs = call float @llvm.fabs.f32(float %in)
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%fsub = fsub float -0.000000e+00, %fabs
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store float %fsub, float addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @v_fneg_fabs_f32
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; SI: V_OR_B32_e32 v{{[0-9]+}}, 0x80000000, v{{[0-9]+}}
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define void @v_fneg_fabs_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
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%val = load float addrspace(1)* %in, align 4
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%fabs = call float @llvm.fabs.f32(float %val)
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%fsub = fsub float -0.000000e+00, %fabs
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store float %fsub, float addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: @fneg_fabs_v2f32
|
||||
; R600: |{{(PV|T[0-9])\.[XYZW]}}|
|
||||
; R600: -PV
|
||||
; R600: |{{(PV|T[0-9])\.[XYZW]}}|
|
||||
; R600: -PV
|
||||
|
||||
; SI: V_OR_B32
|
||||
; SI: V_OR_B32
|
||||
; FIXME: SGPR should be used directly for first src operand.
|
||||
; SI: V_MOV_B32_e32 [[IMMREG:v[0-9]+]], 0x80000000
|
||||
; SI-NOT: 0x80000000
|
||||
; SI: V_OR_B32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[IMMREG]]
|
||||
; SI: V_OR_B32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[IMMREG]]
|
||||
define void @fneg_fabs_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %in) {
|
||||
%fabs = call <2 x float> @llvm.fabs.v2f32(<2 x float> %in)
|
||||
%fsub = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, %fabs
|
||||
@ -49,11 +96,14 @@ define void @fneg_fabs_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %in) {
|
||||
ret void
|
||||
}
|
||||
|
||||
; FIXME: SGPR should be used directly for first src operand.
|
||||
; FUNC-LABEL: @fneg_fabs_v4f32
|
||||
; SI: V_OR_B32
|
||||
; SI: V_OR_B32
|
||||
; SI: V_OR_B32
|
||||
; SI: V_OR_B32
|
||||
; SI: V_MOV_B32_e32 [[IMMREG:v[0-9]+]], 0x80000000
|
||||
; SI-NOT: 0x80000000
|
||||
; SI: V_OR_B32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[IMMREG]]
|
||||
; SI: V_OR_B32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[IMMREG]]
|
||||
; SI: V_OR_B32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[IMMREG]]
|
||||
; SI: V_OR_B32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[IMMREG]]
|
||||
define void @fneg_fabs_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %in) {
|
||||
%fabs = call <4 x float> @llvm.fabs.v4f32(<4 x float> %in)
|
||||
%fsub = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %fabs
|
||||
|
||||
@ -56,6 +56,32 @@ define void @vector_or_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %a, i32 %b)
|
||||
ret void
|
||||
}
|
||||
|
||||
; SI-LABEL: @scalar_or_literal_i32
|
||||
; SI: S_OR_B32 s0, s0, 0x1869f
|
||||
define void @scalar_or_literal_i32(i32 addrspace(1)* %out, i32 %a) {
|
||||
%or = or i32 %a, 99999
|
||||
store i32 %or, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; SI-LABEL: @vector_or_literal_i32
|
||||
; SI: V_OR_B32_e32 v{{[0-9]+}}, 0xffff, v{{[0-9]+}}
|
||||
define void @vector_or_literal_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %a, i32 addrspace(1)* %b) {
|
||||
%loada = load i32 addrspace(1)* %a, align 4
|
||||
%or = or i32 %loada, 65535
|
||||
store i32 %or, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; SI-LABEL: @vector_or_inline_immediate_i32
|
||||
; SI: V_OR_B32_e32 v{{[0-9]+}}, 4, v{{[0-9]+}}
|
||||
define void @vector_or_inline_immediate_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %a, i32 addrspace(1)* %b) {
|
||||
%loada = load i32 addrspace(1)* %a, align 4
|
||||
%or = or i32 %loada, 4
|
||||
store i32 %or, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; EG-LABEL: @scalar_or_i64
|
||||
; EG-DAG: OR_INT * T{{[0-9]\.[XYZW]}}, KC0[2].W, KC0[3].Y
|
||||
; EG-DAG: OR_INT * T{{[0-9]\.[XYZW]}}, KC0[3].X, KC0[3].Z
|
||||
|
||||
Loading…
Reference in New Issue
Block a user