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[PowerPC] Ignore implicit register operands for MCInst

Browse Source 
Summary:
When doing the conversion: MachineInst -> MCInst, we should ignore the
implicit operands, it will expose more opportunity for InstiAlias.

Reviewed By: steven.zhang

Differential Revision: https://reviews.llvm.org/D77118
This commit is contained in:
Kang Zhang 2020-04-16 16:22:43 +00:00
parent 47e57e2c48
commit bb10587376
91 changed files with 1990 additions and 1987 deletions
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3
lib/Target/PowerPC/PPCMCInstLower.cpp
View File

@ -147,6 +147,9 @@ bool llvm::LowerPPCMachineOperandToMCOperand(const MachineOperand &MO,
assert(MO.getReg() > PPC::NoRegister &&
MO.getReg() < PPC::NUM_TARGET_REGS &&
"Invalid register for this target!");
// Ignore all implicit register operands.
if (MO.isImplicit())
return false;
OutMO = MCOperand::createReg(MO.getReg());
return true;
case MachineOperand::MO_Immediate:

2
test/CodeGen/PowerPC/NoCRFieldRedefWhenSpillingCRBIT.mir
View File

@ -94,7 +94,7 @@ body: |
renamable $cr5lt = CRNOR renamable $cr0lt, renamable $cr1gt, implicit killed $cr0
renamable $cr5gt = COPY renamable $cr1gt, implicit $cr1
; CHECK: crnor 4*cr5+lt, lt, 4*cr1+gt
; CHECK: cror 4*cr5+gt, 4*cr1+gt, 4*cr1+gt
; CHECK: crmove 4*cr5+gt, 4*cr1+gt
SPILL_CRBIT killed renamable $cr5lt, 0, %stack.0 :: (store 4 into %stack.0)
renamable $cr1 = CMPW renamable $r4, renamable $r5, implicit killed $x5, implicit killed $x4
SPILL_CRBIT killed renamable $cr5gt, 0, %stack.1 :: (store 4 into %stack.1)

80
test/CodeGen/PowerPC/atomics-regression.ll
View File

@ -400,7 +400,7 @@ define void @test39() {
define void @test40(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test40:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: .LBB40_1:
; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
@ -419,7 +419,7 @@ define void @test40(i8* %ptr, i8 %cmp, i8 %val) {
define void @test41(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test41:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: .LBB41_1:
; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
@ -441,7 +441,7 @@ define void @test41(i8* %ptr, i8 %cmp, i8 %val) {
define void @test42(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test42:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: .LBB42_1:
; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
@ -463,7 +463,7 @@ define void @test42(i8* %ptr, i8 %cmp, i8 %val) {
define void @test43(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test43:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB43_1:
; PPC64LE-NEXT: lbarx 6, 0, 3
@ -483,7 +483,7 @@ define void @test43(i8* %ptr, i8 %cmp, i8 %val) {
define void @test44(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test44:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB44_1:
; PPC64LE-NEXT: lbarx 6, 0, 3
@ -503,7 +503,7 @@ define void @test44(i8* %ptr, i8 %cmp, i8 %val) {
define void @test45(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test45:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB45_1:
; PPC64LE-NEXT: lbarx 6, 0, 3
@ -526,7 +526,7 @@ define void @test45(i8* %ptr, i8 %cmp, i8 %val) {
define void @test46(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test46:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB46_1:
; PPC64LE-NEXT: lbarx 6, 0, 3
@ -549,7 +549,7 @@ define void @test46(i8* %ptr, i8 %cmp, i8 %val) {
define void @test47(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test47:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB47_1:
; PPC64LE-NEXT: lbarx 6, 0, 3
@ -572,7 +572,7 @@ define void @test47(i8* %ptr, i8 %cmp, i8 %val) {
define void @test48(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test48:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB48_1:
; PPC64LE-NEXT: lbarx 6, 0, 3
@ -595,7 +595,7 @@ define void @test48(i8* %ptr, i8 %cmp, i8 %val) {
define void @test49(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test49:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB49_1:
; PPC64LE-NEXT: lbarx 6, 0, 3
@ -618,7 +618,7 @@ define void @test49(i8* %ptr, i8 %cmp, i8 %val) {
define void @test50(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test50:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: .LBB50_1:
; PPC64LE-NEXT: lharx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
@ -637,7 +637,7 @@ define void @test50(i16* %ptr, i16 %cmp, i16 %val) {
define void @test51(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test51:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: .LBB51_1:
; PPC64LE-NEXT: lharx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
@ -659,7 +659,7 @@ define void @test51(i16* %ptr, i16 %cmp, i16 %val) {
define void @test52(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test52:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: .LBB52_1:
; PPC64LE-NEXT: lharx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
@ -681,7 +681,7 @@ define void @test52(i16* %ptr, i16 %cmp, i16 %val) {
define void @test53(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test53:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB53_1:
; PPC64LE-NEXT: lharx 6, 0, 3
@ -701,7 +701,7 @@ define void @test53(i16* %ptr, i16 %cmp, i16 %val) {
define void @test54(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test54:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB54_1:
; PPC64LE-NEXT: lharx 6, 0, 3
@ -721,7 +721,7 @@ define void @test54(i16* %ptr, i16 %cmp, i16 %val) {
define void @test55(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test55:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB55_1:
; PPC64LE-NEXT: lharx 6, 0, 3
@ -744,7 +744,7 @@ define void @test55(i16* %ptr, i16 %cmp, i16 %val) {
define void @test56(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test56:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB56_1:
; PPC64LE-NEXT: lharx 6, 0, 3
@ -767,7 +767,7 @@ define void @test56(i16* %ptr, i16 %cmp, i16 %val) {
define void @test57(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test57:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB57_1:
; PPC64LE-NEXT: lharx 6, 0, 3
@ -790,7 +790,7 @@ define void @test57(i16* %ptr, i16 %cmp, i16 %val) {
define void @test58(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test58:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB58_1:
; PPC64LE-NEXT: lharx 6, 0, 3
@ -813,7 +813,7 @@ define void @test58(i16* %ptr, i16 %cmp, i16 %val) {
define void @test59(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test59:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB59_1:
; PPC64LE-NEXT: lharx 6, 0, 3
@ -1252,7 +1252,7 @@ define void @test79(i64* %ptr, i64 %cmp, i64 %val) {
define void @test80(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test80:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: .LBB80_1:
; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
@ -1271,7 +1271,7 @@ define void @test80(i8* %ptr, i8 %cmp, i8 %val) {
define void @test81(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test81:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: .LBB81_1:
; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
@ -1293,7 +1293,7 @@ define void @test81(i8* %ptr, i8 %cmp, i8 %val) {
define void @test82(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test82:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: .LBB82_1:
; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
@ -1315,7 +1315,7 @@ define void @test82(i8* %ptr, i8 %cmp, i8 %val) {
define void @test83(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test83:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB83_1:
; PPC64LE-NEXT: lbarx 6, 0, 3
@ -1335,7 +1335,7 @@ define void @test83(i8* %ptr, i8 %cmp, i8 %val) {
define void @test84(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test84:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB84_1:
; PPC64LE-NEXT: lbarx 6, 0, 3
@ -1355,7 +1355,7 @@ define void @test84(i8* %ptr, i8 %cmp, i8 %val) {
define void @test85(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test85:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB85_1:
; PPC64LE-NEXT: lbarx 6, 0, 3
@ -1378,7 +1378,7 @@ define void @test85(i8* %ptr, i8 %cmp, i8 %val) {
define void @test86(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test86:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB86_1:
; PPC64LE-NEXT: lbarx 6, 0, 3
@ -1401,7 +1401,7 @@ define void @test86(i8* %ptr, i8 %cmp, i8 %val) {
define void @test87(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test87:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB87_1:
; PPC64LE-NEXT: lbarx 6, 0, 3
@ -1424,7 +1424,7 @@ define void @test87(i8* %ptr, i8 %cmp, i8 %val) {
define void @test88(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test88:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB88_1:
; PPC64LE-NEXT: lbarx 6, 0, 3
@ -1447,7 +1447,7 @@ define void @test88(i8* %ptr, i8 %cmp, i8 %val) {
define void @test89(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test89:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB89_1:
; PPC64LE-NEXT: lbarx 6, 0, 3
@ -1470,7 +1470,7 @@ define void @test89(i8* %ptr, i8 %cmp, i8 %val) {
define void @test90(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test90:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: .LBB90_1:
; PPC64LE-NEXT: lharx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
@ -1489,7 +1489,7 @@ define void @test90(i16* %ptr, i16 %cmp, i16 %val) {
define void @test91(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test91:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: .LBB91_1:
; PPC64LE-NEXT: lharx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
@ -1511,7 +1511,7 @@ define void @test91(i16* %ptr, i16 %cmp, i16 %val) {
define void @test92(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test92:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: .LBB92_1:
; PPC64LE-NEXT: lharx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6
@ -1533,7 +1533,7 @@ define void @test92(i16* %ptr, i16 %cmp, i16 %val) {
define void @test93(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test93:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB93_1:
; PPC64LE-NEXT: lharx 6, 0, 3
@ -1553,7 +1553,7 @@ define void @test93(i16* %ptr, i16 %cmp, i16 %val) {
define void @test94(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test94:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB94_1:
; PPC64LE-NEXT: lharx 6, 0, 3
@ -1573,7 +1573,7 @@ define void @test94(i16* %ptr, i16 %cmp, i16 %val) {
define void @test95(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test95:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB95_1:
; PPC64LE-NEXT: lharx 6, 0, 3
@ -1596,7 +1596,7 @@ define void @test95(i16* %ptr, i16 %cmp, i16 %val) {
define void @test96(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test96:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB96_1:
; PPC64LE-NEXT: lharx 6, 0, 3
@ -1619,7 +1619,7 @@ define void @test96(i16* %ptr, i16 %cmp, i16 %val) {
define void @test97(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test97:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB97_1:
; PPC64LE-NEXT: lharx 6, 0, 3
@ -1642,7 +1642,7 @@ define void @test97(i16* %ptr, i16 %cmp, i16 %val) {
define void @test98(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test98:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB98_1:
; PPC64LE-NEXT: lharx 6, 0, 3
@ -1665,7 +1665,7 @@ define void @test98(i16* %ptr, i16 %cmp, i16 %val) {
define void @test99(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test99:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB99_1:
; PPC64LE-NEXT: lharx 6, 0, 3

8
test/CodeGen/PowerPC/bitcasts-direct-move.ll
View File

@ -11,7 +11,7 @@ entry:
; CHECK-P7: lwa 3,
; CHECK: xscvdpspn [[CONVREG:[0-9]+]], 1
; CHECK: xxsldwi [[SHIFTREG:[0-9]+]], [[CONVREG]], [[CONVREG]], 3
; CHECK: mfvsrwz 3, [[SHIFTREG]]
; CHECK: mffprwz 3, [[SHIFTREG]]
}
define i64 @f64toi64(double %a) {
@ -29,7 +29,7 @@ entry:
ret float %0
; CHECK-P7: stw 3,
; CHECK-P7: lfs 1,
; CHECK: mtvsrd [[MOVEREG:[0-9]+]], 3
; CHECK: mtfprd [[MOVEREG:[0-9]+]], 3
; CHECK: xxsldwi [[SHIFTREG:[0-9]+]], [[MOVEREG]], [[MOVEREG]], 1
; CHECK: xscvspdpn 1, [[SHIFTREG]]
}
@ -51,7 +51,7 @@ entry:
; CHECK-P7: lwz 3,
; CHECK: xscvdpspn [[CONVREG:[0-9]+]], 1
; CHECK: xxsldwi [[SHIFTREG:[0-9]+]], [[CONVREG]], [[CONVREG]], 3
; CHECK: mfvsrwz 3, [[SHIFTREG]]
; CHECK: mffprwz 3, [[SHIFTREG]]
}
define i64 @f64toi64u(double %a) {
@ -69,7 +69,7 @@ entry:
ret float %0
; CHECK-P7: stw 3,
; CHECK-P7: lfs 1,
; CHECK: mtvsrd [[MOVEREG:[0-9]+]], 3
; CHECK: mtfprd [[MOVEREG:[0-9]+]], 3
; CHECK: xxsldwi [[SHIFTREG:[0-9]+]], [[MOVEREG]], [[MOVEREG]], 1
; CHECK: xscvspdpn 1, [[SHIFTREG]]
}

6
test/CodeGen/PowerPC/bool-math.ll
View File

@ -44,7 +44,7 @@ define i8 @sub_zext_cmp_mask_narrower_result(i32 %x) {
define i8 @add_zext_cmp_mask_same_size_result(i8 %x) {
; CHECK-LABEL: add_zext_cmp_mask_same_size_result:
; CHECK: # %bb.0:
; CHECK-NEXT: rlwinm 3, 3, 0, 31, 31
; CHECK-NEXT: clrlwi 3, 3, 31
; CHECK-NEXT: subfic 3, 3, 27
; CHECK-NEXT: blr
%a = and i8 %x, 1
@ -57,7 +57,7 @@ define i8 @add_zext_cmp_mask_same_size_result(i8 %x) {
define i32 @add_zext_cmp_mask_wider_result(i8 %x) {
; CHECK-LABEL: add_zext_cmp_mask_wider_result:
; CHECK: # %bb.0:
; CHECK-NEXT: rlwinm 3, 3, 0, 31, 31
; CHECK-NEXT: clrlwi 3, 3, 31
; CHECK-NEXT: subfic 3, 3, 27
; CHECK-NEXT: blr
%a = and i8 %x, 1
@ -70,7 +70,7 @@ define i32 @add_zext_cmp_mask_wider_result(i8 %x) {
define i8 @add_zext_cmp_mask_narrower_result(i32 %x) {
; CHECK-LABEL: add_zext_cmp_mask_narrower_result:
; CHECK: # %bb.0:
; CHECK-NEXT: rlwinm 3, 3, 0, 31, 31
; CHECK-NEXT: clrlwi 3, 3, 31
; CHECK-NEXT: subfic 3, 3, 43
; CHECK-NEXT: blr
%a = and i32 %x, 1

6
test/CodeGen/PowerPC/branch_coalesce.ll
View File

@ -7,8 +7,8 @@
define double @testBranchCoal(double %a, double %b, double %c, i32 %x) {
; CHECK-LABEL: @testBranchCoal
; CHECK: cmplwi [[CMPR:[0-7]+]], 6, 0
; CHECK: beq [[CMPR]], .LBB[[LAB1:[0-9_]+]]
; CHECK: cmplwi 6, 0
; CHECK: beq 0, .LBB[[LAB1:[0-9_]+]]
; CHECK-DAG: addis [[LD1REG:[0-9]+]], 2, .LCPI0_0@toc@ha
; CHECK-DAG: addis [[LD2REG:[0-9]+]], 2, .LCPI0_1@toc@ha
; CHECK-DAG: xxlxor 2, 2, 2
@ -22,7 +22,7 @@ define double @testBranchCoal(double %a, double %b, double %c, i32 %x) {
; CHECK-NOCOALESCE-LABEL: testBranchCoal:
; CHECK-NOCOALESCE: # %bb.0: # %entry
; CHECK-NOCOALESCE-NEXT: cmplwi 0, 6, 0
; CHECK-NOCOALESCE-NEXT: cmplwi 6, 0
; CHECK-NOCOALESCE-NEXT: bne 0, .LBB0_5
; CHECK-NOCOALESCE-NEXT: # %bb.1: # %entry
; CHECK-NOCOALESCE-NEXT: bne 0, .LBB0_6

2
test/CodeGen/PowerPC/bswap64.ll
View File

@ -11,7 +11,7 @@ define i64 @bswap64(i64 %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mtvsrdd 34, 3, 3
; CHECK-NEXT: xxbrd 0, 34
; CHECK-NEXT: mfvsrd 3, 0
; CHECK-NEXT: mffprd 3, 0
; CHECK-NEXT: blr
;
; NO-ALTIVEC-LABEL: bswap64:

112
test/CodeGen/PowerPC/build-vector-tests.ll
View File

@ -832,8 +832,8 @@ define <4 x i32> @fromRegsi(i32 signext %a, i32 signext %b, i32 signext %c, i32
; P8BE: # %bb.0: # %entry
; P8BE-NEXT: rldimi r6, r5, 32, 0
; P8BE-NEXT: rldimi r4, r3, 32, 0
; P8BE-NEXT: mtvsrd f0, r6
; P8BE-NEXT: mtvsrd f1, r4
; P8BE-NEXT: mtfprd f0, r6
; P8BE-NEXT: mtfprd f1, r4
; P8BE-NEXT: xxmrghd v2, vs1, vs0
; P8BE-NEXT: blr
;
@ -841,8 +841,8 @@ define <4 x i32> @fromRegsi(i32 signext %a, i32 signext %b, i32 signext %c, i32
; P8LE: # %bb.0: # %entry
; P8LE-NEXT: rldimi r3, r4, 32, 0
; P8LE-NEXT: rldimi r5, r6, 32, 0
; P8LE-NEXT: mtvsrd f0, r3
; P8LE-NEXT: mtvsrd f1, r5
; P8LE-NEXT: mtfprd f0, r3
; P8LE-NEXT: mtfprd f1, r5
; P8LE-NEXT: xxmrghd v2, vs1, vs0
; P8LE-NEXT: blr
entry:
@ -1120,8 +1120,8 @@ define <4 x i32> @fromRandMemConsi(i32* nocapture readonly %arr) {
; P8BE-NEXT: lwz r3, 72(r3)
; P8BE-NEXT: rldimi r5, r4, 32, 0
; P8BE-NEXT: rldimi r3, r6, 32, 0
; P8BE-NEXT: mtvsrd f0, r5
; P8BE-NEXT: mtvsrd f1, r3
; P8BE-NEXT: mtfprd f0, r5
; P8BE-NEXT: mtfprd f1, r3
; P8BE-NEXT: xxmrghd v2, vs1, vs0
; P8BE-NEXT: blr
;
@ -1133,8 +1133,8 @@ define <4 x i32> @fromRandMemConsi(i32* nocapture readonly %arr) {
; P8LE-NEXT: lwz r3, 352(r3)
; P8LE-NEXT: rldimi r4, r5, 32, 0
; P8LE-NEXT: rldimi r6, r3, 32, 0
; P8LE-NEXT: mtvsrd f0, r4
; P8LE-NEXT: mtvsrd f1, r6
; P8LE-NEXT: mtfprd f0, r4
; P8LE-NEXT: mtfprd f1, r6
; P8LE-NEXT: xxmrghd v2, vs1, vs0
; P8LE-NEXT: blr
entry:
@ -1190,8 +1190,8 @@ define <4 x i32> @fromRandMemVari(i32* nocapture readonly %arr, i32 signext %ele
; P8BE-NEXT: lwz r3, 4(r3)
; P8BE-NEXT: rldimi r5, r4, 32, 0
; P8BE-NEXT: rldimi r3, r6, 32, 0
; P8BE-NEXT: mtvsrd f0, r5
; P8BE-NEXT: mtvsrd f1, r3
; P8BE-NEXT: mtfprd f0, r5
; P8BE-NEXT: mtfprd f1, r3
; P8BE-NEXT: xxmrghd v2, vs1, vs0
; P8BE-NEXT: blr
;
@ -1205,8 +1205,8 @@ define <4 x i32> @fromRandMemVari(i32* nocapture readonly %arr, i32 signext %ele
; P8LE-NEXT: lwz r3, 32(r3)
; P8LE-NEXT: rldimi r4, r5, 32, 0
; P8LE-NEXT: rldimi r6, r3, 32, 0
; P8LE-NEXT: mtvsrd f0, r4
; P8LE-NEXT: mtvsrd f1, r6
; P8LE-NEXT: mtfprd f0, r4
; P8LE-NEXT: mtfprd f1, r6
; P8LE-NEXT: xxmrghd v2, vs1, vs0
; P8LE-NEXT: blr
entry:
@ -1246,13 +1246,13 @@ define <4 x i32> @spltRegVali(i32 signext %val) {
;
; P8BE-LABEL: spltRegVali:
; P8BE: # %bb.0: # %entry
; P8BE-NEXT: mtvsrwz f0, r3
; P8BE-NEXT: mtfprwz f0, r3
; P8BE-NEXT: xxspltw v2, vs0, 1
; P8BE-NEXT: blr
;
; P8LE-LABEL: spltRegVali:
; P8LE: # %bb.0: # %entry
; P8LE-NEXT: mtvsrwz f0, r3
; P8LE-NEXT: mtfprwz f0, r3
; P8LE-NEXT: xxspltw v2, vs0, 1
; P8LE-NEXT: blr
entry:
@ -2351,8 +2351,8 @@ define <4 x i32> @fromRegsui(i32 zeroext %a, i32 zeroext %b, i32 zeroext %c, i32
; P8BE: # %bb.0: # %entry
; P8BE-NEXT: rldimi r6, r5, 32, 0
; P8BE-NEXT: rldimi r4, r3, 32, 0
; P8BE-NEXT: mtvsrd f0, r6
; P8BE-NEXT: mtvsrd f1, r4
; P8BE-NEXT: mtfprd f0, r6
; P8BE-NEXT: mtfprd f1, r4
; P8BE-NEXT: xxmrghd v2, vs1, vs0
; P8BE-NEXT: blr
;
@ -2360,8 +2360,8 @@ define <4 x i32> @fromRegsui(i32 zeroext %a, i32 zeroext %b, i32 zeroext %c, i32
; P8LE: # %bb.0: # %entry
; P8LE-NEXT: rldimi r3, r4, 32, 0
; P8LE-NEXT: rldimi r5, r6, 32, 0
; P8LE-NEXT: mtvsrd f0, r3
; P8LE-NEXT: mtvsrd f1, r5
; P8LE-NEXT: mtfprd f0, r3
; P8LE-NEXT: mtfprd f1, r5
; P8LE-NEXT: xxmrghd v2, vs1, vs0
; P8LE-NEXT: blr
entry:
@ -2639,8 +2639,8 @@ define <4 x i32> @fromRandMemConsui(i32* nocapture readonly %arr) {
; P8BE-NEXT: lwz r3, 72(r3)
; P8BE-NEXT: rldimi r5, r4, 32, 0
; P8BE-NEXT: rldimi r3, r6, 32, 0
; P8BE-NEXT: mtvsrd f0, r5
; P8BE-NEXT: mtvsrd f1, r3
; P8BE-NEXT: mtfprd f0, r5
; P8BE-NEXT: mtfprd f1, r3
; P8BE-NEXT: xxmrghd v2, vs1, vs0
; P8BE-NEXT: blr
;
@ -2652,8 +2652,8 @@ define <4 x i32> @fromRandMemConsui(i32* nocapture readonly %arr) {
; P8LE-NEXT: lwz r3, 352(r3)
; P8LE-NEXT: rldimi r4, r5, 32, 0
; P8LE-NEXT: rldimi r6, r3, 32, 0
; P8LE-NEXT: mtvsrd f0, r4
; P8LE-NEXT: mtvsrd f1, r6
; P8LE-NEXT: mtfprd f0, r4
; P8LE-NEXT: mtfprd f1, r6
; P8LE-NEXT: xxmrghd v2, vs1, vs0
; P8LE-NEXT: blr
entry:
@ -2709,8 +2709,8 @@ define <4 x i32> @fromRandMemVarui(i32* nocapture readonly %arr, i32 signext %el
; P8BE-NEXT: lwz r3, 4(r3)
; P8BE-NEXT: rldimi r5, r4, 32, 0
; P8BE-NEXT: rldimi r3, r6, 32, 0
; P8BE-NEXT: mtvsrd f0, r5
; P8BE-NEXT: mtvsrd f1, r3
; P8BE-NEXT: mtfprd f0, r5
; P8BE-NEXT: mtfprd f1, r3
; P8BE-NEXT: xxmrghd v2, vs1, vs0
; P8BE-NEXT: blr
;
@ -2724,8 +2724,8 @@ define <4 x i32> @fromRandMemVarui(i32* nocapture readonly %arr, i32 signext %el
; P8LE-NEXT: lwz r3, 32(r3)
; P8LE-NEXT: rldimi r4, r5, 32, 0
; P8LE-NEXT: rldimi r6, r3, 32, 0
; P8LE-NEXT: mtvsrd f0, r4
; P8LE-NEXT: mtvsrd f1, r6
; P8LE-NEXT: mtfprd f0, r4
; P8LE-NEXT: mtfprd f1, r6
; P8LE-NEXT: xxmrghd v2, vs1, vs0
; P8LE-NEXT: blr
entry:
@ -2765,13 +2765,13 @@ define <4 x i32> @spltRegValui(i32 zeroext %val) {
;
; P8BE-LABEL: spltRegValui:
; P8BE: # %bb.0: # %entry
; P8BE-NEXT: mtvsrwz f0, r3
; P8BE-NEXT: mtfprwz f0, r3
; P8BE-NEXT: xxspltw v2, vs0, 1
; P8BE-NEXT: blr
;
; P8LE-LABEL: spltRegValui:
; P8LE: # %bb.0: # %entry
; P8LE-NEXT: mtvsrwz f0, r3
; P8LE-NEXT: mtfprwz f0, r3
; P8LE-NEXT: xxspltw v2, vs0, 1
; P8LE-NEXT: blr
entry:
@ -3884,15 +3884,15 @@ define <2 x i64> @fromRegsll(i64 %a, i64 %b) {
;
; P8BE-LABEL: fromRegsll:
; P8BE: # %bb.0: # %entry
; P8BE-NEXT: mtvsrd f0, r4
; P8BE-NEXT: mtvsrd f1, r3
; P8BE-NEXT: mtfprd f0, r4
; P8BE-NEXT: mtfprd f1, r3
; P8BE-NEXT: xxmrghd v2, vs1, vs0
; P8BE-NEXT: blr
;
; P8LE-LABEL: fromRegsll:
; P8LE: # %bb.0: # %entry
; P8LE-NEXT: mtvsrd f0, r3
; P8LE-NEXT: mtvsrd f1, r4
; P8LE-NEXT: mtfprd f0, r3
; P8LE-NEXT: mtfprd f1, r4
; P8LE-NEXT: xxmrghd v2, vs1, vs0
; P8LE-NEXT: blr
entry:
@ -4103,8 +4103,8 @@ define <2 x i64> @fromRandMemConsll(i64* nocapture readonly %arr) {
; P8BE: # %bb.0: # %entry
; P8BE-NEXT: ld r4, 144(r3)
; P8BE-NEXT: ld r3, 32(r3)
; P8BE-NEXT: mtvsrd f0, r4
; P8BE-NEXT: mtvsrd f1, r3
; P8BE-NEXT: mtfprd f0, r4
; P8BE-NEXT: mtfprd f1, r3
; P8BE-NEXT: xxmrghd v2, vs1, vs0
; P8BE-NEXT: blr
;
@ -4112,8 +4112,8 @@ define <2 x i64> @fromRandMemConsll(i64* nocapture readonly %arr) {
; P8LE: # %bb.0: # %entry
; P8LE-NEXT: ld r4, 32(r3)
; P8LE-NEXT: ld r3, 144(r3)
; P8LE-NEXT: mtvsrd f0, r4
; P8LE-NEXT: mtvsrd f1, r3
; P8LE-NEXT: mtfprd f0, r4
; P8LE-NEXT: mtfprd f1, r3
; P8LE-NEXT: xxmrghd v2, vs1, vs0
; P8LE-NEXT: blr
entry:
@ -4151,8 +4151,8 @@ define <2 x i64> @fromRandMemVarll(i64* nocapture readonly %arr, i32 signext %el
; P8BE-NEXT: add r3, r3, r4
; P8BE-NEXT: ld r4, 8(r3)
; P8BE-NEXT: ld r3, 32(r3)
; P8BE-NEXT: mtvsrd f0, r4
; P8BE-NEXT: mtvsrd f1, r3
; P8BE-NEXT: mtfprd f0, r4
; P8BE-NEXT: mtfprd f1, r3
; P8BE-NEXT: xxmrghd v2, vs1, vs0
; P8BE-NEXT: blr
;
@ -4162,8 +4162,8 @@ define <2 x i64> @fromRandMemVarll(i64* nocapture readonly %arr, i32 signext %el
; P8LE-NEXT: add r3, r3, r4
; P8LE-NEXT: ld r4, 32(r3)
; P8LE-NEXT: ld r3, 8(r3)
; P8LE-NEXT: mtvsrd f0, r4
; P8LE-NEXT: mtvsrd f1, r3
; P8LE-NEXT: mtfprd f0, r4
; P8LE-NEXT: mtfprd f1, r3
; P8LE-NEXT: xxmrghd v2, vs1, vs0
; P8LE-NEXT: blr
entry:
@ -4193,13 +4193,13 @@ define <2 x i64> @spltRegValll(i64 %val) {
;
; P8BE-LABEL: spltRegValll:
; P8BE: # %bb.0: # %entry
; P8BE-NEXT: mtvsrd f0, r3
; P8BE-NEXT: mtfprd f0, r3
; P8BE-NEXT: xxspltd v2, vs0, 0
; P8BE-NEXT: blr
;
; P8LE-LABEL: spltRegValll:
; P8LE: # %bb.0: # %entry
; P8LE-NEXT: mtvsrd f0, r3
; P8LE-NEXT: mtfprd f0, r3
; P8LE-NEXT: xxspltd v2, vs0, 0
; P8LE-NEXT: blr
entry:
@ -5072,15 +5072,15 @@ define <2 x i64> @fromRegsull(i64 %a, i64 %b) {
;
; P8BE-LABEL: fromRegsull:
; P8BE: # %bb.0: # %entry
; P8BE-NEXT: mtvsrd f0, r4
; P8BE-NEXT: mtvsrd f1, r3
; P8BE-NEXT: mtfprd f0, r4
; P8BE-NEXT: mtfprd f1, r3
; P8BE-NEXT: xxmrghd v2, vs1, vs0
; P8BE-NEXT: blr
;
; P8LE-LABEL: fromRegsull:
; P8LE: # %bb.0: # %entry
; P8LE-NEXT: mtvsrd f0, r3
; P8LE-NEXT: mtvsrd f1, r4
; P8LE-NEXT: mtfprd f0, r3
; P8LE-NEXT: mtfprd f1, r4
; P8LE-NEXT: xxmrghd v2, vs1, vs0
; P8LE-NEXT: blr
entry:
@ -5291,8 +5291,8 @@ define <2 x i64> @fromRandMemConsull(i64* nocapture readonly %arr) {
; P8BE: # %bb.0: # %entry
; P8BE-NEXT: ld r4, 144(r3)
; P8BE-NEXT: ld r3, 32(r3)
; P8BE-NEXT: mtvsrd f0, r4
; P8BE-NEXT: mtvsrd f1, r3
; P8BE-NEXT: mtfprd f0, r4
; P8BE-NEXT: mtfprd f1, r3
; P8BE-NEXT: xxmrghd v2, vs1, vs0
; P8BE-NEXT: blr
;
@ -5300,8 +5300,8 @@ define <2 x i64> @fromRandMemConsull(i64* nocapture readonly %arr) {
; P8LE: # %bb.0: # %entry
; P8LE-NEXT: ld r4, 32(r3)
; P8LE-NEXT: ld r3, 144(r3)
; P8LE-NEXT: mtvsrd f0, r4
; P8LE-NEXT: mtvsrd f1, r3
; P8LE-NEXT: mtfprd f0, r4
; P8LE-NEXT: mtfprd f1, r3
; P8LE-NEXT: xxmrghd v2, vs1, vs0
; P8LE-NEXT: blr
entry:
@ -5339,8 +5339,8 @@ define <2 x i64> @fromRandMemVarull(i64* nocapture readonly %arr, i32 signext %e
; P8BE-NEXT: add r3, r3, r4
; P8BE-NEXT: ld r4, 8(r3)
; P8BE-NEXT: ld r3, 32(r3)
; P8BE-NEXT: mtvsrd f0, r4
; P8BE-NEXT: mtvsrd f1, r3
; P8BE-NEXT: mtfprd f0, r4
; P8BE-NEXT: mtfprd f1, r3
; P8BE-NEXT: xxmrghd v2, vs1, vs0
; P8BE-NEXT: blr
;
@ -5350,8 +5350,8 @@ define <2 x i64> @fromRandMemVarull(i64* nocapture readonly %arr, i32 signext %e
; P8LE-NEXT: add r3, r3, r4
; P8LE-NEXT: ld r4, 32(r3)
; P8LE-NEXT: ld r3, 8(r3)
; P8LE-NEXT: mtvsrd f0, r4
; P8LE-NEXT: mtvsrd f1, r3
; P8LE-NEXT: mtfprd f0, r4
; P8LE-NEXT: mtfprd f1, r3
; P8LE-NEXT: xxmrghd v2, vs1, vs0
; P8LE-NEXT: blr
entry:
@ -5381,13 +5381,13 @@ define <2 x i64> @spltRegValull(i64 %val) {
;
; P8BE-LABEL: spltRegValull:
; P8BE: # %bb.0: # %entry
; P8BE-NEXT: mtvsrd f0, r3
; P8BE-NEXT: mtfprd f0, r3
; P8BE-NEXT: xxspltd v2, vs0, 0
; P8BE-NEXT: blr
;
; P8LE-LABEL: spltRegValull:
; P8LE: # %bb.0: # %entry
; P8LE-NEXT: mtvsrd f0, r3
; P8LE-NEXT: mtfprd f0, r3
; P8LE-NEXT: xxspltd v2, vs0, 0
; P8LE-NEXT: blr
entry:

2
test/CodeGen/PowerPC/canonical-merge-shuffles.ll
View File

@ -217,7 +217,7 @@ define dso_local <8 x i16> @testmrglb3(<8 x i8>* nocapture readonly %a) local_un
; CHECK-P8-NEXT: ld r3, 0(r3)
; CHECK-P8-NEXT: addis r4, r2, .LCPI12_0@toc@ha
; CHECK-P8-NEXT: xxlxor v4, v4, v4
; CHECK-P8-NEXT: mtvsrd f0, r3
; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: addi r3, r4, .LCPI12_0@toc@l
; CHECK-P8-NEXT: lvx v3, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0

2
test/CodeGen/PowerPC/convert-rr-to-ri-instrs-out-of-range.mir
View File

@ -891,7 +891,7 @@ body: |
%3 = LI -37
%4 = RLDCL_rec %0, killed %3, 0, implicit-def $cr0
; CHECK: RLDICL_rec %0, 27, 0, implicit-def $cr0
; CHECK-LATE: rldicl. 5, 3, 27, 0
; CHECK-LATE: rotldi. 5, 3, 27
%5 = COPY killed $cr0
%6 = ISEL8 %2, %0, %5.sub_eq
$x3 = COPY %6

2
test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir
View File

@ -3728,7 +3728,7 @@ body: |
%3 = LI 37
%4 = RLDCL_rec %0, killed %3, 0, implicit-def $cr0
; CHECK: RLDICL_rec %0, 37, 0, implicit-def $cr0
; CHECK-LATE: rldicl. 5, 3, 37, 0
; CHECK-LATE: rotldi. 5, 3, 37
%5 = COPY killed $cr0
%6 = ISEL8 %2, %0, %5.sub_eq
$x3 = COPY %6

2
test/CodeGen/PowerPC/crbits.ll
View File

@ -145,7 +145,7 @@ entry:
ret i32 %cond
; CHECK-LABEL: @exttest7
; CHECK-DAG: cmpwi {{[0-9]+}}, 3, 5
; CHECK-DAG: cmpwi 3, 5
; CHECK-DAG: li [[REG1:[0-9]+]], 8
; CHECK-DAG: li [[REG2:[0-9]+]], 7
; CHECK: isel 3, [[REG2]], [[REG1]],

2
test/CodeGen/PowerPC/dform-adjust.ll
View File

@ -19,7 +19,7 @@ define dso_local i64 @test1(i8* nocapture readonly %p, i32 signext %count) local
; CHECK-NEXT: ldx 3, 3, 8
; CHECK-NEXT: mffprd 8, 0
; CHECK-NEXT: mfvsrld 10, 1
; CHECK-NEXT: mfvsrd 11, 1
; CHECK-NEXT: mffprd 11, 1
; CHECK-NEXT: mulld 8, 9, 8
; CHECK-NEXT: mulld 5, 8, 5
; CHECK-NEXT: mulld 5, 5, 10

8
test/CodeGen/PowerPC/expand-isel.ll
View File

@ -11,7 +11,7 @@ entry:
; CHECK-LABEL: @testExpandISELToIfElse
; CHECK: addi r5, r3, 1
; CHECK-NEXT: cmpwi cr0, r3, 0
; CHECK-NEXT: cmpwi r3, 0
; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]]
; CHECK: ori r3, r4, 0
; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
@ -101,7 +101,7 @@ entry:
ret i32 %add
; CHECK-LABEL: @testExpandISELsTo2ORIs1ADDI
; CHECK: cmpwi cr0, r7, 0
; CHECK: cmpwi r7, 0
; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]]
; CHECK: ori r3, r4, 0
; CHECK-NEXT: ori r4, r6, 0
@ -127,7 +127,7 @@ entry:
ret i32 %add2
; CHECK-LABEL: @testExpandISELsTo1ORI1ADDI
; CHECK: cmpwi cr0, r7, 0
; CHECK: cmpwi r7, 0
; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]]
; CHECK: ori r5, r6, 0
; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
@ -154,7 +154,7 @@ entry:
ret i32 %sub1
; CHECK-LABEL: @testExpandISELsTo0ORI2ADDIs
; CHECK: cmpwi cr0, r7, 0
; CHECK: cmpwi r7, 0
; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]]
; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
; CHECK-NEXT: [[TRUE]]

8
test/CodeGen/PowerPC/extract-and-store.ll
View File

@ -645,7 +645,7 @@ define void @test_5_consecutive_stores_of_bytes(<16 x i8> %a, i8* nocapture %b)
; CHECK-NEXT: mfvsrd r3, vs34
; CHECK-NEXT: rldicl r6, r3, 32, 56
; CHECK-NEXT: rldicl r3, r3, 56, 56
; CHECK-NEXT: mfvsrd r4, f0
; CHECK-NEXT: mffprd r4, f0
; CHECK-NEXT: stb r6, 1(r5)
; CHECK-NEXT: stb r3, 2(r5)
; CHECK-NEXT: rldicl r6, r4, 32, 56
@ -661,7 +661,7 @@ define void @test_5_consecutive_stores_of_bytes(<16 x i8> %a, i8* nocapture %b)
; CHECK-BE-NEXT: xxswapd vs0, vs34
; CHECK-BE-NEXT: mfvsrd r3, vs34
; CHECK-BE-NEXT: rldicl r6, r3, 40, 56
; CHECK-BE-NEXT: mfvsrd r4, f0
; CHECK-BE-NEXT: mffprd r4, f0
; CHECK-BE-NEXT: stb r6, 0(r5)
; CHECK-BE-NEXT: rldicl r6, r4, 40, 56
; CHECK-BE-NEXT: rldicl r4, r4, 16, 56
@ -734,7 +734,7 @@ define void @test_13_consecutive_stores_of_bytes(<16 x i8> %a, i8* nocapture %b)
; CHECK-NEXT: rldicl r6, r3, 56, 56
; CHECK-NEXT: stb r4, 1(r5)
; CHECK-NEXT: rldicl r4, r3, 40, 56
; CHECK-NEXT: mfvsrd r7, f0
; CHECK-NEXT: mffprd r7, f0
; CHECK-NEXT: stb r6, 2(r5)
; CHECK-NEXT: rldicl r6, r3, 24, 56
; CHECK-NEXT: stb r4, 6(r5)
@ -767,7 +767,7 @@ define void @test_13_consecutive_stores_of_bytes(<16 x i8> %a, i8* nocapture %b)
; CHECK-BE-NEXT: clrldi r6, r3, 56
; CHECK-BE-NEXT: stb r4, 0(r5)
; CHECK-BE-NEXT: rldicl r4, r3, 56, 56
; CHECK-BE-NEXT: mfvsrd r7, f0
; CHECK-BE-NEXT: mffprd r7, f0
; CHECK-BE-NEXT: stb r6, 3(r5)
; CHECK-BE-NEXT: rldicl r6, r3, 8, 56
; CHECK-BE-NEXT: stb r4, 4(r5)

2
test/CodeGen/PowerPC/f128-aggregates.ll
View File

@ -343,7 +343,7 @@ define fp128 @sum_float128(i32 signext %count, ...) {
; CHECK-DAG: std r7, 64(r1)
; CHECK-DAG: std r6, 56(r1)
; CHECK-DAG: std r4, 40(r1)
; CHECK-DAG: cmpwi cr0, r3, 1
; CHECK-DAG: cmpwi r3, 1
; CHECK-DAG: std r5, 48(r1)
; CHECK-DAG: addis [[REG:r[0-9]+]], r2, .LCPI17_0@toc@ha
; CHECK-DAG: addi [[REG1:r[0-9]+]], [[REG]], .LCPI17_0@toc@l

16
test/CodeGen/PowerPC/fp-int-conversions-direct-moves.ll
View File

@ -10,7 +10,7 @@ define zeroext i8 @_Z6testcff(float %arg) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xscvdpsxws f0, f1
; CHECK-NEXT: stfs f1, -4(r1)
; CHECK-NEXT: mfvsrwz r3, f0
; CHECK-NEXT: mffprwz r3, f0
; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
@ -43,7 +43,7 @@ define zeroext i8 @_Z6testcdd(double %arg) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xscvdpsxws f0, f1
; CHECK-NEXT: stfd f1, -8(r1)
; CHECK-NEXT: mfvsrwz r3, f0
; CHECK-NEXT: mffprwz r3, f0
; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
@ -76,7 +76,7 @@ define zeroext i8 @_Z7testucff(float %arg) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xscvdpsxws f0, f1
; CHECK-NEXT: stfs f1, -4(r1)
; CHECK-NEXT: mfvsrwz r3, f0
; CHECK-NEXT: mffprwz r3, f0
; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
@ -109,7 +109,7 @@ define zeroext i8 @_Z7testucdd(double %arg) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xscvdpsxws f0, f1
; CHECK-NEXT: stfd f1, -8(r1)
; CHECK-NEXT: mfvsrwz r3, f0
; CHECK-NEXT: mffprwz r3, f0
; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
@ -208,7 +208,7 @@ define zeroext i16 @_Z7testusff(float %arg) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xscvdpsxws f0, f1
; CHECK-NEXT: stfs f1, -4(r1)
; CHECK-NEXT: mfvsrwz r3, f0
; CHECK-NEXT: mffprwz r3, f0
; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
@ -241,7 +241,7 @@ define zeroext i16 @_Z7testusdd(double %arg) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xscvdpsxws f0, f1
; CHECK-NEXT: stfd f1, -8(r1)
; CHECK-NEXT: mfvsrwz r3, f0
; CHECK-NEXT: mffprwz r3, f0
; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
@ -340,7 +340,7 @@ define zeroext i32 @_Z7testuiff(float %arg) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xscvdpuxws f0, f1
; CHECK-NEXT: stfs f1, -4(r1)
; CHECK-NEXT: mfvsrwz r3, f0
; CHECK-NEXT: mffprwz r3, f0
; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
@ -373,7 +373,7 @@ define zeroext i32 @_Z7testuidd(double %arg) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xscvdpuxws f0, f1
; CHECK-NEXT: stfd f1, -8(r1)
; CHECK-NEXT: mfvsrwz r3, f0
; CHECK-NEXT: mffprwz r3, f0
; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:

18
test/CodeGen/PowerPC/funnel-shift-rot.ll
View File

@ -18,7 +18,7 @@ declare <4 x i32> @llvm.fshr.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
define i8 @rotl_i8_const_shift(i8 %x) {
; CHECK-LABEL: rotl_i8_const_shift:
; CHECK: # %bb.0:
; CHECK-NEXT: rlwinm 4, 3, 27, 0, 31
; CHECK-NEXT: rotlwi 4, 3, 27
; CHECK-NEXT: rlwimi 4, 3, 3, 0, 28
; CHECK-NEXT: mr 3, 4
; CHECK-NEXT: blr
@ -42,7 +42,7 @@ define i16 @rotl_i16(i16 %x, i16 %z) {
; CHECK: # %bb.0:
; CHECK-NEXT: neg 5, 4
; CHECK-NEXT: clrlwi 6, 3, 16
; CHECK-NEXT: rlwinm 4, 4, 0, 28, 31
; CHECK-NEXT: clrlwi 4, 4, 28
; CHECK-NEXT: clrlwi 5, 5, 28
; CHECK-NEXT: slw 3, 3, 4
; CHECK-NEXT: srw 4, 6, 5
@ -55,7 +55,7 @@ define i16 @rotl_i16(i16 %x, i16 %z) {
define i32 @rotl_i32(i32 %x, i32 %z) {
; CHECK-LABEL: rotl_i32:
; CHECK: # %bb.0:
; CHECK-NEXT: rlwnm 3, 3, 4, 0, 31
; CHECK-NEXT: rotlw 3, 3, 4
; CHECK-NEXT: blr
%f = call i32 @llvm.fshl.i32(i32 %x, i32 %x, i32 %z)
ret i32 %f
@ -64,7 +64,7 @@ define i32 @rotl_i32(i32 %x, i32 %z) {
define i64 @rotl_i64(i64 %x, i64 %z) {
; CHECK-LABEL: rotl_i64:
; CHECK: # %bb.0:
; CHECK-NEXT: rldcl 3, 3, 4, 0
; CHECK-NEXT: rotld 3, 3, 4
; CHECK-NEXT: blr
%f = call i64 @llvm.fshl.i64(i64 %x, i64 %x, i64 %z)
ret i64 %f
@ -98,7 +98,7 @@ define <4 x i32> @rotl_v4i32_const_shift(<4 x i32> %x) {
define i8 @rotr_i8_const_shift(i8 %x) {
; CHECK-LABEL: rotr_i8_const_shift:
; CHECK: # %bb.0:
; CHECK-NEXT: rlwinm 4, 3, 29, 0, 31
; CHECK-NEXT: rotlwi 4, 3, 29
; CHECK-NEXT: rlwimi 4, 3, 5, 0, 26
; CHECK-NEXT: mr 3, 4
; CHECK-NEXT: blr
@ -109,7 +109,7 @@ define i8 @rotr_i8_const_shift(i8 %x) {
define i32 @rotr_i32_const_shift(i32 %x) {
; CHECK-LABEL: rotr_i32_const_shift:
; CHECK: # %bb.0:
; CHECK-NEXT: rlwinm 3, 3, 29, 0, 31
; CHECK-NEXT: rotlwi 3, 3, 29
; CHECK-NEXT: blr
%f = call i32 @llvm.fshr.i32(i32 %x, i32 %x, i32 3)
ret i32 %f
@ -122,7 +122,7 @@ define i16 @rotr_i16(i16 %x, i16 %z) {
; CHECK: # %bb.0:
; CHECK-NEXT: neg 5, 4
; CHECK-NEXT: clrlwi 6, 3, 16
; CHECK-NEXT: rlwinm 4, 4, 0, 28, 31
; CHECK-NEXT: clrlwi 4, 4, 28
; CHECK-NEXT: clrlwi 5, 5, 28
; CHECK-NEXT: srw 4, 6, 4
; CHECK-NEXT: slw 3, 3, 5
@ -136,7 +136,7 @@ define i32 @rotr_i32(i32 %x, i32 %z) {
; CHECK-LABEL: rotr_i32:
; CHECK: # %bb.0:
; CHECK-NEXT: neg 4, 4
; CHECK-NEXT: rlwnm 3, 3, 4, 0, 31
; CHECK-NEXT: rotlw 3, 3, 4
; CHECK-NEXT: blr
%f = call i32 @llvm.fshr.i32(i32 %x, i32 %x, i32 %z)
ret i32 %f
@ -146,7 +146,7 @@ define i64 @rotr_i64(i64 %x, i64 %z) {
; CHECK-LABEL: rotr_i64:
; CHECK: # %bb.0:
; CHECK-NEXT: neg 4, 4
; CHECK-NEXT: rldcl 3, 3, 4, 0
; CHECK-NEXT: rotld 3, 3, 4
; CHECK-NEXT: blr
%f = call i64 @llvm.fshr.i64(i64 %x, i64 %x, i64 %z)
ret i64 %f

12
test/CodeGen/PowerPC/funnel-shift.ll
View File

@ -44,7 +44,7 @@ define i37 @fshl_i37(i37 %x, i37 %y, i37 %z) {
; CHECK-NEXT: mulhdu 6, 5, 6
; CHECK-NEXT: rldicl 6, 6, 59, 5
; CHECK-NEXT: mulli 6, 6, 37
; CHECK-NEXT: subf. 5, 6, 5
; CHECK-NEXT: sub. 5, 5, 6
; CHECK-NEXT: subfic 6, 5, 37
; CHECK-NEXT: sld 5, 3, 5
; CHECK-NEXT: srd 4, 4, 6
@ -72,7 +72,7 @@ define i7 @fshl_i7_const_fold() {
define i32 @fshl_i32_const_shift(i32 %x, i32 %y) {
; CHECK-LABEL: fshl_i32_const_shift:
; CHECK: # %bb.0:
; CHECK-NEXT: rlwinm 4, 4, 9, 0, 31
; CHECK-NEXT: rotlwi 4, 4, 9
; CHECK-NEXT: rlwimi 4, 3, 9, 0, 22
; CHECK-NEXT: mr 3, 4
; CHECK-NEXT: blr
@ -85,7 +85,7 @@ define i32 @fshl_i32_const_shift(i32 %x, i32 %y) {
define i32 @fshl_i32_const_overshift(i32 %x, i32 %y) {
; CHECK-LABEL: fshl_i32_const_overshift:
; CHECK: # %bb.0:
; CHECK-NEXT: rlwinm 4, 4, 9, 0, 31
; CHECK-NEXT: rotlwi 4, 4, 9
; CHECK-NEXT: rlwimi 4, 3, 9, 0, 22
; CHECK-NEXT: mr 3, 4
; CHECK-NEXT: blr
@ -149,7 +149,7 @@ define i37 @fshr_i37(i37 %x, i37 %y, i37 %z) {
; CHECK-NEXT: mulhdu 6, 5, 6
; CHECK-NEXT: rldicl 6, 6, 59, 5
; CHECK-NEXT: mulli 6, 6, 37
; CHECK-NEXT: subf. 5, 6, 5
; CHECK-NEXT: sub. 5, 5, 6
; CHECK-NEXT: clrldi 6, 4, 27
; CHECK-NEXT: subfic 7, 5, 37
; CHECK-NEXT: srd 5, 6, 5
@ -178,7 +178,7 @@ define i7 @fshr_i7_const_fold() {
define i32 @fshr_i32_const_shift(i32 %x, i32 %y) {
; CHECK-LABEL: fshr_i32_const_shift:
; CHECK: # %bb.0:
; CHECK-NEXT: rlwinm 4, 4, 23, 0, 31
; CHECK-NEXT: rotlwi 4, 4, 23
; CHECK-NEXT: rlwimi 4, 3, 23, 0, 8
; CHECK-NEXT: mr 3, 4
; CHECK-NEXT: blr
@ -191,7 +191,7 @@ define i32 @fshr_i32_const_shift(i32 %x, i32 %y) {
define i32 @fshr_i32_const_overshift(i32 %x, i32 %y) {
; CHECK-LABEL: fshr_i32_const_overshift:
; CHECK: # %bb.0:
; CHECK-NEXT: rlwinm 4, 4, 23, 0, 31
; CHECK-NEXT: rotlwi 4, 4, 23
; CHECK-NEXT: rlwimi 4, 3, 23, 0, 8
; CHECK-NEXT: mr 3, 4
; CHECK-NEXT: blr

2
test/CodeGen/PowerPC/inlineasm-i64-reg.ll
View File

@ -81,7 +81,7 @@ entry:
; CHECK: sc
; CHECK: #NO_APP
; CHECK: cmpwi {{[0-9]+}}, [[REG]], 1
; CHECK: cmpwi [[REG]], 1
; CHECK: blr

2
test/CodeGen/PowerPC/knowCRBitSpill.ll
View File

@ -20,7 +20,7 @@
define dso_local signext i32 @spillCRSET(i32 signext %p1, i32 signext %p2) {
; CHECK-LABEL: spillCRSET:
; CHECK: # %bb.2:
; CHECK-DAG: crnor [[CREG:.*]]*cr5+lt, eq, eq
; CHECK-DAG: crnot [[CREG:.*]]*cr5+lt, eq
; CHECK-DAG: mfocrf [[REG2:.*]], [[CREG]]
; CHECK-DAG: rlwinm [[REG2]], [[REG2]]
; CHECK: .LBB0_3:

2
test/CodeGen/PowerPC/load-and-splat.ll
View File

@ -130,7 +130,7 @@ define <16 x i8> @adjusted_lxvwsx(i64* %s, i64* %t) {
; P8-LABEL: adjusted_lxvwsx:
; P8: # %bb.0: # %entry
; P8-NEXT: ld r3, 0(r3)
; P8-NEXT: mtvsrd f0, r3
; P8-NEXT: mtfprd f0, r3
; P8-NEXT: xxswapd v2, vs0
; P8-NEXT: xxspltw v2, v2, 2
; P8-NEXT: blr

2
test/CodeGen/PowerPC/loop-comment.ll
View File

@ -4,7 +4,7 @@
define void @test(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: .LBB0_1:
; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6

4
test/CodeGen/PowerPC/memcmp.ll
View File

@ -6,9 +6,9 @@ define signext i32 @memcmp8(i32* nocapture readonly %buffer1, i32* nocapture rea
; CHECK: # %bb.0:
; CHECK-NEXT: ldbrx 3, 0, 3
; CHECK-NEXT: ldbrx 4, 0, 4
; CHECK-NEXT: subfc 5, 3, 4
; CHECK-NEXT: subc 5, 4, 3
; CHECK-NEXT: subfe 5, 4, 4
; CHECK-NEXT: subfc 4, 4, 3
; CHECK-NEXT: subc 4, 3, 4
; CHECK-NEXT: subfe 3, 3, 3
; CHECK-NEXT: neg 4, 5
; CHECK-NEXT: neg 3, 3

20
test/CodeGen/PowerPC/optcmp.ll
View File

@ -70,14 +70,14 @@ entry:
define i64 @fool(i64 %a, i64 %b, i64* nocapture %c) #0 {
; CHECK-LABEL: fool:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subf. 6, 4, 3
; CHECK-NEXT: sub. 6, 3, 4
; CHECK-NEXT: isel 3, 3, 4, 1
; CHECK-NEXT: std 6, 0(5)
; CHECK-NEXT: blr
;
; CHECK-NO-ISEL-LABEL: fool:
; CHECK-NO-ISEL: # %bb.0: # %entry
; CHECK-NO-ISEL-NEXT: subf. 6, 4, 3
; CHECK-NO-ISEL-NEXT: sub. 6, 3, 4
; CHECK-NO-ISEL-NEXT: bc 12, 1, .LBB2_2
; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
; CHECK-NO-ISEL-NEXT: ori 3, 4, 0
@ -96,14 +96,14 @@ entry:
define i64 @foolb(i64 %a, i64 %b, i64* nocapture %c) #0 {
; CHECK-LABEL: foolb:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subf. 6, 4, 3
; CHECK-NEXT: sub. 6, 3, 4
; CHECK-NEXT: isel 3, 4, 3, 1
; CHECK-NEXT: std 6, 0(5)
; CHECK-NEXT: blr
;
; CHECK-NO-ISEL-LABEL: foolb:
; CHECK-NO-ISEL: # %bb.0: # %entry
; CHECK-NO-ISEL-NEXT: subf. 6, 4, 3
; CHECK-NO-ISEL-NEXT: sub. 6, 3, 4
; CHECK-NO-ISEL-NEXT: bc 12, 1, .LBB3_1
; CHECK-NO-ISEL-NEXT: b .LBB3_2
; CHECK-NO-ISEL-NEXT: .LBB3_1: # %entry
@ -122,14 +122,14 @@ entry:
define i64 @foolc(i64 %a, i64 %b, i64* nocapture %c) #0 {
; CHECK-LABEL: foolc:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subf. 6, 3, 4
; CHECK-NEXT: sub. 6, 4, 3
; CHECK-NEXT: isel 3, 3, 4, 0
; CHECK-NEXT: std 6, 0(5)
; CHECK-NEXT: blr
;
; CHECK-NO-ISEL-LABEL: foolc:
; CHECK-NO-ISEL: # %bb.0: # %entry
; CHECK-NO-ISEL-NEXT: subf. 6, 3, 4
; CHECK-NO-ISEL-NEXT: sub. 6, 4, 3
; CHECK-NO-ISEL-NEXT: bc 12, 0, .LBB4_2
; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
; CHECK-NO-ISEL-NEXT: ori 3, 4, 0
@ -148,14 +148,14 @@ entry:
define i64 @foold(i64 %a, i64 %b, i64* nocapture %c) #0 {
; CHECK-LABEL: foold:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subf. 6, 3, 4
; CHECK-NEXT: sub. 6, 4, 3
; CHECK-NEXT: isel 3, 3, 4, 1
; CHECK-NEXT: std 6, 0(5)
; CHECK-NEXT: blr
;
; CHECK-NO-ISEL-LABEL: foold:
; CHECK-NO-ISEL: # %bb.0: # %entry
; CHECK-NO-ISEL-NEXT: subf. 6, 3, 4
; CHECK-NO-ISEL-NEXT: sub. 6, 4, 3
; CHECK-NO-ISEL-NEXT: bc 12, 1, .LBB5_2
; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
; CHECK-NO-ISEL-NEXT: ori 3, 4, 0
@ -174,14 +174,14 @@ entry:
define i64 @foold2(i64 %a, i64 %b, i64* nocapture %c) #0 {
; CHECK-LABEL: foold2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subf. 6, 4, 3
; CHECK-NEXT: sub. 6, 3, 4
; CHECK-NEXT: isel 3, 3, 4, 0
; CHECK-NEXT: std 6, 0(5)
; CHECK-NEXT: blr
;
; CHECK-NO-ISEL-LABEL: foold2:
; CHECK-NO-ISEL: # %bb.0: # %entry
; CHECK-NO-ISEL-NEXT: subf. 6, 4, 3
; CHECK-NO-ISEL-NEXT: sub. 6, 3, 4
; CHECK-NO-ISEL-NEXT: bc 12, 0, .LBB6_2
; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
; CHECK-NO-ISEL-NEXT: ori 3, 4, 0

4
test/CodeGen/PowerPC/optimize-andiso.ll
View File

@ -15,8 +15,8 @@ define float @floatundisf(i64 %a) {
; CHECK-NEXT: li r4, 3
; CHECK-NEXT: isel r4, r5, r4, eq
; CHECK-NEXT: srd r3, r3, r4
; CHECK-NEXT: rlwinm r3, r3, 0, 9, 31
; CHECK-NEXT: mtvsrd f0, r3
; CHECK-NEXT: clrlwi r3, r3, 9
; CHECK-NEXT: mtfprd f0, r3
; CHECK-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-NEXT: xscvspdpn f1, vs0
; CHECK-NEXT: blr

140
test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll
View File

@ -21,7 +21,7 @@ entry:
; CHECK: sldi r3, r3, 56
; CHECK: mtvsrd v2, r3
; CHECK-LE-LABEL: buildc
; CHECK-LE: mtvsrd f0, r3
; CHECK-LE: mtfprd f0, r3
; CHECK-LE: xxswapd v2, vs0
}
@ -35,7 +35,7 @@ entry:
; CHECK: sldi r3, r3, 48
; CHECK: mtvsrd v2, r3
; CHECK-LE-LABEL: builds
; CHECK-LE: mtvsrd f0, r3
; CHECK-LE: mtfprd f0, r3
; CHECK-LE: xxswapd v2, vs0
}
@ -46,10 +46,10 @@ entry:
%splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
ret <4 x i32> %splat.splat
; CHECK-LABEL: buildi
; CHECK: mtvsrwz f0, r3
; CHECK: mtfprwz f0, r3
; CHECK: xxspltw v2, vs0, 1
; CHECK-LE-LABEL: buildi
; CHECK-LE: mtvsrwz f0, r3
; CHECK-LE: mtfprwz f0, r3
; CHECK-LE: xxspltw v2, vs0, 1
}
@ -60,9 +60,9 @@ entry:
%splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
ret <2 x i64> %splat.splat
; CHECK-LABEL: buildl
; CHECK: mtvsrd f0, r3
; CHECK: mtfprd f0, r3
; CHECK-LE-LABEL: buildl
; CHECK-LE: mtvsrd f0, r3
; CHECK-LE: mtfprd f0, r3
; CHECK-LE: xxspltd v2, vs0, 0
}
@ -107,7 +107,7 @@ entry:
; CHECK: rldicl r3, r3, 8, 56
; CHECK: extsb r3, r3
; CHECK-LE-LABEL: @getsc0
; CHECK-LE: mfvsrd r3, f0
; CHECK-LE: mffprd r3, f0
; CHECK-LE: clrldi r3, r3, 56
; CHECK-LE: extsb r3, r3
}
@ -122,7 +122,7 @@ entry:
; CHECK: rldicl r3, r3, 16, 56
; CHECK: extsb r3, r3
; CHECK-LE-LABEL: @getsc1
; CHECK-LE: mfvsrd r3, f0
; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 56, 56
; CHECK-LE: extsb r3, r3
}
@ -137,7 +137,7 @@ entry:
; CHECK: rldicl r3, r3, 24, 56
; CHECK: extsb r3, r3
; CHECK-LE-LABEL: @getsc2
; CHECK-LE: mfvsrd r3, f0
; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 48, 56
; CHECK-LE: extsb r3, r3
}
@ -152,7 +152,7 @@ entry:
; CHECK: rldicl r3, r3, 32, 56
; CHECK: extsb r3, r3
; CHECK-LE-LABEL: @getsc3
; CHECK-LE: mfvsrd r3, f0
; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 40, 56
; CHECK-LE: extsb r3, r3
}
@ -167,7 +167,7 @@ entry:
; CHECK: rldicl r3, r3, 40, 56
; CHECK: extsb r3, r3
; CHECK-LE-LABEL: @getsc4
; CHECK-LE: mfvsrd r3, f0
; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 32, 56
; CHECK-LE: extsb r3, r3
}
@ -182,7 +182,7 @@ entry:
; CHECK: rldicl r3, r3, 48, 56
; CHECK: extsb r3, r3
; CHECK-LE-LABEL: @getsc5
; CHECK-LE: mfvsrd r3, f0
; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 24, 56
; CHECK-LE: extsb r3, r3
}
@ -197,7 +197,7 @@ entry:
; CHECK: rldicl r3, r3, 56, 56
; CHECK: extsb r3, r3
; CHECK-LE-LABEL: @getsc6
; CHECK-LE: mfvsrd r3, f0
; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 16, 56
; CHECK-LE: extsb r3, r3
}
@ -212,7 +212,7 @@ entry:
; CHECK: clrldi r3, r3, 56
; CHECK: extsb r3, r3
; CHECK-LE-LABEL: @getsc7
; CHECK-LE: mfvsrd r3, f0
; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 8, 56
; CHECK-LE: extsb r3, r3
}
@ -223,7 +223,7 @@ entry:
%vecext = extractelement <16 x i8> %vsc, i32 8
ret i8 %vecext
; CHECK-LABEL: @getsc8
; CHECK: mfvsrd r3, f0
; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 8, 56
; CHECK: extsb r3, r3
; CHECK-LE-LABEL: @getsc8
@ -238,7 +238,7 @@ entry:
%vecext = extractelement <16 x i8> %vsc, i32 9
ret i8 %vecext
; CHECK-LABEL: @getsc9
; CHECK: mfvsrd r3, f0
; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 16, 56
; CHECK: extsb r3, r3
; CHECK-LE-LABEL: @getsc9
@ -253,7 +253,7 @@ entry:
%vecext = extractelement <16 x i8> %vsc, i32 10
ret i8 %vecext
; CHECK-LABEL: @getsc10
; CHECK: mfvsrd r3, f0
; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 24, 56
; CHECK: extsb r3, r3
; CHECK-LE-LABEL: @getsc10
@ -268,7 +268,7 @@ entry:
%vecext = extractelement <16 x i8> %vsc, i32 11
ret i8 %vecext
; CHECK-LABEL: @getsc11
; CHECK: mfvsrd r3, f0
; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 32, 56
; CHECK: extsb r3, r3
; CHECK-LE-LABEL: @getsc11
@ -283,7 +283,7 @@ entry:
%vecext = extractelement <16 x i8> %vsc, i32 12
ret i8 %vecext
; CHECK-LABEL: @getsc12
; CHECK: mfvsrd r3, f0
; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 40, 56
; CHECK: extsb r3, r3
; CHECK-LE-LABEL: @getsc12
@ -298,7 +298,7 @@ entry:
%vecext = extractelement <16 x i8> %vsc, i32 13
ret i8 %vecext
; CHECK-LABEL: @getsc13
; CHECK: mfvsrd r3, f0
; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 48, 56
; CHECK: extsb r3, r3
; CHECK-LE-LABEL: @getsc13
@ -313,7 +313,7 @@ entry:
%vecext = extractelement <16 x i8> %vsc, i32 14
ret i8 %vecext
; CHECK-LABEL: @getsc14
; CHECK: mfvsrd r3, f0
; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 56, 56
; CHECK: extsb r3, r3
; CHECK-LE-LABEL: @getsc14
@ -328,7 +328,7 @@ entry:
%vecext = extractelement <16 x i8> %vsc, i32 15
ret i8 %vecext
; CHECK-LABEL: @getsc15
; CHECK: mfvsrd r3, f0
; CHECK: mffprd r3, f0
; CHECK: clrldi r3, r3, 56
; CHECK: extsb r3, r3
; CHECK-LE-LABEL: @getsc15
@ -346,7 +346,7 @@ entry:
; CHECK: mfvsrd r3, v2
; CHECK: rldicl r3, r3, 8, 56
; CHECK-LE-LABEL: @getuc0
; CHECK-LE: mfvsrd r3, f0
; CHECK-LE: mffprd r3, f0
; CHECK-LE: clrldi r3, r3, 56
}
@ -359,7 +359,7 @@ entry:
; CHECK: mfvsrd r3, v2
; CHECK: rldicl r3, r3, 16, 56
; CHECK-LE-LABEL: @getuc1
; CHECK-LE: mfvsrd r3, f0
; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 56, 56
}
@ -372,7 +372,7 @@ entry:
; CHECK: mfvsrd r3, v2
; CHECK: rldicl r3, r3, 24, 56
; CHECK-LE-LABEL: @getuc2
; CHECK-LE: mfvsrd r3, f0
; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 48, 56
}
@ -385,7 +385,7 @@ entry:
; CHECK: mfvsrd r3, v2
; CHECK: rldicl r3, r3, 32, 56
; CHECK-LE-LABEL: @getuc3
; CHECK-LE: mfvsrd r3, f0
; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 40, 56
}
@ -398,7 +398,7 @@ entry:
; CHECK: mfvsrd r3, v2
; CHECK: rldicl r3, r3, 40, 56
; CHECK-LE-LABEL: @getuc4
; CHECK-LE: mfvsrd r3, f0
; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 32, 56
}
@ -411,7 +411,7 @@ entry:
; CHECK: mfvsrd r3, v2
; CHECK: rldicl r3, r3, 48, 56
; CHECK-LE-LABEL: @getuc5
; CHECK-LE: mfvsrd r3, f0
; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 24, 56
}
@ -424,7 +424,7 @@ entry:
; CHECK: mfvsrd r3, v2
; CHECK: rldicl r3, r3, 56, 56
; CHECK-LE-LABEL: @getuc6
; CHECK-LE: mfvsrd r3, f0
; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 16, 56
}
@ -437,7 +437,7 @@ entry:
; CHECK: mfvsrd r3, v2
; CHECK: clrldi r3, r3, 56
; CHECK-LE-LABEL: @getuc7
; CHECK-LE: mfvsrd r3, f0
; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 8, 56
}
@ -447,7 +447,7 @@ entry:
%vecext = extractelement <16 x i8> %vuc, i32 8
ret i8 %vecext
; CHECK-LABEL: @getuc8
; CHECK: mfvsrd r3, f0
; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 8, 56
; CHECK-LE-LABEL: @getuc8
; CHECK-LE: mfvsrd r3, v2
@ -460,7 +460,7 @@ entry:
%vecext = extractelement <16 x i8> %vuc, i32 9
ret i8 %vecext
; CHECK-LABEL: @getuc9
; CHECK: mfvsrd r3, f0
; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 16, 56
; CHECK-LE-LABEL: @getuc9
; CHECK-LE: mfvsrd r3, v2
@ -473,7 +473,7 @@ entry:
%vecext = extractelement <16 x i8> %vuc, i32 10
ret i8 %vecext
; CHECK-LABEL: @getuc10
; CHECK: mfvsrd r3, f0
; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 24, 56
; CHECK-LE-LABEL: @getuc10
; CHECK-LE: mfvsrd r3, v2
@ -486,7 +486,7 @@ entry:
%vecext = extractelement <16 x i8> %vuc, i32 11
ret i8 %vecext
; CHECK-LABEL: @getuc11
; CHECK: mfvsrd r3, f0
; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 32, 56
; CHECK-LE-LABEL: @getuc11
; CHECK-LE: mfvsrd r3, v2
@ -499,7 +499,7 @@ entry:
%vecext = extractelement <16 x i8> %vuc, i32 12
ret i8 %vecext
; CHECK-LABEL: @getuc12
; CHECK: mfvsrd r3, f0
; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 40, 56
; CHECK-LE-LABEL: @getuc12
; CHECK-LE: mfvsrd r3, v2
@ -512,7 +512,7 @@ entry:
%vecext = extractelement <16 x i8> %vuc, i32 13
ret i8 %vecext
; CHECK-LABEL: @getuc13
; CHECK: mfvsrd r3, f0
; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 48, 56
; CHECK-LE-LABEL: @getuc13
; CHECK-LE: mfvsrd r3, v2
@ -525,7 +525,7 @@ entry:
%vecext = extractelement <16 x i8> %vuc, i32 14
ret i8 %vecext
; CHECK-LABEL: @getuc14
; CHECK: mfvsrd r3, f0
; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 56, 56
; CHECK-LE-LABEL: @getuc14
; CHECK-LE: mfvsrd r3, v2
@ -538,7 +538,7 @@ entry:
%vecext = extractelement <16 x i8> %vuc, i32 15
ret i8 %vecext
; CHECK-LABEL: @getuc15
; CHECK: mfvsrd r3, f0
; CHECK: mffprd r3, f0
; CHECK: clrldi r3, r3, 56
; CHECK-LE-LABEL: @getuc15
; CHECK-LE: mfvsrd r3, v2
@ -611,7 +611,7 @@ entry:
; CHECK: rldicl r3, r3, 16, 48
; CHECK: extsh r3, r3
; CHECK-LE-LABEL: @getss0
; CHECK-LE: mfvsrd r3, f0
; CHECK-LE: mffprd r3, f0
; CHECK-LE: clrldi r3, r3, 48
; CHECK-LE: extsh r3, r3
}
@ -626,7 +626,7 @@ entry:
; CHECK: rldicl r3, r3, 32, 48
; CHECK: extsh r3, r3
; CHECK-LE-LABEL: @getss1
; CHECK-LE: mfvsrd r3, f0
; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 48, 48
; CHECK-LE: extsh r3, r3
}
@ -641,7 +641,7 @@ entry:
; CHECK: rldicl r3, r3, 48, 48
; CHECK: extsh r3, r3
; CHECK-LE-LABEL: @getss2
; CHECK-LE: mfvsrd r3, f0
; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 32, 48
; CHECK-LE: extsh r3, r3
}
@ -656,7 +656,7 @@ entry:
; CHECK: clrldi r3, r3, 48
; CHECK: extsh r3, r3
; CHECK-LE-LABEL: @getss3
; CHECK-LE: mfvsrd r3, f0
; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 16, 48
; CHECK-LE: extsh r3, r3
}
@ -667,7 +667,7 @@ entry:
%vecext = extractelement <8 x i16> %vss, i32 4
ret i16 %vecext
; CHECK-LABEL: @getss4
; CHECK: mfvsrd r3, f0
; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 16, 48
; CHECK: extsh r3, r3
; CHECK-LE-LABEL: @getss4
@ -682,7 +682,7 @@ entry:
%vecext = extractelement <8 x i16> %vss, i32 5
ret i16 %vecext
; CHECK-LABEL: @getss5
; CHECK: mfvsrd r3, f0
; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 32, 48
; CHECK: extsh r3, r3
; CHECK-LE-LABEL: @getss5
@ -697,7 +697,7 @@ entry:
%vecext = extractelement <8 x i16> %vss, i32 6
ret i16 %vecext
; CHECK-LABEL: @getss6
; CHECK: mfvsrd r3, f0
; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 48, 48
; CHECK: extsh r3, r3
; CHECK-LE-LABEL: @getss6
@ -712,7 +712,7 @@ entry:
%vecext = extractelement <8 x i16> %vss, i32 7
ret i16 %vecext
; CHECK-LABEL: @getss7
; CHECK: mfvsrd r3, f0
; CHECK: mffprd r3, f0
; CHECK: clrldi r3, r3, 48
; CHECK: extsh r3, r3
; CHECK-LE-LABEL: @getss7
@ -730,7 +730,7 @@ entry:
; CHECK: mfvsrd r3, v2
; CHECK: rldicl r3, r3, 16, 48
; CHECK-LE-LABEL: @getus0
; CHECK-LE: mfvsrd r3, f0
; CHECK-LE: mffprd r3, f0
; CHECK-LE: clrldi r3, r3, 48
}
@ -743,7 +743,7 @@ entry:
; CHECK: mfvsrd r3, v2
; CHECK: rldicl r3, r3, 32, 48
; CHECK-LE-LABEL: @getus1
; CHECK-LE: mfvsrd r3, f0
; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 48, 48
}
@ -756,7 +756,7 @@ entry:
; CHECK: mfvsrd r3, v2
; CHECK: rldicl r3, r3, 48, 48
; CHECK-LE-LABEL: @getus2
; CHECK-LE: mfvsrd r3, f0
; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 32, 48
}
@ -769,7 +769,7 @@ entry:
; CHECK: mfvsrd r3, v2
; CHECK: clrldi r3, r3, 48
; CHECK-LE-LABEL: @getus3
; CHECK-LE: mfvsrd r3, f0
; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 16, 48
}
@ -779,7 +779,7 @@ entry:
%vecext = extractelement <8 x i16> %vus, i32 4
ret i16 %vecext
; CHECK-LABEL: @getus4
; CHECK: mfvsrd r3, f0
; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 16, 48
; CHECK-LE-LABEL: @getus4
; CHECK-LE: mfvsrd r3, v2
@ -792,7 +792,7 @@ entry:
%vecext = extractelement <8 x i16> %vus, i32 5
ret i16 %vecext
; CHECK-LABEL: @getus5
; CHECK: mfvsrd r3, f0
; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 32, 48
; CHECK-LE-LABEL: @getus5
; CHECK-LE: mfvsrd r3, v2
@ -805,7 +805,7 @@ entry:
%vecext = extractelement <8 x i16> %vus, i32 6
ret i16 %vecext
; CHECK-LABEL: @getus6
; CHECK: mfvsrd r3, f0
; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 48, 48
; CHECK-LE-LABEL: @getus6
; CHECK-LE: mfvsrd r3, v2
@ -818,7 +818,7 @@ entry:
%vecext = extractelement <8 x i16> %vus, i32 7
ret i16 %vecext
; CHECK-LABEL: @getus7
; CHECK: mfvsrd r3, f0
; CHECK: mffprd r3, f0
; CHECK: clrldi r3, r3, 48
; CHECK-LE-LABEL: @getus7
; CHECK-LE: mfvsrd r3, v2
@ -892,11 +892,11 @@ entry:
ret i32 %vecext
; CHECK-LABEL: @getsi0
; CHECK: xxsldwi vs0, v2, v2, 3
; CHECK: mfvsrwz r3, f0
; CHECK: mffprwz r3, f0
; CHECK: extsw r3, r3
; CHECK-LE-LABEL: @getsi0
; CHECK-LE: xxswapd vs0, v2
; CHECK-LE: mfvsrwz r3, f0
; CHECK-LE: mffprwz r3, f0
; CHECK-LE: extsw r3, r3
}
@ -910,7 +910,7 @@ entry:
; CHECK: extsw r3, r3
; CHECK-LE-LABEL: @getsi1
; CHECK-LE: xxsldwi vs0, v2, v2, 1
; CHECK-LE: mfvsrwz r3, f0
; CHECK-LE: mffprwz r3, f0
; CHECK-LE: extsw r3, r3
}
@ -921,7 +921,7 @@ entry:
ret i32 %vecext
; CHECK-LABEL: @getsi2
; CHECK: xxsldwi vs0, v2, v2, 1
; CHECK: mfvsrwz r3, f0
; CHECK: mffprwz r3, f0
; CHECK: extsw r3, r3
; CHECK-LE-LABEL: @getsi2
; CHECK-LE: mfvsrwz r3, v2
@ -935,11 +935,11 @@ entry:
ret i32 %vecext
; CHECK-LABEL: @getsi3
; CHECK: xxswapd vs0, v2
; CHECK: mfvsrwz r3, f0
; CHECK: mffprwz r3, f0
; CHECK: extsw r3, r3
; CHECK-LE-LABEL: @getsi3
; CHECK-LE: xxsldwi vs0, v2, v2, 3
; CHECK-LE: mfvsrwz r3, f0
; CHECK-LE: mffprwz r3, f0
; CHECK-LE: extsw r3, r3
}
@ -950,10 +950,10 @@ entry:
ret i32 %vecext
; CHECK-LABEL: @getui0
; CHECK: xxsldwi vs0, v2, v2, 3
; CHECK: mfvsrwz r3, f0
; CHECK: mffprwz r3, f0
; CHECK-LE-LABEL: @getui0
; CHECK-LE: xxswapd vs0, v2
; CHECK-LE: mfvsrwz r3, f0
; CHECK-LE: mffprwz r3, f0
}
; Function Attrs: norecurse nounwind readnone
@ -965,7 +965,7 @@ entry:
; CHECK: mfvsrwz r3, v2
; CHECK-LE-LABEL: @getui1
; CHECK-LE: xxsldwi vs0, v2, v2, 1
; CHECK-LE: mfvsrwz r3, f0
; CHECK-LE: mffprwz r3, f0
}
; Function Attrs: norecurse nounwind readnone
@ -975,7 +975,7 @@ entry:
ret i32 %vecext
; CHECK-LABEL: @getui2
; CHECK: xxsldwi vs0, v2, v2, 1
; CHECK: mfvsrwz r3, f0
; CHECK: mffprwz r3, f0
; CHECK-LE-LABEL: @getui2
; CHECK-LE: mfvsrwz r3, v2
}
@ -987,10 +987,10 @@ entry:
ret i32 %vecext
; CHECK-LABEL: @getui3
; CHECK: xxswapd vs0, v2
; CHECK: mfvsrwz r3, f0
; CHECK: mffprwz r3, f0
; CHECK-LE-LABEL: @getui3
; CHECK-LE: xxsldwi vs0, v2, v2, 3
; CHECK-LE: mfvsrwz r3, f0
; CHECK-LE: mffprwz r3, f0
}
; Function Attrs: norecurse nounwind readnone
@ -1022,7 +1022,7 @@ entry:
; CHECK: mfvsrd r3, v2
; CHECK-LE-LABEL: @getsl0
; CHECK-LE: xxswapd vs0, v2
; CHECK-LE: mfvsrd r3, f0
; CHECK-LE: mffprd r3, f0
}
; Function Attrs: norecurse nounwind readnone
@ -1032,7 +1032,7 @@ entry:
ret i64 %vecext
; CHECK-LABEL: @getsl1
; CHECK: xxswapd vs0, v2
; CHECK: mfvsrd r3, f0
; CHECK: mffprd r3, f0
; CHECK-LE-LABEL: @getsl1
; CHECK-LE: mfvsrd r3, v2
}
@ -1046,7 +1046,7 @@ entry:
; CHECK: mfvsrd r3, v2
; CHECK-LE-LABEL: @getul0
; CHECK-LE: xxswapd vs0, v2
; CHECK-LE: mfvsrd r3, f0
; CHECK-LE: mffprd r3, f0
}
; Function Attrs: norecurse nounwind readnone
@ -1056,7 +1056,7 @@ entry:
ret i64 %vecext
; CHECK-LABEL: @getul1
; CHECK: xxswapd vs0, v2
; CHECK: mfvsrd r3, f0
; CHECK: mffprd r3, f0
; CHECK-LE-LABEL: @getul1
; CHECK-LE: mfvsrd r3, v2
}

16
test/CodeGen/PowerPC/p9-xxinsertw-xxextractuw.ll
View File

@ -561,10 +561,10 @@ entry:
define <4 x i32> @_Z10testInsEltILj0EDv4_jjET0_S1_T1_(<4 x i32> %a, i32 zeroext %b) {
entry:
; CHECK-LABEL: _Z10testInsEltILj0EDv4_jjET0_S1_T1_
; CHECK: mtvsrwz 0, 5
; CHECK: mtfprwz 0, 5
; CHECK: xxinsertw 34, 0, 12
; CHECK-BE-LABEL: _Z10testInsEltILj0EDv4_jjET0_S1_T1_
; CHECK-BE: mtvsrwz 0, 5
; CHECK-BE: mtfprwz 0, 5
; CHECK-BE: xxinsertw 34, 0, 0
%vecins = insertelement <4 x i32> %a, i32 %b, i32 0
ret <4 x i32> %vecins
@ -573,10 +573,10 @@ entry:
define <4 x i32> @_Z10testInsEltILj1EDv4_jjET0_S1_T1_(<4 x i32> %a, i32 zeroext %b) {
entry:
; CHECK-LABEL: _Z10testInsEltILj1EDv4_jjET0_S1_T1_
; CHECK: mtvsrwz 0, 5
; CHECK: mtfprwz 0, 5
; CHECK: xxinsertw 34, 0, 8
; CHECK-BE-LABEL: _Z10testInsEltILj1EDv4_jjET0_S1_T1_
; CHECK-BE: mtvsrwz 0, 5
; CHECK-BE: mtfprwz 0, 5
; CHECK-BE: xxinsertw 34, 0, 4
%vecins = insertelement <4 x i32> %a, i32 %b, i32 1
ret <4 x i32> %vecins
@ -585,10 +585,10 @@ entry:
define <4 x i32> @_Z10testInsEltILj2EDv4_jjET0_S1_T1_(<4 x i32> %a, i32 zeroext %b) {
entry:
; CHECK-LABEL: _Z10testInsEltILj2EDv4_jjET0_S1_T1_
; CHECK: mtvsrwz 0, 5
; CHECK: mtfprwz 0, 5
; CHECK: xxinsertw 34, 0, 4
; CHECK-BE-LABEL: _Z10testInsEltILj2EDv4_jjET0_S1_T1_
; CHECK-BE: mtvsrwz 0, 5
; CHECK-BE: mtfprwz 0, 5
; CHECK-BE: xxinsertw 34, 0, 8
%vecins = insertelement <4 x i32> %a, i32 %b, i32 2
ret <4 x i32> %vecins
@ -597,10 +597,10 @@ entry:
define <4 x i32> @_Z10testInsEltILj3EDv4_jjET0_S1_T1_(<4 x i32> %a, i32 zeroext %b) {
entry:
; CHECK-LABEL: _Z10testInsEltILj3EDv4_jjET0_S1_T1_
; CHECK: mtvsrwz 0, 5
; CHECK: mtfprwz 0, 5
; CHECK: xxinsertw 34, 0, 0
; CHECK-BE-LABEL: _Z10testInsEltILj3EDv4_jjET0_S1_T1_
; CHECK-BE: mtvsrwz 0, 5
; CHECK-BE: mtfprwz 0, 5
; CHECK-BE: xxinsertw 34, 0, 12
%vecins = insertelement <4 x i32> %a, i32 %b, i32 3
ret <4 x i32> %vecins

18
test/CodeGen/PowerPC/popcnt-zext.ll
View File

@ -12,7 +12,7 @@ define i16 @zpop_i8_i16(i8 %x) {
; SLOW-LABEL: zpop_i8_i16:
; SLOW: # %bb.0:
; SLOW-NEXT: clrlwi 5, 3, 24
; SLOW-NEXT: rlwinm 3, 3, 31, 0, 31
; SLOW-NEXT: rotlwi 3, 3, 31
; SLOW-NEXT: andi. 3, 3, 85
; SLOW-NEXT: lis 4, 13107
; SLOW-NEXT: subf 3, 3, 5
@ -48,7 +48,7 @@ define i16 @popz_i8_i16(i8 %x) {
; SLOW-LABEL: popz_i8_i16:
; SLOW: # %bb.0:
; SLOW-NEXT: clrlwi 5, 3, 24
; SLOW-NEXT: rlwinm 3, 3, 31, 0, 31
; SLOW-NEXT: rotlwi 3, 3, 31
; SLOW-NEXT: andi. 3, 3, 85
; SLOW-NEXT: lis 4, 13107
; SLOW-NEXT: subf 3, 3, 5
@ -77,14 +77,14 @@ define i16 @popz_i8_i16(i8 %x) {
define i32 @zpop_i8_i32(i8 %x) {
; FAST-LABEL: zpop_i8_i32:
; FAST: # %bb.0:
; FAST-NEXT: rlwinm 3, 3, 0, 24, 31
; FAST-NEXT: clrlwi 3, 3, 24
; FAST-NEXT: popcntw 3, 3
; FAST-NEXT: blr
;
; SLOW-LABEL: zpop_i8_i32:
; SLOW: # %bb.0:
; SLOW-NEXT: clrlwi 5, 3, 24
; SLOW-NEXT: rlwinm 3, 3, 31, 0, 31
; SLOW-NEXT: rotlwi 3, 3, 31
; SLOW-NEXT: andi. 3, 3, 85
; SLOW-NEXT: lis 4, 13107
; SLOW-NEXT: subf 3, 3, 5
@ -120,7 +120,7 @@ define i32 @popz_i8_32(i8 %x) {
; SLOW-LABEL: popz_i8_32:
; SLOW: # %bb.0:
; SLOW-NEXT: clrlwi 5, 3, 24
; SLOW-NEXT: rlwinm 3, 3, 31, 0, 31
; SLOW-NEXT: rotlwi 3, 3, 31
; SLOW-NEXT: andi. 3, 3, 85
; SLOW-NEXT: lis 4, 13107
; SLOW-NEXT: subf 3, 3, 5
@ -149,14 +149,14 @@ define i32 @popz_i8_32(i8 %x) {
define i32 @zpop_i16_i32(i16 %x) {
; FAST-LABEL: zpop_i16_i32:
; FAST: # %bb.0:
; FAST-NEXT: rlwinm 3, 3, 0, 16, 31
; FAST-NEXT: clrlwi 3, 3, 16
; FAST-NEXT: popcntw 3, 3
; FAST-NEXT: blr
;
; SLOW-LABEL: zpop_i16_i32:
; SLOW: # %bb.0:
; SLOW-NEXT: clrlwi 5, 3, 16
; SLOW-NEXT: rlwinm 3, 3, 31, 0, 31
; SLOW-NEXT: rotlwi 3, 3, 31
; SLOW-NEXT: andi. 3, 3, 21845
; SLOW-NEXT: lis 4, 13107
; SLOW-NEXT: subf 3, 3, 5
@ -192,7 +192,7 @@ define i32 @popz_i16_32(i16 %x) {
; SLOW-LABEL: popz_i16_32:
; SLOW: # %bb.0:
; SLOW-NEXT: clrlwi 5, 3, 16
; SLOW-NEXT: rlwinm 3, 3, 31, 0, 31
; SLOW-NEXT: rotlwi 3, 3, 31
; SLOW-NEXT: andi. 3, 3, 21845
; SLOW-NEXT: lis 4, 13107
; SLOW-NEXT: subf 3, 3, 5
@ -305,7 +305,7 @@ define i64 @popa_i16_i64(i16 %x) {
; SLOW-LABEL: popa_i16_i64:
; SLOW: # %bb.0:
; SLOW-NEXT: clrlwi 5, 3, 16
; SLOW-NEXT: rlwinm 3, 3, 31, 0, 31
; SLOW-NEXT: rotlwi 3, 3, 31
; SLOW-NEXT: andi. 3, 3, 21845
; SLOW-NEXT: lis 4, 13107
; SLOW-NEXT: subf 3, 3, 5

2
test/CodeGen/PowerPC/ppc-crbits-onoff.ll
View File

@ -14,7 +14,7 @@ entry:
; CHECK-LABEL: @crbitsoff
; CHECK-NO-ISEL-LABEL: @crbitsoff
; CHECK-DAG: cmplwi {{[0-9]+}}, 3, 0
; CHECK-DAG: cmplwi 3, 0
; CHECK-DAG: li [[REG2:[0-9]+]], 1
; CHECK-DAG: cntlzw [[REG3:[0-9]+]],
; CHECK: isel [[REG4:[0-9]+]], 0, [[REG2]]

26
test/CodeGen/PowerPC/ppc-shrink-wrapping.ll
View File

@ -14,7 +14,7 @@
;
; Compare the arguments and return
; No prologue needed.
; ENABLE: cmpw 0, 3, 4
; ENABLE: cmpw 3, 4
; ENABLE-NEXT: bgelr 0
;
; Prologue code.
@ -24,7 +24,7 @@
;
; Compare the arguments and jump to exit.
; After the prologue is set.
; DISABLE: cmpw 0, 3, 4
; DISABLE: cmpw 3, 4
; DISABLE-NEXT: bge 0, .[[EXIT_LABEL:LBB[0-9_]+]]
;
; Store %a on the stack
@ -75,14 +75,14 @@ declare i32 @doSomething(i32, i32*)
; CHECK-LABEL: freqSaveAndRestoreOutsideLoop:
;
; Shrink-wrapping allows to skip the prologue in the else case.
; ENABLE: cmplwi 0, 3, 0
; ENABLE: cmplwi 3, 0
; ENABLE: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
;
; Prologue code.
; Make sure we save the link register
; CHECK: mflr {{[0-9]+}}
;
; DISABLE: cmplwi 0, 3, 0
; DISABLE: cmplwi 3, 0
; DISABLE: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
;
; Loop preheader
@ -202,7 +202,7 @@ for.end: ; preds = %for.body
; restore outside.
; CHECK-LABEL: loopInfoSaveOutsideLoop:
;
; ENABLE: cmplwi 0, 3, 0
; ENABLE: cmplwi 3, 0
; ENABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
;
; Prologue code.
@ -211,7 +211,7 @@ for.end: ; preds = %for.body
;
; DISABLE: std
; DISABLE-NEXT: std
; DISABLE: cmplwi 0, 3, 0
; DISABLE: cmplwi 3, 0
; DISABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
;
; Loop preheader
@ -284,7 +284,7 @@ declare void @somethingElse(...)
; save outside.
; CHECK-LABEL: loopInfoRestoreOutsideLoop:
;
; ENABLE: cmplwi 0, 3, 0
; ENABLE: cmplwi 3, 0
; ENABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
;
; Prologue code.
@ -293,7 +293,7 @@ declare void @somethingElse(...)
;
; DISABLE: std
; DISABLE-NEXT: std
; DISABLE: cmplwi 0, 3, 0
; DISABLE: cmplwi 3, 0
; DISABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
;
; CHECK: bl somethingElse
@ -373,7 +373,7 @@ entry:
; Check that we handle inline asm correctly.
; CHECK-LABEL: inlineAsm:
;
; ENABLE: cmplwi 0, 3, 0
; ENABLE: cmplwi 3, 0
; ENABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
;
; Prologue code.
@ -381,7 +381,7 @@ entry:
; ENABLE-DAG: li [[IV:[0-9]+]], 10
; ENABLE-DAG: std 14, -[[STACK_OFFSET:[0-9]+]](1) # 8-byte Folded Spill
;
; DISABLE: cmplwi 0, 3, 0
; DISABLE: cmplwi 3, 0
; DISABLE-NEXT: std 14, -[[STACK_OFFSET:[0-9]+]](1) # 8-byte Folded Spill
; DISABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
; DISABLE: li [[IV:[0-9]+]], 10
@ -438,13 +438,13 @@ if.end: ; preds = %for.body, %if.else
; Check that we handle calls to variadic functions correctly.
; CHECK-LABEL: callVariadicFunc:
;
; ENABLE: cmplwi 0, 3, 0
; ENABLE: cmplwi 3, 0
; ENABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
;
; Prologue code.
; CHECK: mflr {{[0-9]+}}
;
; DISABLE: cmplwi 0, 3, 0
; DISABLE: cmplwi 3, 0
; DISABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
;
; Setup of the varags.
@ -497,7 +497,7 @@ declare i32 @someVariadicFunc(i32, ...)
; CHECK-LABEL: noreturn:
; DISABLE: mflr {{[0-9]+}}
;
; CHECK: cmplwi 0, 3, 0
; CHECK: cmplwi 3, 0
; CHECK-NEXT: bne{{[-]?}} 0, .[[ABORT:LBB[0-9_]+]]
;
; CHECK: li 3, 42

56
test/CodeGen/PowerPC/ppc64-P9-setb.ll
View File

@ -123,7 +123,7 @@ define i64 @setb5(i64 %a, i64 %b) {
; CHECK-NOT: li
; CHECK: cmpd {{c?r?(0, )?}}r3, r4
; CHECK-NEXT: setb r3, cr0
; CHECK-NOT: subfc
; CHECK-NOT: subc
; CHECK-NOT: adde
; CHECK-NOT: xori
; CHECK-NOT: isel
@ -133,7 +133,7 @@ define i64 @setb5(i64 %a, i64 %b) {
; CHECK-PWR8-DAG: rldicl
; CHECK-PWR8-DAG: li
; CHECK-PWR8-DAG: cmpd
; CHECK-PWR8-DAG: subfc
; CHECK-PWR8-DAG: subc
; CHECK-PWR8-DAG: adde
; CHECK-PWR8-DAG: xori
; CHECK-PWR8: isel
@ -153,7 +153,7 @@ define i64 @setb6(i64 %a, i64 %b) {
; CHECK-NOT: li
; CHECK: cmpd {{c?r?(0, )?}}r3, r4
; CHECK-NEXT: setb r3, cr0
; CHECK-NOT: subfc
; CHECK-NOT: subc
; CHECK-NOT: adde
; CHECK-NOT: xori
; CHECK-NOT: isel
@ -163,7 +163,7 @@ define i64 @setb6(i64 %a, i64 %b) {
; CHECK-PWR8-DAG: rldicl
; CHECK-PWR8-DAG: li
; CHECK-PWR8-DAG: cmpd
; CHECK-PWR8-DAG: subfc
; CHECK-PWR8-DAG: subc
; CHECK-PWR8-DAG: adde
; CHECK-PWR8-DAG: xori
; CHECK-PWR8: isel
@ -183,7 +183,7 @@ define i64 @setb7(i64 %a, i64 %b) {
; CHECK-NOT: li
; CHECK: cmpd {{c?r?(0, )?}}r3, r4
; CHECK-NEXT: setb r3, cr0
; CHECK-NOT: subfc
; CHECK-NOT: subc
; CHECK-NOT: adde
; CHECK-NOT: xori
; CHECK-NOT: isel
@ -193,7 +193,7 @@ define i64 @setb7(i64 %a, i64 %b) {
; CHECK-PWR8-DAG: rldicl
; CHECK-PWR8-DAG: li
; CHECK-PWR8-DAG: cmpd
; CHECK-PWR8-DAG: subfc
; CHECK-PWR8-DAG: subc
; CHECK-PWR8-DAG: adde
; CHECK-PWR8-DAG: xori
; CHECK-PWR8: isel
@ -213,7 +213,7 @@ define i64 @setb8(i64 %a, i64 %b) {
; CHECK-NOT: li
; CHECK: cmpd {{c?r?(0, )?}}r3, r4
; CHECK-NEXT: setb r3, cr0
; CHECK-NOT: subfc
; CHECK-NOT: subc
; CHECK-NOT: adde
; CHECK-NOT: xori
; CHECK-NOT: isel
@ -223,7 +223,7 @@ define i64 @setb8(i64 %a, i64 %b) {
; CHECK-PWR8-DAG: rldicl
; CHECK-PWR8-DAG: li
; CHECK-PWR8-DAG: cmpd
; CHECK-PWR8-DAG: subfc
; CHECK-PWR8-DAG: subc
; CHECK-PWR8-DAG: adde
; CHECK-PWR8-DAG: xori
; CHECK-PWR8: isel
@ -347,7 +347,7 @@ define i64 @setb13(i64 %a, i64 %b) {
; CHECK-NOT: li
; CHECK: cmpd {{c?r?(0, )?}}r3, r4
; CHECK-NEXT: setb r3, cr0
; CHECK-NOT: subfc
; CHECK-NOT: subc
; CHECK-NOT: adde
; CHECK-NOT: xori
; CHECK-NOT: neg
@ -358,7 +358,7 @@ define i64 @setb13(i64 %a, i64 %b) {
; CHECK-PWR8-DAG: rldicl
; CHECK-PWR8-DAG: li
; CHECK-PWR8-DAG: cmpd
; CHECK-PWR8-DAG: subfc
; CHECK-PWR8-DAG: subc
; CHECK-PWR8-DAG: adde
; CHECK-PWR8-DAG: xori
; CHECK-PWR8-DAG: neg
@ -379,7 +379,7 @@ define i64 @setb14(i64 %a, i64 %b) {
; CHECK-NOT: li
; CHECK: cmpd {{c?r?(0, )?}}r3, r4
; CHECK-NEXT: setb r3, cr0
; CHECK-NOT: subfc
; CHECK-NOT: subc
; CHECK-NOT: adde
; CHECK-NOT: xori
; CHECK-NOT: neg
@ -390,7 +390,7 @@ define i64 @setb14(i64 %a, i64 %b) {
; CHECK-PWR8-DAG: rldicl
; CHECK-PWR8-DAG: li
; CHECK-PWR8-DAG: cmpd
; CHECK-PWR8-DAG: subfc
; CHECK-PWR8-DAG: subc
; CHECK-PWR8-DAG: adde
; CHECK-PWR8-DAG: xori
; CHECK-PWR8-DAG: neg
@ -411,7 +411,7 @@ define i64 @setb15(i64 %a, i64 %b) {
; CHECK-NOT: li
; CHECK: cmpd {{c?r?(0, )?}}r3, r4
; CHECK-NEXT: setb r3, cr0
; CHECK-NOT: subfc
; CHECK-NOT: subc
; CHECK-NOT: adde
; CHECK-NOT: xori
; CHECK-NOT: neg
@ -422,7 +422,7 @@ define i64 @setb15(i64 %a, i64 %b) {
; CHECK-PWR8-DAG: rldicl
; CHECK-PWR8-DAG: li
; CHECK-PWR8-DAG: cmpd
; CHECK-PWR8-DAG: subfc
; CHECK-PWR8-DAG: subc
; CHECK-PWR8-DAG: adde
; CHECK-PWR8-DAG: xori
; CHECK-PWR8-DAG: neg
@ -443,7 +443,7 @@ define i64 @setb16(i64 %a, i64 %b) {
; CHECK-NOT: li
; CHECK: cmpd {{c?r?(0, )?}}r3, r4
; CHECK-NEXT: setb r3, cr0
; CHECK-NOT: subfc
; CHECK-NOT: subc
; CHECK-NOT: adde
; CHECK-NOT: xori
; CHECK-NOT: neg
@ -454,7 +454,7 @@ define i64 @setb16(i64 %a, i64 %b) {
; CHECK-PWR8-DAG: rldicl
; CHECK-PWR8-DAG: li
; CHECK-PWR8-DAG: cmpd
; CHECK-PWR8-DAG: subfc
; CHECK-PWR8-DAG: subc
; CHECK-PWR8-DAG: adde
; CHECK-PWR8-DAG: xori
; CHECK-PWR8-DAG: neg
@ -769,14 +769,14 @@ define i64 @setb29(i64 %a, i64 %b) {
; CHECK-NOT: li
; CHECK: cmpd {{c?r?(0, )?}}r3, r4
; CHECK-NEXT: setb r3, cr0
; CHECK-NOT: subfc
; CHECK-NOT: subc
; CHECK-NOT: adde
; CHECK-NOT: xori
; CHECK-NOT: isel
; CHECK: blr
; CHECK-PWR8-LABEL: setb29
; CHECK-PWR8-DAG: cmpd
; CHECK-PWR8-DAG: subfc
; CHECK-PWR8-DAG: subc
; CHECK-PWR8-DAG: adde
; CHECK-PWR8: isel
; CHECK-PWR8: blr
@ -1013,13 +1013,13 @@ define i64 @setbud1(i64 %a, i64 %b) {
; CHECK-NOT: li
; CHECK: cmpld {{c?r?(0, )?}}r3, r4
; CHECK-NEXT: setb r3, cr0
; CHECK-NOT: subfc
; CHECK-NOT: subc
; CHECK-NOT: subfe
; CHECK-NOT: neg
; CHECK-NOT: isel
; CHECK: blr
; CHECK-PWR8-LABEL: setbud1
; CHECK-PWR8-DAG: subfc
; CHECK-PWR8-DAG: subc
; CHECK-PWR8-DAG: subfe
; CHECK-PWR8-DAG: cmpld
; CHECK-PWR8-DAG: neg
@ -1138,8 +1138,8 @@ define i64 @setbuh(i16 %a, i16 %b) {
%t4 = select i1 %t1, i64 1, i64 %t3
ret i64 %t4
; CHECK-LABEL: setbuh:
; CHECK-DAG: rlwinm [[RA:r[0-9]+]], r3, 0, 16, 31
; CHECK-DAG: rlwinm [[RB:r[0-9]+]], r4, 0, 16, 31
; CHECK-DAG: clrlwi [[RA:r[0-9]+]], r3, 16
; CHECK-DAG: clrlwi [[RB:r[0-9]+]], r4, 16
; CHECK-NOT: li
; CHECK-NOT: xor
; CHECK: cmplw {{c?r?(0, )?}}[[RA]], [[RB]]
@ -1151,8 +1151,8 @@ define i64 @setbuh(i16 %a, i16 %b) {
; CHECK-NOT: isel
; CHECK: blr
; CHECK-PWR8-LABEL: setbuh
; CHECK-PWR8: rlwinm
; CHECK-PWR8: rlwinm
; CHECK-PWR8: clrlwi
; CHECK-PWR8: clrlwi
; CHECK-PWR8-DAG: cmplw
; CHECK-PWR8-DAG: cntlzw
; CHECK-PWR8: srwi
@ -1170,8 +1170,8 @@ define i64 @setbuc(i8 %a, i8 %b) {
%t4 = select i1 %t1, i64 1, i64 %t3
ret i64 %t4
; CHECK-LABEL: setbuc:
; CHECK-DAG: rlwinm [[RA:r[0-9]+]], r3, 0, 24, 31
; CHECK-DAG: rlwinm [[RB:r[0-9]+]], r4, 0, 24, 31
; CHECK-DAG: clrlwi [[RA:r[0-9]+]], r3, 24
; CHECK-DAG: clrlwi [[RB:r[0-9]+]], r4, 24
; CHECK-NOT: li
; CHECK-NOT: clrldi
; CHECK: cmplw {{c?r?(0, )?}}[[RA]], [[RB]]
@ -1181,8 +1181,8 @@ define i64 @setbuc(i8 %a, i8 %b) {
; CHECK-NOT: isel
; CHECK: blr
; CHECK-PWR8-LABEL: setbuc
; CHECK-PWR8: rlwinm
; CHECK-PWR8: rlwinm
; CHECK-PWR8: clrlwi
; CHECK-PWR8: clrlwi
; CHECK-PWR8-DAG: clrldi
; CHECK-PWR8-DAG: clrldi
; CHECK-PWR8-DAG: cmplw

40
test/CodeGen/PowerPC/pr25080.ll
View File

@ -18,30 +18,30 @@ define <8 x i16> @pr25080(<8 x i32> %a) {
; LE-NEXT: xxsldwi 1, 34, 34, 1
; LE-NEXT: mfvsrwz 4, 35
; LE-NEXT: xxsldwi 4, 34, 34, 3
; LE-NEXT: mtvsrd 2, 3
; LE-NEXT: mfvsrwz 3, 0
; LE-NEXT: mtfprd 2, 3
; LE-NEXT: mffprwz 3, 0
; LE-NEXT: xxswapd 0, 35
; LE-NEXT: mtvsrd 3, 4
; LE-NEXT: mtfprd 3, 4
; LE-NEXT: xxsldwi 5, 35, 35, 1
; LE-NEXT: mfvsrwz 4, 1
; LE-NEXT: mffprwz 4, 1
; LE-NEXT: xxsldwi 7, 35, 35, 3
; LE-NEXT: mtvsrd 1, 3
; LE-NEXT: mtfprd 1, 3
; LE-NEXT: xxswapd 33, 3
; LE-NEXT: mfvsrwz 3, 4
; LE-NEXT: mtvsrd 4, 4
; LE-NEXT: mffprwz 3, 4
; LE-NEXT: mtfprd 4, 4
; LE-NEXT: xxswapd 34, 1
; LE-NEXT: mfvsrwz 4, 0
; LE-NEXT: mtvsrd 0, 3
; LE-NEXT: mffprwz 4, 0
; LE-NEXT: mtfprd 0, 3
; LE-NEXT: xxswapd 35, 4
; LE-NEXT: mfvsrwz 3, 5
; LE-NEXT: mtvsrd 6, 4
; LE-NEXT: mffprwz 3, 5
; LE-NEXT: mtfprd 6, 4
; LE-NEXT: xxswapd 36, 0
; LE-NEXT: mtvsrd 1, 3
; LE-NEXT: mfvsrwz 3, 7
; LE-NEXT: mtfprd 1, 3
; LE-NEXT: mffprwz 3, 7
; LE-NEXT: xxswapd 37, 6
; LE-NEXT: vmrglh 2, 3, 2
; LE-NEXT: xxswapd 35, 2
; LE-NEXT: mtvsrd 2, 3
; LE-NEXT: mtfprd 2, 3
; LE-NEXT: xxswapd 32, 1
; LE-NEXT: addis 3, 2, .LCPI0_1@toc@ha
; LE-NEXT: addi 3, 3, .LCPI0_1@toc@l
@ -73,29 +73,29 @@ define <8 x i16> @pr25080(<8 x i32> %a) {
; BE-NEXT: mfvsrwz 3, 35
; BE-NEXT: xxsldwi 1, 35, 35, 1
; BE-NEXT: sldi 3, 3, 48
; BE-NEXT: mfvsrwz 4, 0
; BE-NEXT: mffprwz 4, 0
; BE-NEXT: xxsldwi 0, 35, 35, 3
; BE-NEXT: mtvsrd 36, 3
; BE-NEXT: mfvsrwz 3, 1
; BE-NEXT: mffprwz 3, 1
; BE-NEXT: sldi 4, 4, 48
; BE-NEXT: xxswapd 1, 34
; BE-NEXT: mtvsrd 35, 4
; BE-NEXT: mfvsrwz 4, 34
; BE-NEXT: sldi 3, 3, 48
; BE-NEXT: mtvsrd 37, 3
; BE-NEXT: mfvsrwz 3, 0
; BE-NEXT: mffprwz 3, 0
; BE-NEXT: sldi 4, 4, 48
; BE-NEXT: xxsldwi 0, 34, 34, 1
; BE-NEXT: vmrghh 3, 5, 3
; BE-NEXT: mtvsrd 37, 4
; BE-NEXT: sldi 3, 3, 48
; BE-NEXT: mfvsrwz 4, 1
; BE-NEXT: mffprwz 4, 1
; BE-NEXT: xxsldwi 1, 34, 34, 3
; BE-NEXT: mtvsrd 34, 3
; BE-NEXT: mfvsrwz 3, 0
; BE-NEXT: mffprwz 3, 0
; BE-NEXT: sldi 4, 4, 48
; BE-NEXT: mtvsrd 32, 4
; BE-NEXT: mfvsrwz 4, 1
; BE-NEXT: mffprwz 4, 1
; BE-NEXT: sldi 3, 3, 48
; BE-NEXT: mtvsrd 33, 3
; BE-NEXT: sldi 3, 4, 48

4
test/CodeGen/PowerPC/pr33093.ll
View File

@ -115,8 +115,8 @@ define i64 @ReverseBits64(i64 %n) {
; CHECK-NEXT: and 3, 3, 4
; CHECK-NEXT: or 3, 3, 5
; CHECK-NEXT: rldicl 4, 3, 32, 32
; CHECK-NEXT: rlwinm 5, 3, 24, 0, 31
; CHECK-NEXT: rlwinm 6, 4, 24, 0, 31
; CHECK-NEXT: rotlwi 5, 3, 24
; CHECK-NEXT: rotlwi 6, 4, 24
; CHECK-NEXT: rlwimi 5, 3, 8, 8, 15
; CHECK-NEXT: rlwimi 5, 3, 8, 24, 31
; CHECK-NEXT: rlwimi 6, 4, 8, 8, 15

4
test/CodeGen/PowerPC/pr35688.ll
View File

@ -13,7 +13,7 @@ define void @ec_GFp_nistp256_points_mul() {
; CHECK: subfze 6, 4
; CHECK: sradi 7, 6, 63
; CHECK: srad 6, 6, 3
; CHECK: subfc 5, 5, 7
; CHECK: subc 5, 7, 5
; CHECK: subfe 5, 4, 6
; CHECK: sradi 5, 5, 63
@ -25,7 +25,7 @@ define void @ec_GFp_nistp256_points_mul() {
; MSSA: subfic 5, 3, 0
; MSSA: subfze 5, 4
; MSSA: sradi 5, 5, 63
; MSSA: subfc 3, 3, 5
; MSSA: subc 3, 5, 3
; MSSA: subfe 3, 4, 5
; MSSA: sradi 3, 3, 63
; MSSA: std 3, 0(3)

2
test/CodeGen/PowerPC/pr45448.ll
View File

@ -26,7 +26,7 @@ define hidden void @julia_tryparse_internal_45896() #0 {
; CHECK-NEXT: sradi r4, r3, 63
; CHECK-NEXT: mulhdu r3, r3, r5
; CHECK-NEXT: maddld r6, r4, r5, r3
; CHECK-NEXT: crnor 4*cr5+gt, eq, eq
; CHECK-NEXT: crnot 4*cr5+gt, eq
; CHECK-NEXT: cmpld r6, r3
; CHECK-NEXT: mulld r3, r4, r5
; CHECK-NEXT: cmpldi cr1, r3, 0

12
test/CodeGen/PowerPC/pre-inc-disable.ll
View File

@ -361,7 +361,7 @@ define void @test16(i16* nocapture readonly %sums, i32 signext %delta, i32 signe
; CHECK-NEXT: lxsihzx v2, r6, r7
; CHECK-NEXT: lxsihzx v4, r3, r4
; CHECK-NEXT: li r6, 0
; CHECK-NEXT: mtvsrd f0, r6
; CHECK-NEXT: mtfprd f0, r6
; CHECK-NEXT: vsplth v4, v4, 3
; CHECK-NEXT: xxswapd v3, vs0
; CHECK-NEXT: vsplth v2, v2, 3
@ -377,7 +377,7 @@ define void @test16(i16* nocapture readonly %sums, i32 signext %delta, i32 signe
; CHECK-NEXT: xxspltw v3, v2, 2
; CHECK-NEXT: vadduwm v2, v2, v3
; CHECK-NEXT: vextuwrx r3, r3, v2
; CHECK-NEXT: cmpw cr0, r3, r5
; CHECK-NEXT: cmpw r3, r5
; CHECK-NEXT: bgelr+ cr0
; CHECK-NEXT: # %bb.1: # %if.then
;
@ -405,7 +405,7 @@ define void @test16(i16* nocapture readonly %sums, i32 signext %delta, i32 signe
; P9BE-NEXT: xxspltw v3, v2, 1
; P9BE-NEXT: vadduwm v2, v2, v3
; P9BE-NEXT: vextuwlx r3, r3, v2
; P9BE-NEXT: cmpw cr0, r3, r5
; P9BE-NEXT: cmpw r3, r5
; P9BE-NEXT: bgelr+ cr0
; P9BE-NEXT: # %bb.1: # %if.then
entry:
@ -446,7 +446,7 @@ define void @test8(i8* nocapture readonly %sums, i32 signext %delta, i32 signext
; CHECK-NEXT: add r6, r3, r4
; CHECK-NEXT: lxsibzx v2, r3, r4
; CHECK-NEXT: li r3, 0
; CHECK-NEXT: mtvsrd f0, r3
; CHECK-NEXT: mtfprd f0, r3
; CHECK-NEXT: li r3, 8
; CHECK-NEXT: lxsibzx v5, r6, r3
; CHECK-NEXT: xxswapd v3, vs0
@ -467,7 +467,7 @@ define void @test8(i8* nocapture readonly %sums, i32 signext %delta, i32 signext
; CHECK-NEXT: xxspltw v3, v2, 2
; CHECK-NEXT: vadduwm v2, v2, v3
; CHECK-NEXT: vextuwrx r3, r3, v2
; CHECK-NEXT: cmpw cr0, r3, r5
; CHECK-NEXT: cmpw r3, r5
; CHECK-NEXT: bgelr+ cr0
; CHECK-NEXT: # %bb.1: # %if.then
;
@ -496,7 +496,7 @@ define void @test8(i8* nocapture readonly %sums, i32 signext %delta, i32 signext
; P9BE-NEXT: xxspltw v3, v2, 1
; P9BE-NEXT: vadduwm v2, v2, v3
; P9BE-NEXT: vextuwlx r3, r3, v2
; P9BE-NEXT: cmpw cr0, r3, r5
; P9BE-NEXT: cmpw r3, r5
; P9BE-NEXT: bgelr+ cr0
; P9BE-NEXT: # %bb.1: # %if.then
entry:

2
test/CodeGen/PowerPC/qpx-s-sel.ll
View File

@ -56,7 +56,7 @@ entry:
; CHECK-DAG: qvlfiwzx [[REG2:[0-9]+]],
; CHECK-DAG: qvfcfidu [[REG3:[0-9]+]], [[REG2]]
; CHECK: qvfcmpeq [[REG4:[0-9]+]], [[REG3]], [[REG1]]
; CHECK: qvflogical 1, 1, [[REG4]], 1
; CHECK: qvfand 1, 1, [[REG4]]
; CHECK: blr
}

2
test/CodeGen/PowerPC/qpx-sel.ll
View File

@ -60,7 +60,7 @@ entry:
; CHECK-DAG: qvlfiwzx [[REG2:[0-9]+]],
; CHECK-DAG: qvfcfidu [[REG3:[0-9]+]], [[REG2]]
; CHECK: qvfcmpeq [[REG4:[0-9]+]], [[REG3]], [[REG1]]
; CHECK: qvflogical 1, 1, [[REG4]], 1
; CHECK: qvfand 1, 1, [[REG4]]
; CHECK: blr
}

2
test/CodeGen/PowerPC/redundant-copy-after-tail-dup.ll
View File

@ -29,7 +29,7 @@ define dso_local i1 @t(%class.A* %this, i32 %color, i32 %vertex) local_unnamed_a
; CHECK-P9-NEXT: li r3, 0
; CHECK-P9-NEXT: blr
; CHECK-P9-NEXT: .LBB0_4: # %lor.lhs.false
; CHECK-P9-NEXT: cmplwi cr0, r4, 0
; CHECK-P9-NEXT: cmplwi r4, 0
; CHECK-P9-NEXT: bne cr0, .LBB0_2
; CHECK-P9-NEXT: .LBB0_5: # %cleanup16
; CHECK-P9-NEXT: mr r3, r5

18
test/CodeGen/PowerPC/sat-add.ll
View File

@ -24,7 +24,7 @@ define i8 @unsigned_sat_constant_i8_using_min(i8 %x) {
define i8 @unsigned_sat_constant_i8_using_cmp_sum(i8 %x) {
; CHECK-LABEL: unsigned_sat_constant_i8_using_cmp_sum:
; CHECK: # %bb.0:
; CHECK-NEXT: rlwinm 3, 3, 0, 24, 31
; CHECK-NEXT: clrlwi 3, 3, 24
; CHECK-NEXT: addi 3, 3, 42
; CHECK-NEXT: andi. 4, 3, 256
; CHECK-NEXT: li 4, -1
@ -69,7 +69,7 @@ define i16 @unsigned_sat_constant_i16_using_min(i16 %x) {
define i16 @unsigned_sat_constant_i16_using_cmp_sum(i16 %x) {
; CHECK-LABEL: unsigned_sat_constant_i16_using_cmp_sum:
; CHECK: # %bb.0:
; CHECK-NEXT: rlwinm 3, 3, 0, 16, 31
; CHECK-NEXT: clrlwi 3, 3, 16
; CHECK-NEXT: addi 3, 3, 42
; CHECK-NEXT: andis. 4, 3, 1
; CHECK-NEXT: li 4, -1
@ -115,7 +115,7 @@ define i32 @unsigned_sat_constant_i32_using_cmp_sum(i32 %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi 5, 3, 42
; CHECK-NEXT: li 4, -1
; CHECK-NEXT: cmplw 0, 5, 3
; CHECK-NEXT: cmplw 5, 3
; CHECK-NEXT: isel 3, 4, 5, 0
; CHECK-NEXT: blr
%a = add i32 %x, 42
@ -129,7 +129,7 @@ define i32 @unsigned_sat_constant_i32_using_cmp_notval(i32 %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: li 4, -43
; CHECK-NEXT: addi 5, 3, 42
; CHECK-NEXT: cmplw 0, 3, 4
; CHECK-NEXT: cmplw 3, 4
; CHECK-NEXT: li 3, -1
; CHECK-NEXT: isel 3, 3, 5, 1
; CHECK-NEXT: blr
@ -202,8 +202,8 @@ define i8 @unsigned_sat_variable_i8_using_min(i8 %x, i8 %y) {
define i8 @unsigned_sat_variable_i8_using_cmp_sum(i8 %x, i8 %y) {
; CHECK-LABEL: unsigned_sat_variable_i8_using_cmp_sum:
; CHECK: # %bb.0:
; CHECK-NEXT: rlwinm 4, 4, 0, 24, 31
; CHECK-NEXT: rlwinm 3, 3, 0, 24, 31
; CHECK-NEXT: clrlwi 4, 4, 24
; CHECK-NEXT: clrlwi 3, 3, 24
; CHECK-NEXT: add 3, 3, 4
; CHECK-NEXT: andi. 4, 3, 256
; CHECK-NEXT: li 4, -1
@ -253,8 +253,8 @@ define i16 @unsigned_sat_variable_i16_using_min(i16 %x, i16 %y) {
define i16 @unsigned_sat_variable_i16_using_cmp_sum(i16 %x, i16 %y) {
; CHECK-LABEL: unsigned_sat_variable_i16_using_cmp_sum:
; CHECK: # %bb.0:
; CHECK-NEXT: rlwinm 4, 4, 0, 16, 31
; CHECK-NEXT: rlwinm 3, 3, 0, 16, 31
; CHECK-NEXT: clrlwi 4, 4, 16
; CHECK-NEXT: clrlwi 3, 3, 16
; CHECK-NEXT: add 3, 3, 4
; CHECK-NEXT: andis. 4, 3, 1
; CHECK-NEXT: li 4, -1
@ -304,7 +304,7 @@ define i32 @unsigned_sat_variable_i32_using_cmp_sum(i32 %x, i32 %y) {
; CHECK: # %bb.0:
; CHECK-NEXT: add 4, 3, 4
; CHECK-NEXT: li 5, -1
; CHECK-NEXT: cmplw 0, 4, 3
; CHECK-NEXT: cmplw 4, 3
; CHECK-NEXT: isel 3, 5, 4, 0
; CHECK-NEXT: blr
%a = add i32 %x, %y

20
test/CodeGen/PowerPC/select-i1-vs-i1.ll
View File

@ -18,7 +18,7 @@ entry:
; CHECK-LABEL: @testi32slt
; CHECK-NO-ISEL-LABEL: @testi32slt
; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
; CHECK-DAG: cmpw 5, 6
; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
; CHECK: isel 3, 7, 8, [[REG1]]
@ -40,7 +40,7 @@ entry:
ret i32 %cond
; CHECK-NO-ISEL-LABEL: @testi32ult
; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
; CHECK-DAG: cmpw 5, 6
; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
; CHECK: isel 3, 7, 8, [[REG1]]
@ -63,7 +63,7 @@ entry:
; CHECK-LABEL: @testi32sle
; CHECK-NO-ISEL-LABEL: @testi32sle
; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
; CHECK-DAG: cmpw 5, 6
; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
; CHECK: isel 3, 7, 8, [[REG1]]
@ -86,7 +86,7 @@ entry:
; CHECK-LABEL: @testi32ule
; CHECK-NO-ISEL-LABEL: @testi32ule
; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
; CHECK-DAG: cmpw 5, 6
; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
; CHECK: isel 3, 7, 8, [[REG1]]
@ -109,7 +109,7 @@ entry:
; CHECK-LABEL: @testi32eq
; CHECK-NO-ISEL-LABEL: @testi32eq
; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
; CHECK-DAG: cmpw 5, 6
; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
; CHECK: isel 3, 7, 8, [[REG1]]
@ -132,7 +132,7 @@ entry:
; CHECK-LABEL: @testi32sge
; CHECK-NO-ISEL-LABEL: @testi32sge
; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
; CHECK-DAG: cmpw 5, 6
; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
; CHECK: isel 3, 7, 8, [[REG1]]
@ -155,7 +155,7 @@ entry:
; CHECK-LABEL: @testi32uge
; CHECK-NO-ISEL-LABEL: @testi32uge
; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
; CHECK-DAG: cmpw 5, 6
; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
; CHECK: isel 3, 7, 8, [[REG1]]
@ -178,7 +178,7 @@ entry:
; CHECK-LABEL: @testi32sgt
; CHECK-NO-ISEL-LABEL: @testi32sgt
; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
; CHECK-DAG: cmpw 5, 6
; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
; CHECK: isel 3, 7, 8, [[REG1]]
@ -201,7 +201,7 @@ entry:
; CHECK-LABEL: @testi32ugt
; CHECK-NO-ISEL-LABEL: @testi32ugt
; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
; CHECK-DAG: cmpw 5, 6
; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
; CHECK: isel 3, 7, 8, [[REG1]]
@ -224,7 +224,7 @@ entry:
; CHECK-LABEL: @testi32ne
; CHECK-NO-ISEL-LABEL: @testi32ne
; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
; CHECK-DAG: cmpw 5, 6
; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
; CHECK: isel 3, 7, 8, [[REG1]]

6
test/CodeGen/PowerPC/select_const.ll
View File

@ -614,7 +614,7 @@ define i8 @sel_constants_shl_constant(i1 %cond) {
define i8 @shl_constant_sel_constants(i1 %cond) {
; ALL-LABEL: shl_constant_sel_constants:
; ALL: # %bb.0:
; ALL-NEXT: rlwinm 3, 3, 0, 31, 31
; ALL-NEXT: clrlwi 3, 3, 31
; ALL-NEXT: li 4, 1
; ALL-NEXT: subfic 3, 3, 3
; ALL-NEXT: slw 3, 4, 3
@ -651,7 +651,7 @@ define i8 @sel_constants_lshr_constant(i1 %cond) {
define i8 @lshr_constant_sel_constants(i1 %cond) {
; ALL-LABEL: lshr_constant_sel_constants:
; ALL: # %bb.0:
; ALL-NEXT: rlwinm 3, 3, 0, 31, 31
; ALL-NEXT: clrlwi 3, 3, 31
; ALL-NEXT: li 4, 64
; ALL-NEXT: subfic 3, 3, 3
; ALL-NEXT: srw 3, 4, 3
@ -676,7 +676,7 @@ define i8 @sel_constants_ashr_constant(i1 %cond) {
define i8 @ashr_constant_sel_constants(i1 %cond) {
; ALL-LABEL: ashr_constant_sel_constants:
; ALL: # %bb.0:
; ALL-NEXT: rlwinm 3, 3, 0, 31, 31
; ALL-NEXT: clrlwi 3, 3, 31
; ALL-NEXT: li 4, -128
; ALL-NEXT: subfic 3, 3, 3
; ALL-NEXT: sraw 3, 4, 3

12
test/CodeGen/PowerPC/setcc-logic.ll
View File

@ -138,7 +138,7 @@ define i32 @all_sign_bits_clear_branch(i32 %P, i32 %Q) {
; CHECK-LABEL: all_sign_bits_clear_branch:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: or 3, 3, 4
; CHECK-NEXT: cmpwi 0, 3, 0
; CHECK-NEXT: cmpwi 3, 0
; CHECK-NEXT: blt 0, .LBB9_2
; CHECK-NEXT: # %bb.1: # %bb1
; CHECK-NEXT: li 3, 4
@ -163,7 +163,7 @@ define i32 @all_bits_set_branch(i32 %P, i32 %Q) {
; CHECK-LABEL: all_bits_set_branch:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: and 3, 3, 4
; CHECK-NEXT: cmpwi 0, 3, -1
; CHECK-NEXT: cmpwi 3, -1
; CHECK-NEXT: bne 0, .LBB10_2
; CHECK-NEXT: # %bb.1: # %bb1
; CHECK-NEXT: li 3, 4
@ -188,7 +188,7 @@ define i32 @all_sign_bits_set_branch(i32 %P, i32 %Q) {
; CHECK-LABEL: all_sign_bits_set_branch:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: and 3, 3, 4
; CHECK-NEXT: cmpwi 0, 3, -1
; CHECK-NEXT: cmpwi 3, -1
; CHECK-NEXT: bgt 0, .LBB11_2
; CHECK-NEXT: # %bb.1: # %bb1
; CHECK-NEXT: li 3, 4
@ -238,7 +238,7 @@ define i32 @any_sign_bits_set_branch(i32 %P, i32 %Q) {
; CHECK-LABEL: any_sign_bits_set_branch:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: or 3, 3, 4
; CHECK-NEXT: cmpwi 0, 3, -1
; CHECK-NEXT: cmpwi 3, -1
; CHECK-NEXT: bgt 0, .LBB13_2
; CHECK-NEXT: # %bb.1: # %bb1
; CHECK-NEXT: li 3, 4
@ -263,7 +263,7 @@ define i32 @any_bits_clear_branch(i32 %P, i32 %Q) {
; CHECK-LABEL: any_bits_clear_branch:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: and 3, 3, 4
; CHECK-NEXT: cmpwi 0, 3, -1
; CHECK-NEXT: cmpwi 3, -1
; CHECK-NEXT: beq 0, .LBB14_2
; CHECK-NEXT: # %bb.1: # %bb1
; CHECK-NEXT: li 3, 4
@ -288,7 +288,7 @@ define i32 @any_sign_bits_clear_branch(i32 %P, i32 %Q) {
; CHECK-LABEL: any_sign_bits_clear_branch:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: and 3, 3, 4
; CHECK-NEXT: cmpwi 0, 3, 0
; CHECK-NEXT: cmpwi 3, 0
; CHECK-NEXT: blt 0, .LBB15_2
; CHECK-NEXT: # %bb.1: # %bb1
; CHECK-NEXT: li 3, 4

28
test/CodeGen/PowerPC/shift_mask.ll
View File

@ -5,7 +5,7 @@ target triple = "powerpc64le-linux-gnu"
define i8 @test000(i8 %a, i8 %b) {
; CHECK-LABEL: test000:
; CHECK: # %bb.0:
; CHECK-NEXT: rlwinm 4, 4, 0, 29, 31
; CHECK-NEXT: clrlwi 4, 4, 29
; CHECK-NEXT: slw 3, 3, 4
; CHECK-NEXT: blr
%rem = and i8 %b, 7
@ -16,7 +16,7 @@ define i8 @test000(i8 %a, i8 %b) {
define i16 @test001(i16 %a, i16 %b) {
; CHECK-LABEL: test001:
; CHECK: # %bb.0:
; CHECK-NEXT: rlwinm 4, 4, 0, 28, 31
; CHECK-NEXT: clrlwi 4, 4, 28
; CHECK-NEXT: slw 3, 3, 4
; CHECK-NEXT: blr
%rem = and i16 %b, 15
@ -27,7 +27,7 @@ define i16 @test001(i16 %a, i16 %b) {
define i32 @test002(i32 %a, i32 %b) {
; CHECK-LABEL: test002:
; CHECK: # %bb.0:
; CHECK-NEXT: rlwinm 4, 4, 0, 27, 31
; CHECK-NEXT: clrlwi 4, 4, 27
; CHECK-NEXT: slw 3, 3, 4
; CHECK-NEXT: blr
%rem = and i32 %b, 31
@ -38,7 +38,7 @@ define i32 @test002(i32 %a, i32 %b) {
define i64 @test003(i64 %a, i64 %b) {
; CHECK-LABEL: test003:
; CHECK: # %bb.0:
; CHECK-NEXT: rlwinm 4, 4, 0, 26, 31
; CHECK-NEXT: clrlwi 4, 4, 26
; CHECK-NEXT: sld 3, 3, 4
; CHECK-NEXT: blr
%rem = and i64 %b, 63
@ -89,8 +89,8 @@ define <2 x i64> @test013(<2 x i64> %a, <2 x i64> %b) {
define i8 @test100(i8 %a, i8 %b) {
; CHECK-LABEL: test100:
; CHECK: # %bb.0:
; CHECK-NEXT: rlwinm 3, 3, 0, 24, 31
; CHECK-NEXT: rlwinm 4, 4, 0, 29, 31
; CHECK-NEXT: clrlwi 3, 3, 24
; CHECK-NEXT: clrlwi 4, 4, 29
; CHECK-NEXT: srw 3, 3, 4
; CHECK-NEXT: blr
%rem = and i8 %b, 7
@ -101,8 +101,8 @@ define i8 @test100(i8 %a, i8 %b) {
define i16 @test101(i16 %a, i16 %b) {
; CHECK-LABEL: test101:
; CHECK: # %bb.0:
; CHECK-NEXT: rlwinm 3, 3, 0, 16, 31
; CHECK-NEXT: rlwinm 4, 4, 0, 28, 31
; CHECK-NEXT: clrlwi 3, 3, 16
; CHECK-NEXT: clrlwi 4, 4, 28
; CHECK-NEXT: srw 3, 3, 4
; CHECK-NEXT: blr
%rem = and i16 %b, 15
@ -113,7 +113,7 @@ define i16 @test101(i16 %a, i16 %b) {
define i32 @test102(i32 %a, i32 %b) {
; CHECK-LABEL: test102:
; CHECK: # %bb.0:
; CHECK-NEXT: rlwinm 4, 4, 0, 27, 31
; CHECK-NEXT: clrlwi 4, 4, 27
; CHECK-NEXT: srw 3, 3, 4
; CHECK-NEXT: blr
%rem = and i32 %b, 31
@ -124,7 +124,7 @@ define i32 @test102(i32 %a, i32 %b) {
define i64 @test103(i64 %a, i64 %b) {
; CHECK-LABEL: test103:
; CHECK: # %bb.0:
; CHECK-NEXT: rlwinm 4, 4, 0, 26, 31
; CHECK-NEXT: clrlwi 4, 4, 26
; CHECK-NEXT: srd 3, 3, 4
; CHECK-NEXT: blr
%rem = and i64 %b, 63
@ -176,7 +176,7 @@ define i8 @test200(i8 %a, i8 %b) {
; CHECK-LABEL: test200:
; CHECK: # %bb.0:
; CHECK-NEXT: extsb 3, 3
; CHECK-NEXT: rlwinm 4, 4, 0, 29, 31
; CHECK-NEXT: clrlwi 4, 4, 29
; CHECK-NEXT: sraw 3, 3, 4
; CHECK-NEXT: blr
%rem = and i8 %b, 7
@ -188,7 +188,7 @@ define i16 @test201(i16 %a, i16 %b) {
; CHECK-LABEL: test201:
; CHECK: # %bb.0:
; CHECK-NEXT: extsh 3, 3
; CHECK-NEXT: rlwinm 4, 4, 0, 28, 31
; CHECK-NEXT: clrlwi 4, 4, 28
; CHECK-NEXT: sraw 3, 3, 4
; CHECK-NEXT: blr
%rem = and i16 %b, 15
@ -199,7 +199,7 @@ define i16 @test201(i16 %a, i16 %b) {
define i32 @test202(i32 %a, i32 %b) {
; CHECK-LABEL: test202:
; CHECK: # %bb.0:
; CHECK-NEXT: rlwinm 4, 4, 0, 27, 31
; CHECK-NEXT: clrlwi 4, 4, 27
; CHECK-NEXT: sraw 3, 3, 4
; CHECK-NEXT: blr
%rem = and i32 %b, 31
@ -210,7 +210,7 @@ define i32 @test202(i32 %a, i32 %b) {
define i64 @test203(i64 %a, i64 %b) {
; CHECK-LABEL: test203:
; CHECK: # %bb.0:
; CHECK-NEXT: rlwinm 4, 4, 0, 26, 31
; CHECK-NEXT: clrlwi 4, 4, 26
; CHECK-NEXT: srad 3, 3, 4
; CHECK-NEXT: blr
%rem = and i64 %b, 63

8
test/CodeGen/PowerPC/signbit-shift.ll
View File

@ -46,7 +46,7 @@ define i32 @sel_ifpos_tval_bigger(i32 %x) {
; CHECK-LABEL: sel_ifpos_tval_bigger:
; CHECK: # %bb.0:
; CHECK-NEXT: li 4, 41
; CHECK-NEXT: cmpwi 0, 3, -1
; CHECK-NEXT: cmpwi 3, -1
; CHECK-NEXT: li 3, 42
; CHECK-NEXT: isel 3, 3, 4, 1
; CHECK-NEXT: blr
@ -98,7 +98,7 @@ define i32 @sel_ifpos_fval_bigger(i32 %x) {
; CHECK-LABEL: sel_ifpos_fval_bigger:
; CHECK: # %bb.0:
; CHECK-NEXT: li 4, 42
; CHECK-NEXT: cmpwi 0, 3, -1
; CHECK-NEXT: cmpwi 3, -1
; CHECK-NEXT: li 3, 41
; CHECK-NEXT: isel 3, 3, 4, 1
; CHECK-NEXT: blr
@ -135,7 +135,7 @@ define i32 @sel_ifneg_tval_bigger(i32 %x) {
; CHECK-LABEL: sel_ifneg_tval_bigger:
; CHECK: # %bb.0:
; CHECK-NEXT: li 4, 41
; CHECK-NEXT: cmpwi 0, 3, 0
; CHECK-NEXT: cmpwi 3, 0
; CHECK-NEXT: li 3, 42
; CHECK-NEXT: isel 3, 3, 4, 0
; CHECK-NEXT: blr
@ -170,7 +170,7 @@ define i32 @sel_ifneg_fval_bigger(i32 %x) {
; CHECK-LABEL: sel_ifneg_fval_bigger:
; CHECK: # %bb.0:
; CHECK-NEXT: li 4, 42
; CHECK-NEXT: cmpwi 0, 3, 0
; CHECK-NEXT: cmpwi 3, 0
; CHECK-NEXT: li 3, 41
; CHECK-NEXT: isel 3, 3, 4, 0
; CHECK-NEXT: blr

2
test/CodeGen/PowerPC/simplifyConstCmpToISEL.ll
View File

@ -4,7 +4,7 @@
define void @test(i32 zeroext %parts) {
; CHECK-LABEL: test:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmplwi 0, 3, 1
; CHECK-NEXT: cmplwi 3, 1
; CHECK-NEXT: bnelr+ 0
; CHECK-NEXT: # %bb.1: # %test2.exit.us.unr-lcssa
; CHECK-NEXT: ld 3, 0(3)

2
test/CodeGen/PowerPC/sms-cpy-1.ll
View File

@ -13,7 +13,7 @@ define void @print_res() nounwind {
; CHECK-NEXT: lwz 3, 0(3)
; CHECK-NEXT: addi 3, 3, -1
; CHECK-NEXT: clrldi 4, 3, 32
; CHECK-NEXT: cmplwi 0, 3, 1
; CHECK-NEXT: cmplwi 3, 1
; CHECK-NEXT: li 3, 1
; CHECK-NEXT: isel 3, 4, 3, 1
; CHECK-NEXT: li 4, 2

4
test/CodeGen/PowerPC/spill_p9_setb.ll
View File

@ -17,7 +17,7 @@
define void @p9_setb_spill() {
; CHECK-P9-LABEL: p9_setb_spill:
; CHECK-P9: # %bb.1: # %if.then
; CHECK-P9-DAG: crnor 4*cr[[CREG:.*]]+lt, eq, eq
; CHECK-P9-DAG: crnot 4*cr[[CREG:.*]]+lt, eq
; CHECK-P9-DAG: setb [[REG1:.*]], cr[[CREG]]
; CHECK-P9-DAG: stw [[REG1]]
; CHECK-P9: blr
@ -25,7 +25,7 @@ define void @p9_setb_spill() {
;
; CHECK-P8-LABEL: p9_setb_spill:
; CHECK-P8: # %bb.1: # %if.then
; CHECK-P8-DAG: crnor 4*cr[[CREG2:.*]]+lt, eq, eq
; CHECK-P8-DAG: crnot 4*cr[[CREG2:.*]]+lt, eq
; CHECK-P8-DAG: mfocrf [[REG2:.*]],
; CHECK-P8-DAG: rlwinm [[REG2]], [[REG2]]
; CHECK-P8-DAG: stw [[REG2]]

138
test/CodeGen/PowerPC/srem-vector-lkk.ll
View File

@ -26,7 +26,7 @@ define <4 x i16> @fold_srem_vec_1(<4 x i16> %x) {
; P9LE-NEXT: lis r5, 31710
; P9LE-NEXT: mulli r4, r4, 95
; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: mtvsrd f0, r3
; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 2
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: extsh r4, r3
@ -42,7 +42,7 @@ define <4 x i16> @fold_srem_vec_1(<4 x i16> %x) {
; P9LE-NEXT: mulli r4, r4, -124
; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: xxswapd v3, vs0
; P9LE-NEXT: mtvsrd f0, r3
; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 4
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: extsh r4, r3
@ -57,7 +57,7 @@ define <4 x i16> @fold_srem_vec_1(<4 x i16> %x) {
; P9LE-NEXT: mulli r4, r4, 98
; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: xxswapd v4, vs0
; P9LE-NEXT: mtvsrd f0, r3
; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 6
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: extsh r4, r3
@ -72,7 +72,7 @@ define <4 x i16> @fold_srem_vec_1(<4 x i16> %x) {
; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: vmrglh v3, v4, v3
; P9LE-NEXT: xxswapd v4, vs0
; P9LE-NEXT: mtvsrd f0, r3
; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: xxswapd v2, vs0
; P9LE-NEXT: vmrglh v2, v2, v4
; P9LE-NEXT: vmrglw v2, v2, v3
@ -157,7 +157,7 @@ define <4 x i16> @fold_srem_vec_1(<4 x i16> %x) {
; P8LE-NEXT: ori r4, r4, 33437
; P8LE-NEXT: ori r9, r9, 63249
; P8LE-NEXT: ori r11, r11, 37253
; P8LE-NEXT: mfvsrd r5, f0
; P8LE-NEXT: mffprd r5, f0
; P8LE-NEXT: rldicl r3, r5, 32, 48
; P8LE-NEXT: rldicl r6, r5, 16, 48
; P8LE-NEXT: clrldi r7, r5, 48
@ -201,13 +201,13 @@ define <4 x i16> @fold_srem_vec_1(<4 x i16> %x) {
; P8LE-NEXT: mulli r8, r8, -124
; P8LE-NEXT: subf r3, r4, r3
; P8LE-NEXT: subf r4, r9, r6
; P8LE-NEXT: mtvsrd f0, r3
; P8LE-NEXT: mtfprd f0, r3
; P8LE-NEXT: subf r3, r10, r7
; P8LE-NEXT: mtvsrd f1, r4
; P8LE-NEXT: mtfprd f1, r4
; P8LE-NEXT: subf r4, r8, r5
; P8LE-NEXT: mtvsrd f2, r3
; P8LE-NEXT: mtfprd f2, r3
; P8LE-NEXT: xxswapd v2, vs0
; P8LE-NEXT: mtvsrd f3, r4
; P8LE-NEXT: mtfprd f3, r4
; P8LE-NEXT: xxswapd v3, vs1
; P8LE-NEXT: xxswapd v4, vs2
; P8LE-NEXT: xxswapd v5, vs3
@ -302,7 +302,7 @@ define <4 x i16> @fold_srem_vec_2(<4 x i16> %x) {
; P9LE-NEXT: add r4, r4, r6
; P9LE-NEXT: mulli r4, r4, 95
; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: mtvsrd f0, r3
; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 2
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: extsh r4, r3
@ -316,7 +316,7 @@ define <4 x i16> @fold_srem_vec_2(<4 x i16> %x) {
; P9LE-NEXT: mulli r4, r4, 95
; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: xxswapd v3, vs0
; P9LE-NEXT: mtvsrd f0, r3
; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 4
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: extsh r4, r3
@ -330,7 +330,7 @@ define <4 x i16> @fold_srem_vec_2(<4 x i16> %x) {
; P9LE-NEXT: mulli r4, r4, 95
; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: xxswapd v4, vs0
; P9LE-NEXT: mtvsrd f0, r3
; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 6
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: extsh r4, r3
@ -345,7 +345,7 @@ define <4 x i16> @fold_srem_vec_2(<4 x i16> %x) {
; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: vmrglh v3, v4, v3
; P9LE-NEXT: xxswapd v4, vs0
; P9LE-NEXT: mtvsrd f0, r3
; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: xxswapd v2, vs0
; P9LE-NEXT: vmrglh v2, v2, v4
; P9LE-NEXT: vmrglw v2, v2, v3
@ -422,7 +422,7 @@ define <4 x i16> @fold_srem_vec_2(<4 x i16> %x) {
; P8LE-NEXT: lis r4, -21386
; P8LE-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; P8LE-NEXT: ori r4, r4, 37253
; P8LE-NEXT: mfvsrd r5, f0
; P8LE-NEXT: mffprd r5, f0
; P8LE-NEXT: clrldi r3, r5, 48
; P8LE-NEXT: rldicl r7, r5, 32, 48
; P8LE-NEXT: extsh r8, r3
@ -466,13 +466,13 @@ define <4 x i16> @fold_srem_vec_2(<4 x i16> %x) {
; P8LE-NEXT: mulli r4, r4, 95
; P8LE-NEXT: subf r3, r8, r3
; P8LE-NEXT: subf r6, r9, r6
; P8LE-NEXT: mtvsrd f0, r3
; P8LE-NEXT: mtfprd f0, r3
; P8LE-NEXT: subf r3, r10, r7
; P8LE-NEXT: subf r4, r4, r5
; P8LE-NEXT: mtvsrd f1, r6
; P8LE-NEXT: mtvsrd f2, r3
; P8LE-NEXT: mtfprd f1, r6
; P8LE-NEXT: mtfprd f2, r3
; P8LE-NEXT: xxswapd v2, vs0
; P8LE-NEXT: mtvsrd f3, r4
; P8LE-NEXT: mtfprd f3, r4
; P8LE-NEXT: xxswapd v3, vs1
; P8LE-NEXT: xxswapd v4, vs2
; P8LE-NEXT: xxswapd v5, vs3
@ -565,7 +565,7 @@ define <4 x i16> @combine_srem_sdiv(<4 x i16> %x) {
; P9LE-NEXT: add r4, r4, r6
; P9LE-NEXT: mulli r6, r4, 95
; P9LE-NEXT: subf r3, r6, r3
; P9LE-NEXT: mtvsrd f0, r3
; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 2
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: extsh r6, r3
@ -579,7 +579,7 @@ define <4 x i16> @combine_srem_sdiv(<4 x i16> %x) {
; P9LE-NEXT: mulli r7, r6, 95
; P9LE-NEXT: subf r3, r7, r3
; P9LE-NEXT: xxswapd v3, vs0
; P9LE-NEXT: mtvsrd f0, r3
; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 4
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: extsh r7, r3
@ -593,7 +593,7 @@ define <4 x i16> @combine_srem_sdiv(<4 x i16> %x) {
; P9LE-NEXT: mulli r8, r7, 95
; P9LE-NEXT: subf r3, r8, r3
; P9LE-NEXT: xxswapd v4, vs0
; P9LE-NEXT: mtvsrd f0, r3
; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 6
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: extsh r8, r3
@ -608,18 +608,18 @@ define <4 x i16> @combine_srem_sdiv(<4 x i16> %x) {
; P9LE-NEXT: subf r3, r8, r3
; P9LE-NEXT: vmrglh v3, v4, v3
; P9LE-NEXT: xxswapd v4, vs0
; P9LE-NEXT: mtvsrd f0, r3
; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: xxswapd v2, vs0
; P9LE-NEXT: mtvsrd f0, r4
; P9LE-NEXT: mtfprd f0, r4
; P9LE-NEXT: vmrglh v2, v2, v4
; P9LE-NEXT: vmrglw v2, v2, v3
; P9LE-NEXT: xxswapd v3, vs0
; P9LE-NEXT: mtvsrd f0, r6
; P9LE-NEXT: mtfprd f0, r6
; P9LE-NEXT: xxswapd v4, vs0
; P9LE-NEXT: mtvsrd f0, r7
; P9LE-NEXT: mtfprd f0, r7
; P9LE-NEXT: vmrglh v3, v4, v3
; P9LE-NEXT: xxswapd v4, vs0
; P9LE-NEXT: mtvsrd f0, r5
; P9LE-NEXT: mtfprd f0, r5
; P9LE-NEXT: xxswapd v5, vs0
; P9LE-NEXT: vmrglh v4, v5, v4
; P9LE-NEXT: vmrglw v3, v4, v3
@ -709,7 +709,7 @@ define <4 x i16> @combine_srem_sdiv(<4 x i16> %x) {
; P8LE-NEXT: lis r5, -21386
; P8LE-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; P8LE-NEXT: ori r5, r5, 37253
; P8LE-NEXT: mfvsrd r6, f0
; P8LE-NEXT: mffprd r6, f0
; P8LE-NEXT: clrldi r3, r6, 48
; P8LE-NEXT: rldicl r4, r6, 48, 48
; P8LE-NEXT: rldicl r7, r6, 32, 48
@ -745,28 +745,28 @@ define <4 x i16> @combine_srem_sdiv(<4 x i16> %x) {
; P8LE-NEXT: add r9, r0, r9
; P8LE-NEXT: mulli r0, r8, 95
; P8LE-NEXT: add r10, r12, r10
; P8LE-NEXT: mtvsrd f0, r8
; P8LE-NEXT: mtfprd f0, r8
; P8LE-NEXT: srwi r8, r5, 31
; P8LE-NEXT: srawi r5, r5, 6
; P8LE-NEXT: mulli r11, r9, 95
; P8LE-NEXT: mtvsrd f1, r9
; P8LE-NEXT: mtfprd f1, r9
; P8LE-NEXT: mulli r9, r10, 95
; P8LE-NEXT: add r5, r5, r8
; P8LE-NEXT: xxswapd v2, vs0
; P8LE-NEXT: mtvsrd f2, r10
; P8LE-NEXT: mtvsrd f3, r5
; P8LE-NEXT: mtfprd f2, r10
; P8LE-NEXT: mtfprd f3, r5
; P8LE-NEXT: mulli r5, r5, 95
; P8LE-NEXT: xxswapd v3, vs1
; P8LE-NEXT: subf r3, r0, r3
; P8LE-NEXT: xxswapd v1, vs2
; P8LE-NEXT: mtvsrd f0, r3
; P8LE-NEXT: mtfprd f0, r3
; P8LE-NEXT: subf r4, r11, r4
; P8LE-NEXT: xxswapd v6, vs3
; P8LE-NEXT: subf r3, r9, r7
; P8LE-NEXT: mtvsrd f1, r4
; P8LE-NEXT: mtvsrd f4, r3
; P8LE-NEXT: mtfprd f1, r4
; P8LE-NEXT: mtfprd f4, r3
; P8LE-NEXT: subf r3, r5, r6
; P8LE-NEXT: mtvsrd f5, r3
; P8LE-NEXT: mtfprd f5, r3
; P8LE-NEXT: xxswapd v4, vs1
; P8LE-NEXT: vmrglh v2, v3, v2
; P8LE-NEXT: xxswapd v3, vs0
@ -870,7 +870,7 @@ define <4 x i16> @dont_fold_srem_power_of_two(<4 x i16> %x) {
; P9LE-NEXT: addze r4, r4
; P9LE-NEXT: slwi r4, r4, 6
; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: mtvsrd f0, r3
; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 2
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: extsh r4, r3
@ -879,7 +879,7 @@ define <4 x i16> @dont_fold_srem_power_of_two(<4 x i16> %x) {
; P9LE-NEXT: slwi r4, r4, 5
; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: xxswapd v3, vs0
; P9LE-NEXT: mtvsrd f0, r3
; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 6
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: extsh r4, r3
@ -896,7 +896,7 @@ define <4 x i16> @dont_fold_srem_power_of_two(<4 x i16> %x) {
; P9LE-NEXT: add r4, r4, r5
; P9LE-NEXT: mulli r4, r4, 95
; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: mtvsrd f0, r3
; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 4
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: extsh r4, r3
@ -905,7 +905,7 @@ define <4 x i16> @dont_fold_srem_power_of_two(<4 x i16> %x) {
; P9LE-NEXT: slwi r4, r4, 3
; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: xxswapd v4, vs0
; P9LE-NEXT: mtvsrd f0, r3
; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: xxswapd v2, vs0
; P9LE-NEXT: vmrglh v2, v4, v2
; P9LE-NEXT: vmrglw v2, v2, v3
@ -966,7 +966,7 @@ define <4 x i16> @dont_fold_srem_power_of_two(<4 x i16> %x) {
; P8LE-NEXT: xxswapd vs0, v2
; P8LE-NEXT: lis r3, -21386
; P8LE-NEXT: ori r3, r3, 37253
; P8LE-NEXT: mfvsrd r4, f0
; P8LE-NEXT: mffprd r4, f0
; P8LE-NEXT: rldicl r5, r4, 16, 48
; P8LE-NEXT: clrldi r7, r4, 48
; P8LE-NEXT: extsh r6, r5
@ -982,7 +982,7 @@ define <4 x i16> @dont_fold_srem_power_of_two(<4 x i16> %x) {
; P8LE-NEXT: slwi r8, r8, 6
; P8LE-NEXT: subf r7, r8, r7
; P8LE-NEXT: rldicl r3, r3, 32, 32
; P8LE-NEXT: mtvsrd f0, r7
; P8LE-NEXT: mtfprd f0, r7
; P8LE-NEXT: add r3, r3, r6
; P8LE-NEXT: addze r6, r10
; P8LE-NEXT: srwi r10, r3, 31
@ -994,14 +994,14 @@ define <4 x i16> @dont_fold_srem_power_of_two(<4 x i16> %x) {
; P8LE-NEXT: subf r6, r6, r9
; P8LE-NEXT: mulli r3, r3, 95
; P8LE-NEXT: srawi r8, r10, 3
; P8LE-NEXT: mtvsrd f1, r6
; P8LE-NEXT: mtfprd f1, r6
; P8LE-NEXT: addze r7, r8
; P8LE-NEXT: xxswapd v3, vs1
; P8LE-NEXT: subf r3, r3, r5
; P8LE-NEXT: slwi r5, r7, 3
; P8LE-NEXT: subf r4, r5, r4
; P8LE-NEXT: mtvsrd f2, r3
; P8LE-NEXT: mtvsrd f3, r4
; P8LE-NEXT: mtfprd f2, r3
; P8LE-NEXT: mtfprd f3, r4
; P8LE-NEXT: xxswapd v4, vs2
; P8LE-NEXT: vmrglh v2, v3, v2
; P8LE-NEXT: xxswapd v5, vs3
@ -1079,7 +1079,7 @@ define <4 x i16> @dont_fold_srem_one(<4 x i16> %x) {
; P9LE-NEXT: lis r5, -19946
; P9LE-NEXT: mulli r4, r4, 654
; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: mtvsrd f0, r3
; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 4
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: extsh r4, r3
@ -1095,7 +1095,7 @@ define <4 x i16> @dont_fold_srem_one(<4 x i16> %x) {
; P9LE-NEXT: mulli r4, r4, 23
; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: xxswapd v3, vs0
; P9LE-NEXT: mtvsrd f0, r3
; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 6
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: extsh r4, r3
@ -1110,7 +1110,7 @@ define <4 x i16> @dont_fold_srem_one(<4 x i16> %x) {
; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: vmrglh v3, v3, v4
; P9LE-NEXT: xxswapd v4, vs0
; P9LE-NEXT: mtvsrd f0, r3
; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: xxswapd v2, vs0
; P9LE-NEXT: vmrglh v2, v2, v4
; P9LE-NEXT: vmrglw v2, v2, v3
@ -1182,7 +1182,7 @@ define <4 x i16> @dont_fold_srem_one(<4 x i16> %x) {
; P8LE-NEXT: xxlxor v5, v5, v5
; P8LE-NEXT: ori r3, r3, 47143
; P8LE-NEXT: ori r8, r8, 17097
; P8LE-NEXT: mfvsrd r4, f0
; P8LE-NEXT: mffprd r4, f0
; P8LE-NEXT: rldicl r5, r4, 16, 48
; P8LE-NEXT: rldicl r6, r4, 32, 48
; P8LE-NEXT: rldicl r4, r4, 48, 48
@ -1214,11 +1214,11 @@ define <4 x i16> @dont_fold_srem_one(<4 x i16> %x) {
; P8LE-NEXT: mulli r8, r8, 23
; P8LE-NEXT: mulli r7, r7, 654
; P8LE-NEXT: subf r3, r3, r5
; P8LE-NEXT: mtvsrd f0, r3
; P8LE-NEXT: mtfprd f0, r3
; P8LE-NEXT: subf r3, r8, r6
; P8LE-NEXT: subf r4, r7, r4
; P8LE-NEXT: mtvsrd f1, r3
; P8LE-NEXT: mtvsrd f2, r4
; P8LE-NEXT: mtfprd f1, r3
; P8LE-NEXT: mtfprd f2, r4
; P8LE-NEXT: xxswapd v2, vs0
; P8LE-NEXT: xxswapd v3, vs1
; P8LE-NEXT: xxswapd v4, vs2
@ -1304,7 +1304,7 @@ define <4 x i16> @dont_fold_urem_i16_smax(<4 x i16> %x) {
; P9LE-NEXT: lis r5, 24749
; P9LE-NEXT: mulli r4, r4, 23
; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: mtvsrd f0, r3
; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 6
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: extsh r4, r3
@ -1318,7 +1318,7 @@ define <4 x i16> @dont_fold_urem_i16_smax(<4 x i16> %x) {
; P9LE-NEXT: mulli r4, r4, 5423
; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: xxswapd v3, vs0
; P9LE-NEXT: mtvsrd f0, r3
; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 2
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: extsh r4, r3
@ -1327,7 +1327,7 @@ define <4 x i16> @dont_fold_urem_i16_smax(<4 x i16> %x) {
; P9LE-NEXT: slwi r4, r4, 15
; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: xxswapd v4, vs0
; P9LE-NEXT: mtvsrd f0, r3
; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: xxswapd v2, vs0
; P9LE-NEXT: vmrglh v3, v4, v3
; P9LE-NEXT: xxlxor v4, v4, v4
@ -1393,7 +1393,7 @@ define <4 x i16> @dont_fold_urem_i16_smax(<4 x i16> %x) {
; P8LE-NEXT: xxlxor v5, v5, v5
; P8LE-NEXT: ori r6, r6, 47143
; P8LE-NEXT: ori r7, r7, 17097
; P8LE-NEXT: mfvsrd r3, f0
; P8LE-NEXT: mffprd r3, f0
; P8LE-NEXT: rldicl r4, r3, 16, 48
; P8LE-NEXT: rldicl r5, r3, 32, 48
; P8LE-NEXT: extsh r8, r4
@ -1418,13 +1418,13 @@ define <4 x i16> @dont_fold_urem_i16_smax(<4 x i16> %x) {
; P8LE-NEXT: srawi r8, r8, 15
; P8LE-NEXT: subf r4, r6, r4
; P8LE-NEXT: addze r6, r8
; P8LE-NEXT: mtvsrd f0, r4
; P8LE-NEXT: mtfprd f0, r4
; P8LE-NEXT: slwi r4, r6, 15
; P8LE-NEXT: subf r5, r7, r5
; P8LE-NEXT: subf r3, r4, r3
; P8LE-NEXT: mtvsrd f1, r5
; P8LE-NEXT: mtfprd f1, r5
; P8LE-NEXT: xxswapd v2, vs0
; P8LE-NEXT: mtvsrd f2, r3
; P8LE-NEXT: mtfprd f2, r3
; P8LE-NEXT: xxswapd v3, vs1
; P8LE-NEXT: xxswapd v4, vs2
; P8LE-NEXT: vmrglh v2, v2, v3
@ -1588,7 +1588,7 @@ define <4 x i64> @dont_fold_srem_i64(<4 x i64> %x) {
; P8LE-NEXT: sldi r5, r5, 32
; P8LE-NEXT: oris r3, r3, 58853
; P8LE-NEXT: oris r4, r4, 22795
; P8LE-NEXT: mfvsrd r8, f0
; P8LE-NEXT: mffprd r8, f0
; P8LE-NEXT: oris r5, r5, 1603
; P8LE-NEXT: ori r3, r3, 6055
; P8LE-NEXT: ori r4, r4, 8549
@ -1610,13 +1610,13 @@ define <4 x i64> @dont_fold_srem_i64(<4 x i64> %x) {
; P8LE-NEXT: add r4, r4, r9
; P8LE-NEXT: mulli r4, r4, 23
; P8LE-NEXT: sub r3, r6, r3
; P8LE-NEXT: mtvsrd f0, r3
; P8LE-NEXT: mtfprd f0, r3
; P8LE-NEXT: sub r5, r7, r5
; P8LE-NEXT: mtvsrd f1, r5
; P8LE-NEXT: mtfprd f1, r5
; P8LE-NEXT: sub r3, r8, r4
; P8LE-NEXT: li r4, 0
; P8LE-NEXT: mtvsrd f2, r3
; P8LE-NEXT: mtvsrd f3, r4
; P8LE-NEXT: mtfprd f2, r3
; P8LE-NEXT: mtfprd f3, r4
; P8LE-NEXT: xxmrghd v3, vs0, vs2
; P8LE-NEXT: xxmrghd v2, vs1, vs3
; P8LE-NEXT: blr
@ -1637,11 +1637,11 @@ define <4 x i64> @dont_fold_srem_i64(<4 x i64> %x) {
; P8BE-NEXT: oris r4, r4, 22795
; P8BE-NEXT: sldi r5, r5, 32
; P8BE-NEXT: oris r3, r3, 58853
; P8BE-NEXT: mfvsrd r7, f0
; P8BE-NEXT: mffprd r7, f0
; P8BE-NEXT: ori r4, r4, 8549
; P8BE-NEXT: ori r3, r3, 6055
; P8BE-NEXT: oris r5, r5, 1603
; P8BE-NEXT: mfvsrd r8, f1
; P8BE-NEXT: mffprd r8, f1
; P8BE-NEXT: mulhd r4, r6, r4
; P8BE-NEXT: mulhd r3, r7, r3
; P8BE-NEXT: ori r5, r5, 21445
@ -1661,12 +1661,12 @@ define <4 x i64> @dont_fold_srem_i64(<4 x i64> %x) {
; P8BE-NEXT: mulli r5, r5, 654
; P8BE-NEXT: sub r3, r7, r3
; P8BE-NEXT: sub r4, r6, r4
; P8BE-NEXT: mtvsrd f0, r3
; P8BE-NEXT: mtfprd f0, r3
; P8BE-NEXT: sub r3, r8, r5
; P8BE-NEXT: mtvsrd f1, r4
; P8BE-NEXT: mtfprd f1, r4
; P8BE-NEXT: li r4, 0
; P8BE-NEXT: mtvsrd f2, r3
; P8BE-NEXT: mtvsrd f3, r4
; P8BE-NEXT: mtfprd f2, r3
; P8BE-NEXT: mtfprd f3, r4
; P8BE-NEXT: xxmrghd v3, vs1, vs0
; P8BE-NEXT: xxmrghd v2, vs3, vs2
; P8BE-NEXT: blr

2
test/CodeGen/PowerPC/stack-realign.ll
View File

@ -129,7 +129,7 @@ entry:
; CHECK-DAG: std 30, -16(1)
; CHECK-DAG: mr 30, 1
; CHECK-DAG: std 0, 16(1)
; CHECK-DAG: subfc 0, [[REG3]], [[REG2]]
; CHECK-DAG: subc 0, [[REG2]], [[REG3]]
; CHECK: stdux 1, 1, 0
; CHECK: .cfi_def_cfa_register r30

4
test/CodeGen/PowerPC/testBitReverse.ll
View File

@ -91,8 +91,8 @@ define i64 @testBitReverseIntrinsicI64(i64 %arg) {
; CHECK-NEXT: and 3, 3, 4
; CHECK-NEXT: or 3, 3, 5
; CHECK-NEXT: rldicl 4, 3, 32, 32
; CHECK-NEXT: rlwinm 5, 3, 24, 0, 31
; CHECK-NEXT: rlwinm 6, 4, 24, 0, 31
; CHECK-NEXT: rotlwi 5, 3, 24
; CHECK-NEXT: rotlwi 6, 4, 24
; CHECK-NEXT: rlwimi 5, 3, 8, 8, 15
; CHECK-NEXT: rlwimi 5, 3, 8, 24, 31
; CHECK-NEXT: rlwimi 6, 4, 8, 8, 15

4
test/CodeGen/PowerPC/testComparesi32gtu.ll
View File

@ -72,8 +72,8 @@ entry:
define signext i32 @testCompare2(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: testCompare2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: rlwinm r3, r3, 0, 31, 31
; CHECK-NEXT: rlwinm r4, r4, 0, 31, 31
; CHECK-NEXT: clrlwi r3, r3, 31
; CHECK-NEXT: clrlwi r4, r4, 31
; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: clrldi r4, r4, 32
; CHECK-NEXT: sub r3, r4, r3

4
test/CodeGen/PowerPC/testComparesi32leu.ll
View File

@ -9,8 +9,8 @@
define signext i32 @test(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: rlwinm r3, r3, 0, 31, 31
; CHECK-NEXT: rlwinm r4, r4, 0, 31, 31
; CHECK-NEXT: clrlwi r3, r3, 31
; CHECK-NEXT: clrlwi r4, r4, 31
; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: clrldi r4, r4, 32
; CHECK-NEXT: sub r3, r4, r3

4
test/CodeGen/PowerPC/testComparesi32ltu.ll
View File

@ -72,8 +72,8 @@ entry:
define signext i32 @testCompare2(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: testCompare2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: rlwinm r3, r3, 0, 31, 31
; CHECK-NEXT: rlwinm r4, r4, 0, 31, 31
; CHECK-NEXT: clrlwi r3, r3, 31
; CHECK-NEXT: clrlwi r4, r4, 31
; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: clrldi r4, r4, 32
; CHECK-NEXT: sub r3, r3, r4

16
test/CodeGen/PowerPC/testComparesigesll.ll
View File

@ -19,7 +19,7 @@ define signext i32 @test_igesll(i64 %a, i64 %b) {
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sradi r5, r3, 63
; CHECK-BE-NEXT: rldicl r6, r4, 1, 63
; CHECK-BE-NEXT: subfc r3, r4, r3
; CHECK-BE-NEXT: subc r3, r3, r4
; CHECK-BE-NEXT: adde r3, r5, r6
; CHECK-BE-NEXT: blr
;
@ -27,7 +27,7 @@ define signext i32 @test_igesll(i64 %a, i64 %b) {
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r5, r3, 63
; CHECK-LE-NEXT: rldicl r6, r4, 1, 63
; CHECK-LE-NEXT: subfc r3, r4, r3
; CHECK-LE-NEXT: subc r3, r3, r4
; CHECK-LE-NEXT: adde r3, r5, r6
; CHECK-LE-NEXT: blr
entry:
@ -49,7 +49,7 @@ define signext i32 @test_igesll_sext(i64 %a, i64 %b) {
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sradi r5, r3, 63
; CHECK-BE-NEXT: rldicl r6, r4, 1, 63
; CHECK-BE-NEXT: subfc r3, r4, r3
; CHECK-BE-NEXT: subc r3, r3, r4
; CHECK-BE-NEXT: adde r3, r5, r6
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: blr
@ -58,7 +58,7 @@ define signext i32 @test_igesll_sext(i64 %a, i64 %b) {
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r5, r3, 63
; CHECK-LE-NEXT: rldicl r6, r4, 1, 63
; CHECK-LE-NEXT: subfc r3, r4, r3
; CHECK-LE-NEXT: subc r3, r3, r4
; CHECK-LE-NEXT: adde r3, r5, r6
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: blr
@ -129,7 +129,7 @@ define void @test_igesll_store(i64 %a, i64 %b) {
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sradi r6, r3, 63
; CHECK-BE-NEXT: ld r5, .LC0@toc@l(r5)
; CHECK-BE-NEXT: subfc r3, r4, r3
; CHECK-BE-NEXT: subc r3, r3, r4
; CHECK-BE-NEXT: rldicl r3, r4, 1, 63
; CHECK-BE-NEXT: adde r3, r6, r3
; CHECK-BE-NEXT: std r3, 0(r5)
@ -139,7 +139,7 @@ define void @test_igesll_store(i64 %a, i64 %b) {
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r6, r3, 63
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: subfc r3, r4, r3
; CHECK-LE-NEXT: subc r3, r3, r4
; CHECK-LE-NEXT: rldicl r3, r4, 1, 63
; CHECK-LE-NEXT: adde r3, r6, r3
; CHECK-LE-NEXT: std r3, glob@toc@l(r5)
@ -166,7 +166,7 @@ define void @test_igesll_sext_store(i64 %a, i64 %b) {
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sradi r6, r3, 63
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: subfc r3, r4, r3
; CHECK-BE-NEXT: subc r3, r3, r4
; CHECK-BE-NEXT: rldicl r3, r4, 1, 63
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: adde r3, r6, r3
@ -178,7 +178,7 @@ define void @test_igesll_sext_store(i64 %a, i64 %b) {
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r6, r3, 63
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: subfc r3, r4, r3
; CHECK-LE-NEXT: subc r3, r3, r4
; CHECK-LE-NEXT: rldicl r3, r4, 1, 63
; CHECK-LE-NEXT: adde r3, r6, r3
; CHECK-LE-NEXT: neg r3, r3

12
test/CodeGen/PowerPC/testComparesigeull.ll
View File

@ -14,7 +14,7 @@
define signext i32 @test_igeull(i64 %a, i64 %b) {
; CHECK-LABEL: test_igeull:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subfc r3, r4, r3
; CHECK-NEXT: subc r3, r3, r4
; CHECK-NEXT: subfe r3, r4, r4
; CHECK-NEXT: addi r3, r3, 1
; CHECK-NEXT: blr
@ -28,7 +28,7 @@ entry:
define signext i32 @test_igeull_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_igeull_sext:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subfc r3, r4, r3
; CHECK-NEXT: subc r3, r3, r4
; CHECK-NEXT: subfe r3, r4, r4
; CHECK-NEXT: not r3, r3
; CHECK-NEXT: blr
@ -67,7 +67,7 @@ define void @test_igeull_store(i64 %a, i64 %b) {
; BE-LABEL: test_igeull_store:
; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: subfc r3, r4, r3
; BE-NEXT: subc r3, r3, r4
; BE-NEXT: ld r3, .LC0@toc@l(r5)
; BE-NEXT: subfe r4, r4, r4
; BE-NEXT: addi r4, r4, 1
@ -76,7 +76,7 @@ define void @test_igeull_store(i64 %a, i64 %b) {
;
; LE-LABEL: test_igeull_store:
; LE: # %bb.0: # %entry
; LE-NEXT: subfc r3, r4, r3
; LE-NEXT: subc r3, r3, r4
; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: subfe r3, r4, r4
; LE-NEXT: addi r3, r3, 1
@ -94,7 +94,7 @@ define void @test_igeull_sext_store(i64 %a, i64 %b) {
; BE-LABEL: test_igeull_sext_store:
; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: subfc r3, r4, r3
; BE-NEXT: subc r3, r3, r4
; BE-NEXT: ld r3, .LC0@toc@l(r5)
; BE-NEXT: subfe r4, r4, r4
; BE-NEXT: not r4, r4
@ -103,7 +103,7 @@ define void @test_igeull_sext_store(i64 %a, i64 %b) {
;
; LE-LABEL: test_igeull_sext_store:
; LE: # %bb.0: # %entry
; LE-NEXT: subfc r3, r4, r3
; LE-NEXT: subc r3, r3, r4
; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: subfe r3, r4, r4
; LE-NEXT: not r3, r3

8
test/CodeGen/PowerPC/testComparesigtsll.ll
View File

@ -14,7 +14,7 @@ define signext i32 @test_igtsll(i64 %a, i64 %b) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r5, r4, 63
; CHECK-NEXT: rldicl r6, r3, 1, 63
; CHECK-NEXT: subfc r3, r3, r4
; CHECK-NEXT: subc r3, r4, r3
; CHECK-NEXT: adde r3, r6, r5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
@ -30,7 +30,7 @@ define signext i32 @test_igtsll_sext(i64 %a, i64 %b) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r5, r4, 63
; CHECK-NEXT: rldicl r6, r3, 1, 63
; CHECK-NEXT: subfc r3, r3, r4
; CHECK-NEXT: subc r3, r4, r3
; CHECK-NEXT: adde r3, r6, r5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
@ -76,7 +76,7 @@ define void @test_igtsll_store(i64 %a, i64 %b) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r6, r4, 63
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subfc r4, r3, r4
; CHECK-NEXT: subc r4, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: adde r3, r3, r6
@ -97,7 +97,7 @@ define void @test_igtsll_sext_store(i64 %a, i64 %b) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r6, r4, 63
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subfc r4, r3, r4
; CHECK-NEXT: subc r4, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: adde r3, r3, r6
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)

16
test/CodeGen/PowerPC/testComparesilesll.ll
View File

@ -19,7 +19,7 @@ define signext i32 @test_ilesll(i64 %a, i64 %b) {
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sradi r5, r4, 63
; CHECK-BE-NEXT: rldicl r6, r3, 1, 63
; CHECK-BE-NEXT: subfc r3, r3, r4
; CHECK-BE-NEXT: subc r3, r4, r3
; CHECK-BE-NEXT: adde r3, r5, r6
; CHECK-BE-NEXT: blr
;
@ -27,7 +27,7 @@ define signext i32 @test_ilesll(i64 %a, i64 %b) {
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r5, r4, 63
; CHECK-LE-NEXT: rldicl r6, r3, 1, 63
; CHECK-LE-NEXT: subfc r3, r3, r4
; CHECK-LE-NEXT: subc r3, r4, r3
; CHECK-LE-NEXT: adde r3, r5, r6
; CHECK-LE-NEXT: blr
entry:
@ -49,7 +49,7 @@ define signext i32 @test_ilesll_sext(i64 %a, i64 %b) {
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sradi r5, r4, 63
; CHECK-BE-NEXT: rldicl r6, r3, 1, 63
; CHECK-BE-NEXT: subfc r3, r3, r4
; CHECK-BE-NEXT: subc r3, r4, r3
; CHECK-BE-NEXT: adde r3, r5, r6
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: blr
@ -58,7 +58,7 @@ define signext i32 @test_ilesll_sext(i64 %a, i64 %b) {
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r5, r4, 63
; CHECK-LE-NEXT: rldicl r6, r3, 1, 63
; CHECK-LE-NEXT: subfc r3, r3, r4
; CHECK-LE-NEXT: subc r3, r4, r3
; CHECK-LE-NEXT: adde r3, r5, r6
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: blr
@ -135,7 +135,7 @@ define void @test_ilesll_store(i64 %a, i64 %b) {
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sradi r6, r4, 63
; CHECK-BE-NEXT: ld r5, .LC0@toc@l(r5)
; CHECK-BE-NEXT: subfc r4, r3, r4
; CHECK-BE-NEXT: subc r4, r4, r3
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: adde r3, r6, r3
; CHECK-BE-NEXT: std r3, 0(r5)
@ -145,7 +145,7 @@ define void @test_ilesll_store(i64 %a, i64 %b) {
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r6, r4, 63
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: subfc r4, r3, r4
; CHECK-LE-NEXT: subc r4, r4, r3
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: adde r3, r6, r3
; CHECK-LE-NEXT: std r3, glob@toc@l(r5)
@ -172,7 +172,7 @@ define void @test_ilesll_sext_store(i64 %a, i64 %b) {
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sradi r6, r4, 63
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: subfc r4, r3, r4
; CHECK-BE-NEXT: subc r4, r4, r3
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: adde r3, r6, r3
@ -184,7 +184,7 @@ define void @test_ilesll_sext_store(i64 %a, i64 %b) {
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r6, r4, 63
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: subfc r4, r3, r4
; CHECK-LE-NEXT: subc r4, r4, r3
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: adde r3, r6, r3
; CHECK-LE-NEXT: neg r3, r3

12
test/CodeGen/PowerPC/testComparesileull.ll
View File

@ -14,7 +14,7 @@
define signext i32 @test_ileull(i64 %a, i64 %b) {
; CHECK-LABEL: test_ileull:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subfc r4, r3, r4
; CHECK-NEXT: subc r4, r4, r3
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: addi r3, r3, 1
; CHECK-NEXT: blr
@ -28,7 +28,7 @@ entry:
define signext i32 @test_ileull_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_ileull_sext:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subfc r4, r3, r4
; CHECK-NEXT: subc r4, r4, r3
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: not r3, r3
; CHECK-NEXT: blr
@ -69,7 +69,7 @@ define void @test_ileull_store(i64 %a, i64 %b) {
; BE-LABEL: test_ileull_store:
; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: subfc r4, r3, r4
; BE-NEXT: subc r4, r4, r3
; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: subfe r3, r3, r3
; BE-NEXT: addi r3, r3, 1
@ -78,7 +78,7 @@ define void @test_ileull_store(i64 %a, i64 %b) {
;
; LE-LABEL: test_ileull_store:
; LE: # %bb.0: # %entry
; LE-NEXT: subfc r4, r3, r4
; LE-NEXT: subc r4, r4, r3
; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: subfe r3, r3, r3
; LE-NEXT: addi r3, r3, 1
@ -96,7 +96,7 @@ define void @test_ileull_sext_store(i64 %a, i64 %b) {
; BE-LABEL: test_ileull_sext_store:
; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: subfc r4, r3, r4
; BE-NEXT: subc r4, r4, r3
; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: subfe r3, r3, r3
; BE-NEXT: not r3, r3
@ -105,7 +105,7 @@ define void @test_ileull_sext_store(i64 %a, i64 %b) {
;
; LE-LABEL: test_ileull_sext_store:
; LE: # %bb.0: # %entry
; LE-NEXT: subfc r4, r3, r4
; LE-NEXT: subc r4, r4, r3
; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: subfe r3, r3, r3
; LE-NEXT: not r3, r3

12
test/CodeGen/PowerPC/testComparesiltsll.ll
View File

@ -16,7 +16,7 @@ define signext i32 @test_iltsll(i64 %a, i64 %b) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r5, r3, 63
; CHECK-NEXT: rldicl r6, r4, 1, 63
; CHECK-NEXT: subfc r3, r4, r3
; CHECK-NEXT: subc r3, r3, r4
; CHECK-NEXT: adde r3, r6, r5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
@ -32,7 +32,7 @@ define signext i32 @test_iltsll_sext(i64 %a, i64 %b) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r5, r3, 63
; CHECK-NEXT: rldicl r6, r4, 1, 63
; CHECK-NEXT: subfc r3, r4, r3
; CHECK-NEXT: subc r3, r3, r4
; CHECK-NEXT: adde r3, r6, r5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
@ -61,7 +61,7 @@ define void @test_iltsll_store(i64 %a, i64 %b) {
; BE: # %bb.0: # %entry
; BE-NEXT: sradi r6, r3, 63
; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: subfc r3, r4, r3
; BE-NEXT: subc r3, r3, r4
; BE-NEXT: rldicl r3, r4, 1, 63
; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: adde r3, r3, r6
@ -73,7 +73,7 @@ define void @test_iltsll_store(i64 %a, i64 %b) {
; LE: # %bb.0: # %entry
; LE-NEXT: sradi r6, r3, 63
; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: subfc r3, r4, r3
; LE-NEXT: subc r3, r3, r4
; LE-NEXT: rldicl r3, r4, 1, 63
; LE-NEXT: adde r3, r3, r6
; LE-NEXT: xori r3, r3, 1
@ -93,7 +93,7 @@ define void @test_iltsll_sext_store(i64 %a, i64 %b) {
; BE: # %bb.0: # %entry
; BE-NEXT: sradi r6, r3, 63
; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: subfc r3, r4, r3
; BE-NEXT: subc r3, r3, r4
; BE-NEXT: rldicl r3, r4, 1, 63
; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: adde r3, r3, r6
@ -106,7 +106,7 @@ define void @test_iltsll_sext_store(i64 %a, i64 %b) {
; LE: # %bb.0: # %entry
; LE-NEXT: sradi r6, r3, 63
; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: subfc r3, r4, r3
; LE-NEXT: subc r3, r3, r4
; LE-NEXT: rldicl r3, r4, 1, 63
; LE-NEXT: adde r3, r3, r6
; LE-NEXT: xori r3, r3, 1

16
test/CodeGen/PowerPC/testComparesllgesll.ll
View File

@ -19,7 +19,7 @@ define i64 @test_llgesll(i64 %a, i64 %b) {
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sradi r5, r3, 63
; CHECK-BE-NEXT: rldicl r6, r4, 1, 63
; CHECK-BE-NEXT: subfc r3, r4, r3
; CHECK-BE-NEXT: subc r3, r3, r4
; CHECK-BE-NEXT: adde r3, r5, r6
; CHECK-BE-NEXT: blr
;
@ -27,7 +27,7 @@ define i64 @test_llgesll(i64 %a, i64 %b) {
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r5, r3, 63
; CHECK-LE-NEXT: rldicl r6, r4, 1, 63
; CHECK-LE-NEXT: subfc r3, r4, r3
; CHECK-LE-NEXT: subc r3, r3, r4
; CHECK-LE-NEXT: adde r3, r5, r6
; CHECK-LE-NEXT: blr
entry:
@ -49,7 +49,7 @@ define i64 @test_llgesll_sext(i64 %a, i64 %b) {
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sradi r5, r3, 63
; CHECK-BE-NEXT: rldicl r6, r4, 1, 63
; CHECK-BE-NEXT: subfc r3, r4, r3
; CHECK-BE-NEXT: subc r3, r3, r4
; CHECK-BE-NEXT: adde r3, r5, r6
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: blr
@ -58,7 +58,7 @@ define i64 @test_llgesll_sext(i64 %a, i64 %b) {
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r5, r3, 63
; CHECK-LE-NEXT: rldicl r6, r4, 1, 63
; CHECK-LE-NEXT: subfc r3, r4, r3
; CHECK-LE-NEXT: subc r3, r3, r4
; CHECK-LE-NEXT: adde r3, r5, r6
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: blr
@ -129,7 +129,7 @@ define void @test_llgesll_store(i64 %a, i64 %b) {
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sradi r6, r3, 63
; CHECK-BE-NEXT: ld r5, .LC0@toc@l(r5)
; CHECK-BE-NEXT: subfc r3, r4, r3
; CHECK-BE-NEXT: subc r3, r3, r4
; CHECK-BE-NEXT: rldicl r3, r4, 1, 63
; CHECK-BE-NEXT: adde r3, r6, r3
; CHECK-BE-NEXT: std r3, 0(r5)
@ -139,7 +139,7 @@ define void @test_llgesll_store(i64 %a, i64 %b) {
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r6, r3, 63
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: subfc r3, r4, r3
; CHECK-LE-NEXT: subc r3, r3, r4
; CHECK-LE-NEXT: rldicl r3, r4, 1, 63
; CHECK-LE-NEXT: adde r3, r6, r3
; CHECK-LE-NEXT: std r3, glob@toc@l(r5)
@ -166,7 +166,7 @@ define void @test_llgesll_sext_store(i64 %a, i64 %b) {
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sradi r6, r3, 63
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: subfc r3, r4, r3
; CHECK-BE-NEXT: subc r3, r3, r4
; CHECK-BE-NEXT: rldicl r3, r4, 1, 63
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: adde r3, r6, r3
@ -178,7 +178,7 @@ define void @test_llgesll_sext_store(i64 %a, i64 %b) {
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r6, r3, 63
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: subfc r3, r4, r3
; CHECK-LE-NEXT: subc r3, r3, r4
; CHECK-LE-NEXT: rldicl r3, r4, 1, 63
; CHECK-LE-NEXT: adde r3, r6, r3
; CHECK-LE-NEXT: neg r3, r3

12
test/CodeGen/PowerPC/testComparesllgeull.ll
View File

@ -14,7 +14,7 @@
define i64 @test_llgeull(i64 %a, i64 %b) {
; CHECK-LABEL: test_llgeull:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subfc r3, r4, r3
; CHECK-NEXT: subc r3, r3, r4
; CHECK-NEXT: subfe r3, r4, r4
; CHECK-NEXT: addi r3, r3, 1
; CHECK-NEXT: blr
@ -28,7 +28,7 @@ entry:
define i64 @test_llgeull_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_llgeull_sext:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subfc r3, r4, r3
; CHECK-NEXT: subc r3, r3, r4
; CHECK-NEXT: subfe r3, r4, r4
; CHECK-NEXT: not r3, r3
; CHECK-NEXT: blr
@ -67,7 +67,7 @@ define void @test_llgeull_store(i64 %a, i64 %b) {
; BE-LABEL: test_llgeull_store:
; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: subfc r3, r4, r3
; BE-NEXT: subc r3, r3, r4
; BE-NEXT: ld r3, .LC0@toc@l(r5)
; BE-NEXT: subfe r4, r4, r4
; BE-NEXT: addi r4, r4, 1
@ -76,7 +76,7 @@ define void @test_llgeull_store(i64 %a, i64 %b) {
;
; LE-LABEL: test_llgeull_store:
; LE: # %bb.0: # %entry
; LE-NEXT: subfc r3, r4, r3
; LE-NEXT: subc r3, r3, r4
; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: subfe r3, r4, r4
; LE-NEXT: addi r3, r3, 1
@ -94,7 +94,7 @@ define void @test_llgeull_sext_store(i64 %a, i64 %b) {
; BE-LABEL: test_llgeull_sext_store:
; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: subfc r3, r4, r3
; BE-NEXT: subc r3, r3, r4
; BE-NEXT: ld r3, .LC0@toc@l(r5)
; BE-NEXT: subfe r4, r4, r4
; BE-NEXT: not r4, r4
@ -103,7 +103,7 @@ define void @test_llgeull_sext_store(i64 %a, i64 %b) {
;
; LE-LABEL: test_llgeull_sext_store:
; LE: # %bb.0: # %entry
; LE-NEXT: subfc r3, r4, r3
; LE-NEXT: subc r3, r3, r4
; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: subfe r3, r4, r4
; LE-NEXT: not r3, r3

8
test/CodeGen/PowerPC/testComparesllgtsll.ll
View File

@ -14,7 +14,7 @@ define i64 @test_llgtsll(i64 %a, i64 %b) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r5, r4, 63
; CHECK-NEXT: rldicl r6, r3, 1, 63
; CHECK-NEXT: subfc r3, r3, r4
; CHECK-NEXT: subc r3, r4, r3
; CHECK-NEXT: adde r3, r6, r5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
@ -30,7 +30,7 @@ define i64 @test_llgtsll_sext(i64 %a, i64 %b) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r5, r4, 63
; CHECK-NEXT: rldicl r6, r3, 1, 63
; CHECK-NEXT: subfc r3, r3, r4
; CHECK-NEXT: subc r3, r4, r3
; CHECK-NEXT: adde r3, r6, r5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
@ -76,7 +76,7 @@ define void @test_llgtsll_store(i64 %a, i64 %b) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r6, r4, 63
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subfc r4, r3, r4
; CHECK-NEXT: subc r4, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: adde r3, r3, r6
@ -97,7 +97,7 @@ define void @test_llgtsll_sext_store(i64 %a, i64 %b) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r6, r4, 63
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subfc r4, r3, r4
; CHECK-NEXT: subc r4, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: adde r3, r3, r6
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)

16
test/CodeGen/PowerPC/testCompareslllesll.ll
View File

@ -20,7 +20,7 @@ define i64 @test_lllesll(i64 %a, i64 %b) {
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sradi r5, r4, 63
; CHECK-BE-NEXT: rldicl r6, r3, 1, 63
; CHECK-BE-NEXT: subfc r3, r3, r4
; CHECK-BE-NEXT: subc r3, r4, r3
; CHECK-BE-NEXT: adde r3, r5, r6
; CHECK-BE-NEXT: blr
;
@ -28,7 +28,7 @@ define i64 @test_lllesll(i64 %a, i64 %b) {
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r5, r4, 63
; CHECK-LE-NEXT: rldicl r6, r3, 1, 63
; CHECK-LE-NEXT: subfc r3, r3, r4
; CHECK-LE-NEXT: subc r3, r4, r3
; CHECK-LE-NEXT: adde r3, r5, r6
; CHECK-LE-NEXT: blr
entry:
@ -51,7 +51,7 @@ define i64 @test_lllesll_sext(i64 %a, i64 %b) {
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sradi r5, r4, 63
; CHECK-BE-NEXT: rldicl r6, r3, 1, 63
; CHECK-BE-NEXT: subfc r3, r3, r4
; CHECK-BE-NEXT: subc r3, r4, r3
; CHECK-BE-NEXT: adde r3, r5, r6
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: blr
@ -60,7 +60,7 @@ define i64 @test_lllesll_sext(i64 %a, i64 %b) {
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r5, r4, 63
; CHECK-LE-NEXT: rldicl r6, r3, 1, 63
; CHECK-LE-NEXT: subfc r3, r3, r4
; CHECK-LE-NEXT: subc r3, r4, r3
; CHECK-LE-NEXT: adde r3, r5, r6
; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: blr
@ -140,7 +140,7 @@ define void @test_lllesll_store(i64 %a, i64 %b) {
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sradi r6, r4, 63
; CHECK-BE-NEXT: ld r5, .LC0@toc@l(r5)
; CHECK-BE-NEXT: subfc r4, r3, r4
; CHECK-BE-NEXT: subc r4, r4, r3
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: adde r3, r6, r3
; CHECK-BE-NEXT: std r3, 0(r5)
@ -150,7 +150,7 @@ define void @test_lllesll_store(i64 %a, i64 %b) {
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r6, r4, 63
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: subfc r4, r3, r4
; CHECK-LE-NEXT: subc r4, r4, r3
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: adde r3, r6, r3
; CHECK-LE-NEXT: std r3, glob@toc@l(r5)
@ -178,7 +178,7 @@ define void @test_lllesll_sext_store(i64 %a, i64 %b) {
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sradi r6, r4, 63
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: subfc r4, r3, r4
; CHECK-BE-NEXT: subc r4, r4, r3
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: adde r3, r6, r3
@ -190,7 +190,7 @@ define void @test_lllesll_sext_store(i64 %a, i64 %b) {
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r6, r4, 63
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: subfc r4, r3, r4
; CHECK-LE-NEXT: subc r4, r4, r3
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: adde r3, r6, r3
; CHECK-LE-NEXT: neg r3, r3

12
test/CodeGen/PowerPC/testComparesllleull.ll
View File

@ -14,7 +14,7 @@
define i64 @test_llleull(i64 %a, i64 %b) {
; CHECK-LABEL: test_llleull:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subfc r4, r3, r4
; CHECK-NEXT: subc r4, r4, r3
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: addi r3, r3, 1
; CHECK-NEXT: blr
@ -28,7 +28,7 @@ entry:
define i64 @test_llleull_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_llleull_sext:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subfc r4, r3, r4
; CHECK-NEXT: subc r4, r4, r3
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: not r3, r3
; CHECK-NEXT: blr
@ -69,7 +69,7 @@ define void @test_llleull_store(i64 %a, i64 %b) {
; BE-LABEL: test_llleull_store:
; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: subfc r4, r3, r4
; BE-NEXT: subc r4, r4, r3
; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: subfe r3, r3, r3
; BE-NEXT: addi r3, r3, 1
@ -78,7 +78,7 @@ define void @test_llleull_store(i64 %a, i64 %b) {
;
; LE-LABEL: test_llleull_store:
; LE: # %bb.0: # %entry
; LE-NEXT: subfc r4, r3, r4
; LE-NEXT: subc r4, r4, r3
; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: subfe r3, r3, r3
; LE-NEXT: addi r3, r3, 1
@ -96,7 +96,7 @@ define void @test_llleull_sext_store(i64 %a, i64 %b) {
; BE-LABEL: test_llleull_sext_store:
; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: subfc r4, r3, r4
; BE-NEXT: subc r4, r4, r3
; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: subfe r3, r3, r3
; BE-NEXT: not r3, r3
@ -105,7 +105,7 @@ define void @test_llleull_sext_store(i64 %a, i64 %b) {
;
; LE-LABEL: test_llleull_sext_store:
; LE: # %bb.0: # %entry
; LE-NEXT: subfc r4, r3, r4
; LE-NEXT: subc r4, r4, r3
; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: subfe r3, r3, r3
; LE-NEXT: not r3, r3

12
test/CodeGen/PowerPC/testComparesllltsll.ll
View File

@ -16,7 +16,7 @@ define i64 @test_llltsll(i64 %a, i64 %b) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r5, r3, 63
; CHECK-NEXT: rldicl r6, r4, 1, 63
; CHECK-NEXT: subfc r3, r4, r3
; CHECK-NEXT: subc r3, r3, r4
; CHECK-NEXT: adde r3, r6, r5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
@ -32,7 +32,7 @@ define i64 @test_llltsll_sext(i64 %a, i64 %b) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r5, r3, 63
; CHECK-NEXT: rldicl r6, r4, 1, 63
; CHECK-NEXT: subfc r3, r4, r3
; CHECK-NEXT: subc r3, r3, r4
; CHECK-NEXT: adde r3, r6, r5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
@ -61,7 +61,7 @@ define void @test_llltsll_store(i64 %a, i64 %b) {
; BE: # %bb.0: # %entry
; BE-NEXT: sradi r6, r3, 63
; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: subfc r3, r4, r3
; BE-NEXT: subc r3, r3, r4
; BE-NEXT: rldicl r3, r4, 1, 63
; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: adde r3, r3, r6
@ -73,7 +73,7 @@ define void @test_llltsll_store(i64 %a, i64 %b) {
; LE: # %bb.0: # %entry
; LE-NEXT: sradi r6, r3, 63
; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: subfc r3, r4, r3
; LE-NEXT: subc r3, r3, r4
; LE-NEXT: rldicl r3, r4, 1, 63
; LE-NEXT: adde r3, r3, r6
; LE-NEXT: xori r3, r3, 1
@ -93,7 +93,7 @@ define void @test_llltsll_sext_store(i64 %a, i64 %b) {
; BE: # %bb.0: # %entry
; BE-NEXT: sradi r6, r3, 63
; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: subfc r3, r4, r3
; BE-NEXT: subc r3, r3, r4
; BE-NEXT: rldicl r3, r4, 1, 63
; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: adde r3, r3, r6
@ -106,7 +106,7 @@ define void @test_llltsll_sext_store(i64 %a, i64 %b) {
; LE: # %bb.0: # %entry
; LE-NEXT: sradi r6, r3, 63
; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: subfc r3, r4, r3
; LE-NEXT: subc r3, r3, r4
; LE-NEXT: rldicl r3, r4, 1, 63
; LE-NEXT: adde r3, r3, r6
; LE-NEXT: xori r3, r3, 1

2
test/CodeGen/PowerPC/tocSaveInPrologue.ll
View File

@ -22,7 +22,7 @@ define dso_local void @test(void (i32)* nocapture %fp, i32 signext %Arg, i32 sig
; CHECK-NEXT: cmpwi r29, 1
; CHECK-NEXT: bc 12, lt, .LBB0_3
; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: cmpwi cr0, r4, 11
; CHECK-NEXT: cmpwi r4, 11
; CHECK-NEXT: bc 12, lt, .LBB0_3
; CHECK-NEXT: .p2align 5
; CHECK-NEXT: .LBB0_2: # %for.body.us

2
test/CodeGen/PowerPC/trunc-srl-load.ll
View File

@ -5,7 +5,7 @@ define dso_local fastcc void @trunc_srl_load(i32 zeroext %AttrArgNo) {
; CHECK-LABEL: trunc_srl_load:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lhz 4, 2(0)
; CHECK-NEXT: cmplw 0, 4, 3
; CHECK-NEXT: cmplw 4, 3
; CHECK-NEXT: ble 0, .LBB0_2
; CHECK-NEXT: # %bb.1: # %exit
; CHECK-NEXT: .LBB0_2: # %cond.false

24
test/CodeGen/PowerPC/uint-to-fp-v4i32.ll
View File

@ -16,11 +16,11 @@ define dso_local <2 x double> @test1(<8 x i16> %a) {
; P9BE: # %bb.0: # %entry
; P9BE-NEXT: li r3, 0
; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: rlwinm r3, r3, 0, 16, 31
; P9BE-NEXT: clrlwi r3, r3, 16
; P9BE-NEXT: mtfprwz f0, r3
; P9BE-NEXT: li r3, 2
; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: rlwinm r3, r3, 0, 16, 31
; P9BE-NEXT: clrlwi r3, r3, 16
; P9BE-NEXT: mtfprwz f1, r3
; P9BE-NEXT: xscvuxddp f0, f0
; P9BE-NEXT: xscvuxddp f1, f1
@ -31,11 +31,11 @@ define dso_local <2 x double> @test1(<8 x i16> %a) {
; P9LE: # %bb.0: # %entry
; P9LE-NEXT: li r3, 0
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: rlwinm r3, r3, 0, 16, 31
; P9LE-NEXT: clrlwi r3, r3, 16
; P9LE-NEXT: mtfprwz f0, r3
; P9LE-NEXT: li r3, 2
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: rlwinm r3, r3, 0, 16, 31
; P9LE-NEXT: clrlwi r3, r3, 16
; P9LE-NEXT: mtfprwz f1, r3
; P9LE-NEXT: xscvuxddp f0, f0
; P9LE-NEXT: xscvuxddp f1, f1
@ -47,8 +47,8 @@ define dso_local <2 x double> @test1(<8 x i16> %a) {
; P8BE-NEXT: mfvsrd r3, v2
; P8BE-NEXT: rldicl r4, r3, 16, 48
; P8BE-NEXT: rldicl r3, r3, 32, 48
; P8BE-NEXT: rlwinm r4, r4, 0, 16, 31
; P8BE-NEXT: rlwinm r3, r3, 0, 16, 31
; P8BE-NEXT: clrlwi r4, r4, 16
; P8BE-NEXT: clrlwi r3, r3, 16
; P8BE-NEXT: mtfprwz f0, r4
; P8BE-NEXT: mtfprwz f1, r3
; P8BE-NEXT: xscvuxddp f0, f0
@ -59,11 +59,11 @@ define dso_local <2 x double> @test1(<8 x i16> %a) {
; P8LE-LABEL: test1:
; P8LE: # %bb.0: # %entry
; P8LE-NEXT: xxswapd vs0, v2
; P8LE-NEXT: mfvsrd r3, f0
; P8LE-NEXT: mffprd r3, f0
; P8LE-NEXT: clrldi r4, r3, 48
; P8LE-NEXT: rldicl r3, r3, 48, 48
; P8LE-NEXT: rlwinm r4, r4, 0, 16, 31
; P8LE-NEXT: rlwinm r3, r3, 0, 16, 31
; P8LE-NEXT: clrlwi r4, r4, 16
; P8LE-NEXT: clrlwi r3, r3, 16
; P8LE-NEXT: mtfprwz f0, r4
; P8LE-NEXT: mtfprwz f1, r3
; P8LE-NEXT: xscvuxddp f0, f0
@ -104,7 +104,7 @@ define dso_local <2 x double> @test2(<4 x i32> %a, <4 x i32> %b) {
; P8BE-NEXT: xxsldwi vs0, v2, v2, 3
; P8BE-NEXT: mfvsrwz r4, v3
; P8BE-NEXT: mtfprwz f1, r4
; P8BE-NEXT: mfvsrwz r3, f0
; P8BE-NEXT: mffprwz r3, f0
; P8BE-NEXT: xscvuxddp f1, f1
; P8BE-NEXT: mtfprwz f0, r3
; P8BE-NEXT: xscvuxddp f0, f0
@ -115,8 +115,8 @@ define dso_local <2 x double> @test2(<4 x i32> %a, <4 x i32> %b) {
; P8LE: # %bb.0: # %entry
; P8LE-NEXT: xxswapd vs0, v2
; P8LE-NEXT: xxsldwi vs1, v3, v3, 1
; P8LE-NEXT: mfvsrwz r3, f0
; P8LE-NEXT: mfvsrwz r4, f1
; P8LE-NEXT: mffprwz r3, f0
; P8LE-NEXT: mffprwz r4, f1
; P8LE-NEXT: mtfprwz f0, r3
; P8LE-NEXT: mtfprwz f1, r4
; P8LE-NEXT: xscvuxddp f0, f0

248
test/CodeGen/PowerPC/urem-vector-lkk.ll
View File

@ -22,7 +22,7 @@ define <4 x i16> @fold_urem_vec_1(<4 x i16> %x) {
; P9LE-NEXT: rldicl r4, r4, 27, 37
; P9LE-NEXT: mulli r4, r4, 98
; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: mtvsrd f0, r3
; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 6
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: rlwinm r4, r3, 0, 16, 31
@ -33,7 +33,7 @@ define <4 x i16> @fold_urem_vec_1(<4 x i16> %x) {
; P9LE-NEXT: mulli r4, r4, 1003
; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: xxswapd v3, vs0
; P9LE-NEXT: mtvsrd f0, r3
; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 2
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: rlwinm r4, r3, 30, 18, 31
@ -42,10 +42,10 @@ define <4 x i16> @fold_urem_vec_1(<4 x i16> %x) {
; P9LE-NEXT: mulli r4, r4, 124
; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: xxswapd v4, vs0
; P9LE-NEXT: mtvsrd f0, r3
; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 0
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: rlwinm r4, r3, 0, 16, 31
; P9LE-NEXT: clrlwi r4, r3, 16
; P9LE-NEXT: lis r6, 22765
; P9LE-NEXT: ori r6, r6, 8969
; P9LE-NEXT: vmrglh v3, v4, v3
@ -59,7 +59,7 @@ define <4 x i16> @fold_urem_vec_1(<4 x i16> %x) {
; P9LE-NEXT: srwi r4, r4, 6
; P9LE-NEXT: mulli r4, r4, 95
; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: mtvsrd f0, r3
; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: xxswapd v2, vs0
; P9LE-NEXT: vmrglh v2, v4, v2
; P9LE-NEXT: vmrglw v2, v3, v2
@ -69,7 +69,7 @@ define <4 x i16> @fold_urem_vec_1(<4 x i16> %x) {
; P9BE: # %bb.0:
; P9BE-NEXT: li r3, 6
; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: rlwinm r3, r3, 0, 16, 31
; P9BE-NEXT: clrlwi r3, r3, 16
; P9BE-NEXT: lis r5, 16727
; P9BE-NEXT: ori r5, r5, 2287
; P9BE-NEXT: clrldi r4, r3, 32
@ -83,7 +83,7 @@ define <4 x i16> @fold_urem_vec_1(<4 x i16> %x) {
; P9BE-NEXT: mtvsrd v3, r3
; P9BE-NEXT: li r3, 4
; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: rlwinm r3, r3, 0, 16, 31
; P9BE-NEXT: clrlwi r3, r3, 16
; P9BE-NEXT: clrldi r4, r3, 32
; P9BE-NEXT: mulld r4, r4, r5
; P9BE-NEXT: lis r5, 8456
@ -108,7 +108,7 @@ define <4 x i16> @fold_urem_vec_1(<4 x i16> %x) {
; P9BE-NEXT: mtvsrd v4, r3
; P9BE-NEXT: li r3, 0
; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: rlwinm r3, r3, 0, 16, 31
; P9BE-NEXT: clrlwi r3, r3, 16
; P9BE-NEXT: clrldi r4, r3, 32
; P9BE-NEXT: mulld r4, r4, r5
; P9BE-NEXT: rldicl r4, r4, 32, 32
@ -131,10 +131,10 @@ define <4 x i16> @fold_urem_vec_1(<4 x i16> %x) {
; P8LE-NEXT: lis r8, 21399
; P8LE-NEXT: ori r3, r3, 8969
; P8LE-NEXT: ori r8, r8, 33437
; P8LE-NEXT: mfvsrd r4, f0
; P8LE-NEXT: mffprd r4, f0
; P8LE-NEXT: clrldi r5, r4, 48
; P8LE-NEXT: rldicl r9, r4, 32, 48
; P8LE-NEXT: rlwinm r6, r5, 0, 16, 31
; P8LE-NEXT: clrlwi r6, r5, 16
; P8LE-NEXT: rldicl r10, r4, 16, 48
; P8LE-NEXT: rlwinm r11, r9, 0, 16, 31
; P8LE-NEXT: clrldi r7, r6, 32
@ -163,13 +163,13 @@ define <4 x i16> @fold_urem_vec_1(<4 x i16> %x) {
; P8LE-NEXT: mulli r8, r8, 124
; P8LE-NEXT: subf r7, r7, r9
; P8LE-NEXT: subf r6, r6, r10
; P8LE-NEXT: mtvsrd f0, r7
; P8LE-NEXT: mtfprd f0, r7
; P8LE-NEXT: subf r3, r3, r5
; P8LE-NEXT: subf r4, r8, r4
; P8LE-NEXT: mtvsrd f1, r6
; P8LE-NEXT: mtvsrd f2, r3
; P8LE-NEXT: mtfprd f1, r6
; P8LE-NEXT: mtfprd f2, r3
; P8LE-NEXT: xxswapd v2, vs0
; P8LE-NEXT: mtvsrd f3, r4
; P8LE-NEXT: mtfprd f3, r4
; P8LE-NEXT: xxswapd v3, vs1
; P8LE-NEXT: xxswapd v4, vs2
; P8LE-NEXT: xxswapd v5, vs3
@ -187,11 +187,11 @@ define <4 x i16> @fold_urem_vec_1(<4 x i16> %x) {
; P8BE-NEXT: ori r9, r9, 2287
; P8BE-NEXT: rldicl r5, r4, 16, 48
; P8BE-NEXT: clrldi r6, r4, 48
; P8BE-NEXT: rlwinm r5, r5, 0, 16, 31
; P8BE-NEXT: clrlwi r5, r5, 16
; P8BE-NEXT: rldicl r7, r4, 48, 48
; P8BE-NEXT: rlwinm r6, r6, 0, 16, 31
; P8BE-NEXT: clrlwi r6, r6, 16
; P8BE-NEXT: clrldi r8, r5, 32
; P8BE-NEXT: rlwinm r7, r7, 0, 16, 31
; P8BE-NEXT: clrlwi r7, r7, 16
; P8BE-NEXT: mulld r3, r8, r3
; P8BE-NEXT: lis r8, 21399
; P8BE-NEXT: clrldi r10, r6, 32
@ -204,7 +204,7 @@ define <4 x i16> @fold_urem_vec_1(<4 x i16> %x) {
; P8BE-NEXT: ori r10, r10, 16913
; P8BE-NEXT: rlwinm r11, r4, 30, 18, 31
; P8BE-NEXT: rldicl r3, r3, 32, 32
; P8BE-NEXT: rlwinm r4, r4, 0, 16, 31
; P8BE-NEXT: clrlwi r4, r4, 16
; P8BE-NEXT: mulld r10, r11, r10
; P8BE-NEXT: subf r11, r3, r5
; P8BE-NEXT: srwi r11, r11, 1
@ -242,7 +242,7 @@ define <4 x i16> @fold_urem_vec_2(<4 x i16> %x) {
; P9LE: # %bb.0:
; P9LE-NEXT: li r3, 0
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: rlwinm r4, r3, 0, 16, 31
; P9LE-NEXT: clrlwi r4, r3, 16
; P9LE-NEXT: lis r6, 22765
; P9LE-NEXT: ori r6, r6, 8969
; P9LE-NEXT: clrldi r5, r4, 32
@ -254,10 +254,10 @@ define <4 x i16> @fold_urem_vec_2(<4 x i16> %x) {
; P9LE-NEXT: srwi r4, r4, 6
; P9LE-NEXT: mulli r4, r4, 95
; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: mtvsrd f0, r3
; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 2
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: rlwinm r4, r3, 0, 16, 31
; P9LE-NEXT: clrlwi r4, r3, 16
; P9LE-NEXT: clrldi r5, r4, 32
; P9LE-NEXT: mulld r5, r5, r6
; P9LE-NEXT: rldicl r5, r5, 32, 32
@ -268,10 +268,10 @@ define <4 x i16> @fold_urem_vec_2(<4 x i16> %x) {
; P9LE-NEXT: mulli r4, r4, 95
; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: xxswapd v3, vs0
; P9LE-NEXT: mtvsrd f0, r3
; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 4
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: rlwinm r4, r3, 0, 16, 31
; P9LE-NEXT: clrlwi r4, r3, 16
; P9LE-NEXT: clrldi r5, r4, 32
; P9LE-NEXT: mulld r5, r5, r6
; P9LE-NEXT: rldicl r5, r5, 32, 32
@ -282,10 +282,10 @@ define <4 x i16> @fold_urem_vec_2(<4 x i16> %x) {
; P9LE-NEXT: mulli r4, r4, 95
; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: xxswapd v4, vs0
; P9LE-NEXT: mtvsrd f0, r3
; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 6
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: rlwinm r4, r3, 0, 16, 31
; P9LE-NEXT: clrlwi r4, r3, 16
; P9LE-NEXT: clrldi r5, r4, 32
; P9LE-NEXT: mulld r5, r5, r6
; P9LE-NEXT: rldicl r5, r5, 32, 32
@ -297,7 +297,7 @@ define <4 x i16> @fold_urem_vec_2(<4 x i16> %x) {
; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: vmrglh v3, v4, v3
; P9LE-NEXT: xxswapd v4, vs0
; P9LE-NEXT: mtvsrd f0, r3
; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: xxswapd v2, vs0
; P9LE-NEXT: vmrglh v2, v2, v4
; P9LE-NEXT: vmrglw v2, v2, v3
@ -307,7 +307,7 @@ define <4 x i16> @fold_urem_vec_2(<4 x i16> %x) {
; P9BE: # %bb.0:
; P9BE-NEXT: li r3, 6
; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: rlwinm r3, r3, 0, 16, 31
; P9BE-NEXT: clrlwi r3, r3, 16
; P9BE-NEXT: lis r5, 22765
; P9BE-NEXT: ori r5, r5, 8969
; P9BE-NEXT: clrldi r4, r3, 32
@ -323,7 +323,7 @@ define <4 x i16> @fold_urem_vec_2(<4 x i16> %x) {
; P9BE-NEXT: mtvsrd v3, r3
; P9BE-NEXT: li r3, 4
; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: rlwinm r3, r3, 0, 16, 31
; P9BE-NEXT: clrlwi r3, r3, 16
; P9BE-NEXT: clrldi r4, r3, 32
; P9BE-NEXT: mulld r4, r4, r5
; P9BE-NEXT: rldicl r4, r4, 32, 32
@ -337,7 +337,7 @@ define <4 x i16> @fold_urem_vec_2(<4 x i16> %x) {
; P9BE-NEXT: mtvsrd v4, r3
; P9BE-NEXT: li r3, 2
; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: rlwinm r3, r3, 0, 16, 31
; P9BE-NEXT: clrlwi r3, r3, 16
; P9BE-NEXT: clrldi r4, r3, 32
; P9BE-NEXT: mulld r4, r4, r5
; P9BE-NEXT: rldicl r4, r4, 32, 32
@ -352,7 +352,7 @@ define <4 x i16> @fold_urem_vec_2(<4 x i16> %x) {
; P9BE-NEXT: mtvsrd v4, r3
; P9BE-NEXT: li r3, 0
; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: rlwinm r3, r3, 0, 16, 31
; P9BE-NEXT: clrlwi r3, r3, 16
; P9BE-NEXT: clrldi r4, r3, 32
; P9BE-NEXT: mulld r4, r4, r5
; P9BE-NEXT: rldicl r4, r4, 32, 32
@ -375,16 +375,16 @@ define <4 x i16> @fold_urem_vec_2(<4 x i16> %x) {
; P8LE-NEXT: std r29, -24(r1) # 8-byte Folded Spill
; P8LE-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; P8LE-NEXT: ori r4, r4, 8969
; P8LE-NEXT: mfvsrd r5, f0
; P8LE-NEXT: mffprd r5, f0
; P8LE-NEXT: clrldi r3, r5, 48
; P8LE-NEXT: rldicl r6, r5, 48, 48
; P8LE-NEXT: rlwinm r8, r3, 0, 16, 31
; P8LE-NEXT: clrlwi r8, r3, 16
; P8LE-NEXT: rldicl r7, r5, 32, 48
; P8LE-NEXT: rlwinm r9, r6, 0, 16, 31
; P8LE-NEXT: clrlwi r9, r6, 16
; P8LE-NEXT: rldicl r5, r5, 16, 48
; P8LE-NEXT: clrldi r11, r8, 32
; P8LE-NEXT: rlwinm r10, r7, 0, 16, 31
; P8LE-NEXT: rlwinm r12, r5, 0, 16, 31
; P8LE-NEXT: clrlwi r10, r7, 16
; P8LE-NEXT: clrlwi r12, r5, 16
; P8LE-NEXT: mulld r11, r11, r4
; P8LE-NEXT: clrldi r0, r9, 32
; P8LE-NEXT: clrldi r30, r10, 32
@ -420,13 +420,13 @@ define <4 x i16> @fold_urem_vec_2(<4 x i16> %x) {
; P8LE-NEXT: mulli r4, r4, 95
; P8LE-NEXT: subf r3, r8, r3
; P8LE-NEXT: subf r6, r9, r6
; P8LE-NEXT: mtvsrd f0, r3
; P8LE-NEXT: mtfprd f0, r3
; P8LE-NEXT: subf r3, r10, r7
; P8LE-NEXT: subf r4, r4, r5
; P8LE-NEXT: mtvsrd f1, r6
; P8LE-NEXT: mtvsrd f2, r3
; P8LE-NEXT: mtfprd f1, r6
; P8LE-NEXT: mtfprd f2, r3
; P8LE-NEXT: xxswapd v2, vs0
; P8LE-NEXT: mtvsrd f3, r4
; P8LE-NEXT: mtfprd f3, r4
; P8LE-NEXT: xxswapd v3, vs1
; P8LE-NEXT: xxswapd v4, vs2
; P8LE-NEXT: xxswapd v5, vs3
@ -442,15 +442,15 @@ define <4 x i16> @fold_urem_vec_2(<4 x i16> %x) {
; P8BE-NEXT: ori r3, r3, 8969
; P8BE-NEXT: clrldi r5, r4, 48
; P8BE-NEXT: rldicl r6, r4, 48, 48
; P8BE-NEXT: rlwinm r5, r5, 0, 16, 31
; P8BE-NEXT: clrlwi r5, r5, 16
; P8BE-NEXT: rldicl r7, r4, 32, 48
; P8BE-NEXT: rlwinm r6, r6, 0, 16, 31
; P8BE-NEXT: clrlwi r6, r6, 16
; P8BE-NEXT: clrldi r8, r5, 32
; P8BE-NEXT: rldicl r4, r4, 16, 48
; P8BE-NEXT: rlwinm r7, r7, 0, 16, 31
; P8BE-NEXT: clrlwi r7, r7, 16
; P8BE-NEXT: clrldi r9, r6, 32
; P8BE-NEXT: mulld r8, r8, r3
; P8BE-NEXT: rlwinm r4, r4, 0, 16, 31
; P8BE-NEXT: clrlwi r4, r4, 16
; P8BE-NEXT: clrldi r10, r7, 32
; P8BE-NEXT: mulld r9, r9, r3
; P8BE-NEXT: clrldi r11, r4, 32
@ -507,7 +507,7 @@ define <4 x i16> @combine_urem_udiv(<4 x i16> %x) {
; P9LE: # %bb.0:
; P9LE-NEXT: li r3, 0
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: rlwinm r4, r3, 0, 16, 31
; P9LE-NEXT: clrlwi r4, r3, 16
; P9LE-NEXT: lis r6, 22765
; P9LE-NEXT: ori r6, r6, 8969
; P9LE-NEXT: clrldi r5, r4, 32
@ -519,10 +519,10 @@ define <4 x i16> @combine_urem_udiv(<4 x i16> %x) {
; P9LE-NEXT: srwi r4, r4, 6
; P9LE-NEXT: mulli r5, r4, 95
; P9LE-NEXT: subf r3, r5, r3
; P9LE-NEXT: mtvsrd f0, r3
; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 2
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: rlwinm r5, r3, 0, 16, 31
; P9LE-NEXT: clrlwi r5, r3, 16
; P9LE-NEXT: clrldi r7, r5, 32
; P9LE-NEXT: mulld r7, r7, r6
; P9LE-NEXT: rldicl r7, r7, 32, 32
@ -533,10 +533,10 @@ define <4 x i16> @combine_urem_udiv(<4 x i16> %x) {
; P9LE-NEXT: mulli r7, r5, 95
; P9LE-NEXT: subf r3, r7, r3
; P9LE-NEXT: xxswapd v3, vs0
; P9LE-NEXT: mtvsrd f0, r3
; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 4
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: rlwinm r7, r3, 0, 16, 31
; P9LE-NEXT: clrlwi r7, r3, 16
; P9LE-NEXT: clrldi r8, r7, 32
; P9LE-NEXT: mulld r8, r8, r6
; P9LE-NEXT: rldicl r8, r8, 32, 32
@ -547,10 +547,10 @@ define <4 x i16> @combine_urem_udiv(<4 x i16> %x) {
; P9LE-NEXT: mulli r8, r7, 95
; P9LE-NEXT: subf r3, r8, r3
; P9LE-NEXT: xxswapd v4, vs0
; P9LE-NEXT: mtvsrd f0, r3
; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 6
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: rlwinm r8, r3, 0, 16, 31
; P9LE-NEXT: clrlwi r8, r3, 16
; P9LE-NEXT: clrldi r9, r8, 32
; P9LE-NEXT: mulld r6, r9, r6
; P9LE-NEXT: rldicl r6, r6, 32, 32
@ -562,18 +562,18 @@ define <4 x i16> @combine_urem_udiv(<4 x i16> %x) {
; P9LE-NEXT: subf r3, r8, r3
; P9LE-NEXT: vmrglh v3, v4, v3
; P9LE-NEXT: xxswapd v4, vs0
; P9LE-NEXT: mtvsrd f0, r3
; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: xxswapd v2, vs0
; P9LE-NEXT: mtvsrd f0, r4
; P9LE-NEXT: mtfprd f0, r4
; P9LE-NEXT: vmrglh v2, v2, v4
; P9LE-NEXT: vmrglw v2, v2, v3
; P9LE-NEXT: xxswapd v3, vs0
; P9LE-NEXT: mtvsrd f0, r5
; P9LE-NEXT: mtfprd f0, r5
; P9LE-NEXT: xxswapd v4, vs0
; P9LE-NEXT: mtvsrd f0, r7
; P9LE-NEXT: mtfprd f0, r7
; P9LE-NEXT: vmrglh v3, v4, v3
; P9LE-NEXT: xxswapd v4, vs0
; P9LE-NEXT: mtvsrd f0, r6
; P9LE-NEXT: mtfprd f0, r6
; P9LE-NEXT: xxswapd v5, vs0
; P9LE-NEXT: vmrglh v4, v5, v4
; P9LE-NEXT: vmrglw v3, v4, v3
@ -584,7 +584,7 @@ define <4 x i16> @combine_urem_udiv(<4 x i16> %x) {
; P9BE: # %bb.0:
; P9BE-NEXT: li r3, 6
; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: rlwinm r4, r3, 0, 16, 31
; P9BE-NEXT: clrlwi r4, r3, 16
; P9BE-NEXT: lis r6, 22765
; P9BE-NEXT: ori r6, r6, 8969
; P9BE-NEXT: clrldi r5, r4, 32
@ -600,7 +600,7 @@ define <4 x i16> @combine_urem_udiv(<4 x i16> %x) {
; P9BE-NEXT: mtvsrd v3, r3
; P9BE-NEXT: li r3, 4
; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: rlwinm r5, r3, 0, 16, 31
; P9BE-NEXT: clrlwi r5, r3, 16
; P9BE-NEXT: clrldi r7, r5, 32
; P9BE-NEXT: mulld r7, r7, r6
; P9BE-NEXT: rldicl r7, r7, 32, 32
@ -614,7 +614,7 @@ define <4 x i16> @combine_urem_udiv(<4 x i16> %x) {
; P9BE-NEXT: mtvsrd v4, r3
; P9BE-NEXT: li r3, 2
; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: rlwinm r7, r3, 0, 16, 31
; P9BE-NEXT: clrlwi r7, r3, 16
; P9BE-NEXT: clrldi r8, r7, 32
; P9BE-NEXT: mulld r8, r8, r6
; P9BE-NEXT: rldicl r8, r8, 32, 32
@ -629,7 +629,7 @@ define <4 x i16> @combine_urem_udiv(<4 x i16> %x) {
; P9BE-NEXT: mtvsrd v4, r3
; P9BE-NEXT: li r3, 0
; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: rlwinm r3, r3, 0, 16, 31
; P9BE-NEXT: clrlwi r3, r3, 16
; P9BE-NEXT: clrldi r8, r3, 32
; P9BE-NEXT: mulld r6, r8, r6
; P9BE-NEXT: rldicl r6, r6, 32, 32
@ -664,16 +664,16 @@ define <4 x i16> @combine_urem_udiv(<4 x i16> %x) {
; P8LE-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; P8LE-NEXT: std r29, -24(r1) # 8-byte Folded Spill
; P8LE-NEXT: ori r5, r5, 8969
; P8LE-NEXT: mfvsrd r6, f0
; P8LE-NEXT: mffprd r6, f0
; P8LE-NEXT: clrldi r3, r6, 48
; P8LE-NEXT: rldicl r4, r6, 48, 48
; P8LE-NEXT: rldicl r7, r6, 32, 48
; P8LE-NEXT: rlwinm r8, r3, 0, 16, 31
; P8LE-NEXT: rlwinm r9, r4, 0, 16, 31
; P8LE-NEXT: clrlwi r8, r3, 16
; P8LE-NEXT: clrlwi r9, r4, 16
; P8LE-NEXT: rldicl r6, r6, 16, 48
; P8LE-NEXT: rlwinm r10, r7, 0, 16, 31
; P8LE-NEXT: clrlwi r10, r7, 16
; P8LE-NEXT: clrldi r11, r8, 32
; P8LE-NEXT: rlwinm r12, r6, 0, 16, 31
; P8LE-NEXT: clrlwi r12, r6, 16
; P8LE-NEXT: clrldi r0, r9, 32
; P8LE-NEXT: clrldi r30, r10, 32
; P8LE-NEXT: mulld r11, r11, r5
@ -703,26 +703,26 @@ define <4 x i16> @combine_urem_udiv(<4 x i16> %x) {
; P8LE-NEXT: mulli r12, r8, 95
; P8LE-NEXT: srwi r10, r10, 6
; P8LE-NEXT: add r5, r11, r5
; P8LE-NEXT: mtvsrd f0, r8
; P8LE-NEXT: mtfprd f0, r8
; P8LE-NEXT: mulli r8, r9, 95
; P8LE-NEXT: mtvsrd f1, r9
; P8LE-NEXT: mtfprd f1, r9
; P8LE-NEXT: mulli r9, r10, 95
; P8LE-NEXT: srwi r5, r5, 6
; P8LE-NEXT: mtvsrd f3, r5
; P8LE-NEXT: mtfprd f3, r5
; P8LE-NEXT: mulli r5, r5, 95
; P8LE-NEXT: xxswapd v2, vs0
; P8LE-NEXT: xxswapd v3, vs1
; P8LE-NEXT: mtvsrd f2, r10
; P8LE-NEXT: mtfprd f2, r10
; P8LE-NEXT: subf r3, r12, r3
; P8LE-NEXT: xxswapd v6, vs3
; P8LE-NEXT: mtvsrd f0, r3
; P8LE-NEXT: mtfprd f0, r3
; P8LE-NEXT: subf r3, r9, r7
; P8LE-NEXT: subf r4, r8, r4
; P8LE-NEXT: xxswapd v1, vs2
; P8LE-NEXT: mtvsrd f4, r3
; P8LE-NEXT: mtfprd f4, r3
; P8LE-NEXT: subf r3, r5, r6
; P8LE-NEXT: mtvsrd f1, r4
; P8LE-NEXT: mtvsrd f5, r3
; P8LE-NEXT: mtfprd f1, r4
; P8LE-NEXT: mtfprd f5, r3
; P8LE-NEXT: xxswapd v5, vs4
; P8LE-NEXT: vmrglh v2, v3, v2
; P8LE-NEXT: xxswapd v3, vs0
@ -744,13 +744,13 @@ define <4 x i16> @combine_urem_udiv(<4 x i16> %x) {
; P8BE-NEXT: ori r5, r5, 8969
; P8BE-NEXT: clrldi r3, r6, 48
; P8BE-NEXT: rldicl r4, r6, 48, 48
; P8BE-NEXT: rlwinm r8, r3, 0, 16, 31
; P8BE-NEXT: clrlwi r8, r3, 16
; P8BE-NEXT: rldicl r7, r6, 32, 48
; P8BE-NEXT: rlwinm r9, r4, 0, 16, 31
; P8BE-NEXT: clrlwi r9, r4, 16
; P8BE-NEXT: rldicl r6, r6, 16, 48
; P8BE-NEXT: clrldi r11, r8, 32
; P8BE-NEXT: rlwinm r10, r7, 0, 16, 31
; P8BE-NEXT: rlwinm r6, r6, 0, 16, 31
; P8BE-NEXT: clrlwi r10, r7, 16
; P8BE-NEXT: clrlwi r6, r6, 16
; P8BE-NEXT: clrldi r12, r9, 32
; P8BE-NEXT: mulld r11, r11, r5
; P8BE-NEXT: clrldi r0, r10, 32
@ -823,16 +823,16 @@ define <4 x i16> @dont_fold_urem_power_of_two(<4 x i16> %x) {
; P9LE: # %bb.0:
; P9LE-NEXT: li r3, 0
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: rlwinm r3, r3, 0, 26, 31
; P9LE-NEXT: mtvsrd f0, r3
; P9LE-NEXT: clrlwi r3, r3, 26
; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 2
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: rlwinm r3, r3, 0, 27, 31
; P9LE-NEXT: clrlwi r3, r3, 27
; P9LE-NEXT: xxswapd v3, vs0
; P9LE-NEXT: mtvsrd f0, r3
; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 6
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: rlwinm r4, r3, 0, 16, 31
; P9LE-NEXT: clrlwi r4, r3, 16
; P9LE-NEXT: lis r6, 22765
; P9LE-NEXT: ori r6, r6, 8969
; P9LE-NEXT: xxswapd v4, vs0
@ -846,12 +846,12 @@ define <4 x i16> @dont_fold_urem_power_of_two(<4 x i16> %x) {
; P9LE-NEXT: srwi r4, r4, 6
; P9LE-NEXT: mulli r4, r4, 95
; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: mtvsrd f0, r3
; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 4
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: rlwinm r3, r3, 0, 29, 31
; P9LE-NEXT: clrlwi r3, r3, 29
; P9LE-NEXT: xxswapd v4, vs0
; P9LE-NEXT: mtvsrd f0, r3
; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: xxswapd v2, vs0
; P9LE-NEXT: vmrglh v2, v4, v2
; P9LE-NEXT: vmrglw v2, v2, v3
@ -861,17 +861,17 @@ define <4 x i16> @dont_fold_urem_power_of_two(<4 x i16> %x) {
; P9BE: # %bb.0:
; P9BE-NEXT: li r3, 2
; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: rlwinm r3, r3, 0, 27, 31
; P9BE-NEXT: clrlwi r3, r3, 27
; P9BE-NEXT: sldi r3, r3, 48
; P9BE-NEXT: mtvsrd v3, r3
; P9BE-NEXT: li r3, 0
; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: rlwinm r3, r3, 0, 26, 31
; P9BE-NEXT: clrlwi r3, r3, 26
; P9BE-NEXT: sldi r3, r3, 48
; P9BE-NEXT: mtvsrd v4, r3
; P9BE-NEXT: li r3, 6
; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: rlwinm r3, r3, 0, 16, 31
; P9BE-NEXT: clrlwi r3, r3, 16
; P9BE-NEXT: lis r5, 22765
; P9BE-NEXT: ori r5, r5, 8969
; P9BE-NEXT: vmrghh v3, v4, v3
@ -888,7 +888,7 @@ define <4 x i16> @dont_fold_urem_power_of_two(<4 x i16> %x) {
; P9BE-NEXT: mtvsrd v4, r3
; P9BE-NEXT: li r3, 4
; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: rlwinm r3, r3, 0, 29, 31
; P9BE-NEXT: clrlwi r3, r3, 29
; P9BE-NEXT: sldi r3, r3, 48
; P9BE-NEXT: mtvsrd v2, r3
; P9BE-NEXT: vmrghh v2, v2, v4
@ -900,14 +900,14 @@ define <4 x i16> @dont_fold_urem_power_of_two(<4 x i16> %x) {
; P8LE-NEXT: xxswapd vs0, v2
; P8LE-NEXT: lis r3, 22765
; P8LE-NEXT: ori r3, r3, 8969
; P8LE-NEXT: mfvsrd r4, f0
; P8LE-NEXT: mffprd r4, f0
; P8LE-NEXT: rldicl r5, r4, 16, 48
; P8LE-NEXT: rlwinm r6, r5, 0, 16, 31
; P8LE-NEXT: clrlwi r6, r5, 16
; P8LE-NEXT: clrldi r7, r6, 32
; P8LE-NEXT: mulld r3, r7, r3
; P8LE-NEXT: rldicl r7, r4, 48, 48
; P8LE-NEXT: rlwinm r7, r7, 0, 27, 31
; P8LE-NEXT: mtvsrd f1, r7
; P8LE-NEXT: clrlwi r7, r7, 27
; P8LE-NEXT: mtfprd f1, r7
; P8LE-NEXT: rldicl r3, r3, 32, 32
; P8LE-NEXT: xxswapd v3, vs1
; P8LE-NEXT: subf r6, r3, r6
@ -916,15 +916,15 @@ define <4 x i16> @dont_fold_urem_power_of_two(<4 x i16> %x) {
; P8LE-NEXT: clrldi r6, r4, 48
; P8LE-NEXT: srwi r3, r3, 6
; P8LE-NEXT: rldicl r4, r4, 32, 48
; P8LE-NEXT: rlwinm r6, r6, 0, 26, 31
; P8LE-NEXT: clrlwi r6, r6, 26
; P8LE-NEXT: mulli r3, r3, 95
; P8LE-NEXT: rlwinm r4, r4, 0, 29, 31
; P8LE-NEXT: mtvsrd f0, r6
; P8LE-NEXT: mtvsrd f3, r4
; P8LE-NEXT: clrlwi r4, r4, 29
; P8LE-NEXT: mtfprd f0, r6
; P8LE-NEXT: mtfprd f3, r4
; P8LE-NEXT: xxswapd v2, vs0
; P8LE-NEXT: xxswapd v5, vs3
; P8LE-NEXT: subf r3, r3, r5
; P8LE-NEXT: mtvsrd f2, r3
; P8LE-NEXT: mtfprd f2, r3
; P8LE-NEXT: vmrglh v2, v3, v2
; P8LE-NEXT: xxswapd v4, vs2
; P8LE-NEXT: vmrglh v3, v4, v5
@ -938,8 +938,8 @@ define <4 x i16> @dont_fold_urem_power_of_two(<4 x i16> %x) {
; P8BE-NEXT: ori r3, r3, 8969
; P8BE-NEXT: clrldi r5, r4, 48
; P8BE-NEXT: rldicl r7, r4, 16, 48
; P8BE-NEXT: rlwinm r5, r5, 0, 16, 31
; P8BE-NEXT: rlwinm r7, r7, 0, 26, 31
; P8BE-NEXT: clrlwi r5, r5, 16
; P8BE-NEXT: clrlwi r7, r7, 26
; P8BE-NEXT: clrldi r6, r5, 32
; P8BE-NEXT: mulld r3, r6, r3
; P8BE-NEXT: rldicl r3, r3, 32, 32
@ -949,10 +949,10 @@ define <4 x i16> @dont_fold_urem_power_of_two(<4 x i16> %x) {
; P8BE-NEXT: rldicl r6, r4, 32, 48
; P8BE-NEXT: srwi r3, r3, 6
; P8BE-NEXT: rldicl r4, r4, 48, 48
; P8BE-NEXT: rlwinm r6, r6, 0, 27, 31
; P8BE-NEXT: clrlwi r6, r6, 27
; P8BE-NEXT: mulli r3, r3, 95
; P8BE-NEXT: sldi r6, r6, 48
; P8BE-NEXT: rlwinm r4, r4, 0, 29, 31
; P8BE-NEXT: clrlwi r4, r4, 29
; P8BE-NEXT: mtvsrd v2, r6
; P8BE-NEXT: sldi r6, r7, 48
; P8BE-NEXT: sldi r4, r4, 48
@ -987,7 +987,7 @@ define <4 x i16> @dont_fold_urem_one(<4 x i16> %x) {
; P9LE-NEXT: rldicl r4, r4, 28, 36
; P9LE-NEXT: mulli r4, r4, 23
; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: mtvsrd f0, r3
; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 6
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: rlwinm r4, r3, 0, 16, 31
@ -996,7 +996,7 @@ define <4 x i16> @dont_fold_urem_one(<4 x i16> %x) {
; P9LE-NEXT: mulli r4, r4, 5423
; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: xxswapd v3, vs0
; P9LE-NEXT: mtvsrd f0, r3
; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 2
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: rlwinm r4, r3, 31, 17, 31
@ -1005,7 +1005,7 @@ define <4 x i16> @dont_fold_urem_one(<4 x i16> %x) {
; P9LE-NEXT: mulli r4, r4, 654
; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: xxswapd v4, vs0
; P9LE-NEXT: mtvsrd f0, r3
; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: xxswapd v2, vs0
; P9LE-NEXT: vmrglh v3, v4, v3
; P9LE-NEXT: xxlxor v4, v4, v4
@ -1017,7 +1017,7 @@ define <4 x i16> @dont_fold_urem_one(<4 x i16> %x) {
; P9BE: # %bb.0:
; P9BE-NEXT: li r3, 6
; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: rlwinm r3, r3, 0, 16, 31
; P9BE-NEXT: clrlwi r3, r3, 16
; P9BE-NEXT: lis r5, 24749
; P9BE-NEXT: ori r5, r5, 47143
; P9BE-NEXT: clrldi r4, r3, 32
@ -1034,7 +1034,7 @@ define <4 x i16> @dont_fold_urem_one(<4 x i16> %x) {
; P9BE-NEXT: mtvsrd v3, r3
; P9BE-NEXT: li r3, 4
; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: rlwinm r3, r3, 0, 16, 31
; P9BE-NEXT: clrlwi r3, r3, 16
; P9BE-NEXT: clrldi r4, r3, 32
; P9BE-NEXT: mulld r4, r4, r6
; P9BE-NEXT: rldicl r4, r4, 28, 36
@ -1071,7 +1071,7 @@ define <4 x i16> @dont_fold_urem_one(<4 x i16> %x) {
; P8LE-NEXT: oris r3, r3, 51306
; P8LE-NEXT: ori r5, r5, 17097
; P8LE-NEXT: ori r3, r3, 30865
; P8LE-NEXT: mfvsrd r4, f0
; P8LE-NEXT: mffprd r4, f0
; P8LE-NEXT: rldicl r6, r4, 32, 48
; P8LE-NEXT: rldicl r7, r4, 16, 48
; P8LE-NEXT: rlwinm r9, r6, 0, 16, 31
@ -1089,10 +1089,10 @@ define <4 x i16> @dont_fold_urem_one(<4 x i16> %x) {
; P8LE-NEXT: mulli r3, r3, 654
; P8LE-NEXT: subf r5, r5, r6
; P8LE-NEXT: subf r6, r8, r7
; P8LE-NEXT: mtvsrd f0, r5
; P8LE-NEXT: mtfprd f0, r5
; P8LE-NEXT: subf r3, r3, r4
; P8LE-NEXT: mtvsrd f1, r6
; P8LE-NEXT: mtvsrd f2, r3
; P8LE-NEXT: mtfprd f1, r6
; P8LE-NEXT: mtfprd f2, r3
; P8LE-NEXT: xxswapd v2, vs0
; P8LE-NEXT: xxswapd v3, vs1
; P8LE-NEXT: xxswapd v4, vs2
@ -1115,9 +1115,9 @@ define <4 x i16> @dont_fold_urem_one(<4 x i16> %x) {
; P8BE-NEXT: ori r3, r3, 17097
; P8BE-NEXT: rldicl r4, r4, 48, 48
; P8BE-NEXT: rlwinm r9, r5, 31, 17, 31
; P8BE-NEXT: rlwinm r7, r7, 0, 16, 31
; P8BE-NEXT: rlwinm r5, r5, 0, 16, 31
; P8BE-NEXT: rlwinm r4, r4, 0, 16, 31
; P8BE-NEXT: clrlwi r7, r7, 16
; P8BE-NEXT: clrlwi r5, r5, 16
; P8BE-NEXT: clrlwi r4, r4, 16
; P8BE-NEXT: mulld r6, r9, r6
; P8BE-NEXT: clrldi r9, r7, 32
; P8BE-NEXT: mulld r8, r9, r8
@ -1255,7 +1255,7 @@ define <4 x i64> @dont_fold_urem_i64(<4 x i64> %x) {
; P8LE-NEXT: sldi r3, r3, 32
; P8LE-NEXT: sldi r4, r4, 32
; P8LE-NEXT: oris r3, r3, 45590
; P8LE-NEXT: mfvsrd r7, f0
; P8LE-NEXT: mffprd r7, f0
; P8LE-NEXT: sldi r5, r5, 32
; P8LE-NEXT: oris r4, r4, 52170
; P8LE-NEXT: ori r3, r3, 17097
@ -1277,12 +1277,12 @@ define <4 x i64> @dont_fold_urem_i64(<4 x i64> %x) {
; P8LE-NEXT: mulli r3, r3, 23
; P8LE-NEXT: sub r4, r8, r4
; P8LE-NEXT: sub r5, r6, r5
; P8LE-NEXT: mtvsrd f0, r4
; P8LE-NEXT: mtfprd f0, r4
; P8LE-NEXT: sub r3, r7, r3
; P8LE-NEXT: li r4, 0
; P8LE-NEXT: mtvsrd f1, r5
; P8LE-NEXT: mtvsrd f2, r3
; P8LE-NEXT: mtvsrd f3, r4
; P8LE-NEXT: mtfprd f1, r5
; P8LE-NEXT: mtfprd f2, r3
; P8LE-NEXT: mtfprd f3, r4
; P8LE-NEXT: xxmrghd v3, vs0, vs2
; P8LE-NEXT: xxmrghd v2, vs1, vs3
; P8LE-NEXT: blr
@ -1302,10 +1302,10 @@ define <4 x i64> @dont_fold_urem_i64(<4 x i64> %x) {
; P8BE-NEXT: sldi r4, r4, 32
; P8BE-NEXT: oris r3, r3, 45590
; P8BE-NEXT: sldi r5, r5, 32
; P8BE-NEXT: mfvsrd r7, f0
; P8BE-NEXT: mffprd r7, f0
; P8BE-NEXT: oris r4, r4, 52170
; P8BE-NEXT: ori r3, r3, 17097
; P8BE-NEXT: mfvsrd r8, f1
; P8BE-NEXT: mffprd r8, f1
; P8BE-NEXT: oris r5, r5, 1603
; P8BE-NEXT: ori r4, r4, 12109
; P8BE-NEXT: mulhdu r3, r6, r3
@ -1323,13 +1323,13 @@ define <4 x i64> @dont_fold_urem_i64(<4 x i64> %x) {
; P8BE-NEXT: mulli r5, r5, 654
; P8BE-NEXT: mulli r3, r3, 23
; P8BE-NEXT: sub r4, r7, r4
; P8BE-NEXT: mtvsrd f0, r4
; P8BE-NEXT: mtfprd f0, r4
; P8BE-NEXT: sub r4, r8, r5
; P8BE-NEXT: sub r3, r6, r3
; P8BE-NEXT: mtvsrd f1, r4
; P8BE-NEXT: mtfprd f1, r4
; P8BE-NEXT: li r4, 0
; P8BE-NEXT: mtvsrd f2, r3
; P8BE-NEXT: mtvsrd f3, r4
; P8BE-NEXT: mtfprd f2, r3
; P8BE-NEXT: mtfprd f3, r4
; P8BE-NEXT: xxmrghd v3, vs2, vs0
; P8BE-NEXT: xxmrghd v2, vs3, vs1
; P8BE-NEXT: blr

6
test/CodeGen/PowerPC/vec-min-max.ll
View File

@ -246,9 +246,9 @@ define i128 @invalidv1i128(<2 x i128> %v1, <2 x i128> %v2) {
; CHECK-NEXT: xxswapd 1, 34
; CHECK-NEXT: cmpld 4, 3
; CHECK-NEXT: cmpd 1, 4, 3
; CHECK-NEXT: mfvsrd 3, 0
; CHECK-NEXT: mffprd 3, 0
; CHECK-NEXT: crandc 20, 4, 2
; CHECK-NEXT: mfvsrd 4, 1
; CHECK-NEXT: mffprd 4, 1
; CHECK-NEXT: cmpld 1, 4, 3
; CHECK-NEXT: bc 12, 20, .LBB12_3
; CHECK-NEXT: # %bb.1:
@ -259,7 +259,7 @@ define i128 @invalidv1i128(<2 x i128> %v1, <2 x i128> %v2) {
; CHECK-NEXT: .LBB12_3:
; CHECK-NEXT: xxswapd 0, 34
; CHECK-NEXT: mfvsrd 4, 34
; CHECK-NEXT: mfvsrd 3, 0
; CHECK-NEXT: mffprd 3, 0
; CHECK-NEXT: blr
;
; NOP8VEC-LABEL: invalidv1i128:

2
test/CodeGen/PowerPC/vec-trunc.ll
View File

@ -93,7 +93,7 @@ define void @test2i8(<2 x i8>* nocapture %Sink, <2 x i16>* nocapture readonly %S
; CHECK-NEXT: lvx v2, 0, r4
; CHECK-NEXT: vpkuhum v2, v2, v2
; CHECK-NEXT: xxswapd vs0, v2
; CHECK-NEXT: mfvsrd r4, f0
; CHECK-NEXT: mffprd r4, f0
; CHECK-NEXT: clrldi r4, r4, 48
; CHECK-NEXT: sth r4, 0(r3)
; CHECK-NEXT: blr

4
test/CodeGen/PowerPC/vec_add_sub_doubleword.ll
View File

@ -36,7 +36,7 @@ define <2 x i64> @increment_by_one(<2 x i64> %x) nounwind {
define <2 x i64> @increment_by_val(<2 x i64> %x, i64 %val) nounwind {
; VSX-LABEL: increment_by_val:
; VSX: # %bb.0:
; VSX-NEXT: mtvsrd 0, 5
; VSX-NEXT: mtfprd 0, 5
; VSX-NEXT: xxspltd 35, 0, 0
; VSX-NEXT: vaddudm 2, 2, 3
; VSX-NEXT: blr
@ -98,7 +98,7 @@ define <2 x i64> @decrement_by_one(<2 x i64> %x) nounwind {
define <2 x i64> @decrement_by_val(<2 x i64> %x, i64 %val) nounwind {
; VSX-LABEL: decrement_by_val:
; VSX: # %bb.0:
; VSX-NEXT: mtvsrd 0, 5
; VSX-NEXT: mtfprd 0, 5
; VSX-NEXT: xxspltd 35, 0, 0
; VSX-NEXT: vsubudm 2, 2, 3
; VSX-NEXT: blr

8
test/CodeGen/PowerPC/vec_add_sub_quadword.ll
View File

@ -45,8 +45,8 @@ define <1 x i128> @increment_by_one(<1 x i128> %x) nounwind {
define <1 x i128> @increment_by_val(<1 x i128> %x, i128 %val) nounwind {
; VSX-LABEL: increment_by_val:
; VSX: # %bb.0:
; VSX-NEXT: mtvsrd 0, 6
; VSX-NEXT: mtvsrd 1, 5
; VSX-NEXT: mtfprd 0, 6
; VSX-NEXT: mtfprd 1, 5
; VSX-NEXT: xxmrghd 35, 1, 0
; VSX-NEXT: vadduqm 2, 2, 3
; VSX-NEXT: blr
@ -96,8 +96,8 @@ define <1 x i128> @decrement_by_one(<1 x i128> %x) nounwind {
define <1 x i128> @decrement_by_val(<1 x i128> %x, i128 %val) nounwind {
; VSX-LABEL: decrement_by_val:
; VSX: # %bb.0:
; VSX-NEXT: mtvsrd 0, 6
; VSX-NEXT: mtvsrd 1, 5
; VSX-NEXT: mtfprd 0, 6
; VSX-NEXT: mtfprd 1, 5
; VSX-NEXT: xxmrghd 35, 1, 0
; VSX-NEXT: vsubuqm 2, 2, 3
; VSX-NEXT: blr

612
test/CodeGen/PowerPC/vec_conv_fp32_to_i16_elts.ll
View File

File diff suppressed because it is too large Load Diff

12
test/CodeGen/PowerPC/vec_conv_fp32_to_i64_elts.ll
View File

@ -12,7 +12,7 @@
define <2 x i64> @test2elt(i64 %a.coerce) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtvsrd f0, r3
; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxmrglw vs0, v2, v2
; CHECK-P8-NEXT: xvcvspdp vs0, vs0
@ -21,7 +21,7 @@ define <2 x i64> @test2elt(i64 %a.coerce) local_unnamed_addr #0 {
;
; CHECK-P9-LABEL: test2elt:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: xxmrglw vs0, v2, v2
; CHECK-P9-NEXT: xvcvspdp vs0, vs0
@ -30,7 +30,7 @@ define <2 x i64> @test2elt(i64 %a.coerce) local_unnamed_addr #0 {
;
; CHECK-BE-LABEL: test2elt:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrd f0, r3
; CHECK-BE-NEXT: mtfprd f0, r3
; CHECK-BE-NEXT: xxmrghw vs0, vs0, vs0
; CHECK-BE-NEXT: xvcvspdp vs0, vs0
; CHECK-BE-NEXT: xvcvdpuxds v2, vs0
@ -311,7 +311,7 @@ entry:
define <2 x i64> @test2elt_signed(i64 %a.coerce) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt_signed:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtvsrd f0, r3
; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxmrglw vs0, v2, v2
; CHECK-P8-NEXT: xvcvspdp vs0, vs0
@ -320,7 +320,7 @@ define <2 x i64> @test2elt_signed(i64 %a.coerce) local_unnamed_addr #0 {
;
; CHECK-P9-LABEL: test2elt_signed:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: xxmrglw vs0, v2, v2
; CHECK-P9-NEXT: xvcvspdp vs0, vs0
@ -329,7 +329,7 @@ define <2 x i64> @test2elt_signed(i64 %a.coerce) local_unnamed_addr #0 {
;
; CHECK-BE-LABEL: test2elt_signed:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrd f0, r3
; CHECK-BE-NEXT: mtfprd f0, r3
; CHECK-BE-NEXT: xxmrghw vs0, vs0, vs0
; CHECK-BE-NEXT: xvcvspdp vs0, vs0
; CHECK-BE-NEXT: xvcvdpuxds v2, vs0

624
test/CodeGen/PowerPC/vec_conv_fp32_to_i8_elts.ll
View File

File diff suppressed because it is too large Load Diff

592
test/CodeGen/PowerPC/vec_conv_fp64_to_i16_elts.ll
View File

File diff suppressed because it is too large Load Diff

20
test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll
View File

@ -15,15 +15,15 @@ define i64 @test2elt(<2 x double> %a) local_unnamed_addr #0 {
; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: xscvdpuxws f1, v2
; CHECK-P8-NEXT: xscvdpuxws f0, f0
; CHECK-P8-NEXT: mfvsrwz r3, f1
; CHECK-P8-NEXT: mfvsrwz r4, f0
; CHECK-P8-NEXT: mtvsrd f0, r3
; CHECK-P8-NEXT: mtvsrd f1, r4
; CHECK-P8-NEXT: mffprwz r3, f1
; CHECK-P8-NEXT: mffprwz r4, f0
; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: mtfprd f1, r4
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: vmrglw v2, v2, v3
; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mfvsrd r3, f0
; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr
;
; CHECK-P9-LABEL: test2elt:
@ -309,15 +309,15 @@ define i64 @test2elt_signed(<2 x double> %a) local_unnamed_addr #0 {
; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: xscvdpsxws f1, v2
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mfvsrwz r3, f1
; CHECK-P8-NEXT: mfvsrwz r4, f0
; CHECK-P8-NEXT: mtvsrd f0, r3
; CHECK-P8-NEXT: mtvsrd f1, r4
; CHECK-P8-NEXT: mffprwz r3, f1
; CHECK-P8-NEXT: mffprwz r4, f0
; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: mtfprd f1, r4
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: vmrglw v2, v2, v3
; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mfvsrd r3, f0
; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr
;
; CHECK-P9-LABEL: test2elt_signed:

596
test/CodeGen/PowerPC/vec_conv_fp64_to_i8_elts.ll
View File

File diff suppressed because it is too large Load Diff

20
test/CodeGen/PowerPC/vec_conv_fp_to_i_4byte_elts.ll
View File

@ -12,16 +12,16 @@
define i64 @test2elt(i64 %a.coerce) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtvsrd f0, r3
; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xvcvspuxws vs0, v2
; CHECK-P8-NEXT: xxswapd vs0, vs0
; CHECK-P8-NEXT: mfvsrd r3, f0
; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr
;
; CHECK-P9-LABEL: test2elt:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: xvcvspuxws vs0, v2
; CHECK-P9-NEXT: mfvsrld r3, vs0
@ -29,9 +29,9 @@ define i64 @test2elt(i64 %a.coerce) local_unnamed_addr #0 {
;
; CHECK-BE-LABEL: test2elt:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrd f0, r3
; CHECK-BE-NEXT: mtfprd f0, r3
; CHECK-BE-NEXT: xvcvspuxws vs0, vs0
; CHECK-BE-NEXT: mfvsrd r3, f0
; CHECK-BE-NEXT: mffprd r3, f0
; CHECK-BE-NEXT: blr
entry:
%0 = bitcast i64 %a.coerce to <2 x float>
@ -159,16 +159,16 @@ entry:
define i64 @test2elt_signed(i64 %a.coerce) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt_signed:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtvsrd f0, r3
; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xvcvspsxws vs0, v2
; CHECK-P8-NEXT: xxswapd vs0, vs0
; CHECK-P8-NEXT: mfvsrd r3, f0
; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr
;
; CHECK-P9-LABEL: test2elt_signed:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: xvcvspsxws vs0, v2
; CHECK-P9-NEXT: mfvsrld r3, vs0
@ -176,9 +176,9 @@ define i64 @test2elt_signed(i64 %a.coerce) local_unnamed_addr #0 {
;
; CHECK-BE-LABEL: test2elt_signed:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrd f0, r3
; CHECK-BE-NEXT: mtfprd f0, r3
; CHECK-BE-NEXT: xvcvspsxws vs0, vs0
; CHECK-BE-NEXT: mfvsrd r3, f0
; CHECK-BE-NEXT: mffprd r3, f0
; CHECK-BE-NEXT: blr
entry:
%0 = bitcast i64 %a.coerce to <2 x float>

32
test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll
View File

@ -12,12 +12,12 @@
define i64 @test2elt(i32 %a.coerce) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtvsrd f0, r3
; CHECK-P8-NEXT: mfvsrd r3, f0
; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: clrldi r4, r3, 48
; CHECK-P8-NEXT: rldicl r3, r3, 48, 48
; CHECK-P8-NEXT: rlwinm r4, r4, 0, 16, 31
; CHECK-P8-NEXT: rlwinm r3, r3, 0, 16, 31
; CHECK-P8-NEXT: clrlwi r4, r4, 16
; CHECK-P8-NEXT: clrlwi r3, r3, 16
; CHECK-P8-NEXT: mtfprwz f0, r4
; CHECK-P8-NEXT: mtfprwz f1, r3
; CHECK-P8-NEXT: xscvuxdsp f0, f0
@ -28,7 +28,7 @@ define i64 @test2elt(i32 %a.coerce) local_unnamed_addr #0 {
; CHECK-P8-NEXT: xxsldwi v3, vs1, vs1, 1
; CHECK-P8-NEXT: vmrglw v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mfvsrd r3, f0
; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr
;
; CHECK-P9-LABEL: test2elt:
@ -36,13 +36,13 @@ define i64 @test2elt(i32 %a.coerce) local_unnamed_addr #0 {
; CHECK-P9-NEXT: mtvsrws v2, r3
; CHECK-P9-NEXT: li r3, 0
; CHECK-P9-NEXT: vextuhrx r3, r3, v2
; CHECK-P9-NEXT: rlwinm r3, r3, 0, 16, 31
; CHECK-P9-NEXT: clrlwi r3, r3, 16
; CHECK-P9-NEXT: mtfprwz f0, r3
; CHECK-P9-NEXT: li r3, 2
; CHECK-P9-NEXT: xscvuxdsp f0, f0
; CHECK-P9-NEXT: xscvdpspn vs0, f0
; CHECK-P9-NEXT: vextuhrx r3, r3, v2
; CHECK-P9-NEXT: rlwinm r3, r3, 0, 16, 31
; CHECK-P9-NEXT: clrlwi r3, r3, 16
; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 1
; CHECK-P9-NEXT: mtfprwz f0, r3
; CHECK-P9-NEXT: xscvuxdsp f0, f0
@ -57,12 +57,12 @@ define i64 @test2elt(i32 %a.coerce) local_unnamed_addr #0 {
; CHECK-BE-NEXT: mtvsrws v2, r3
; CHECK-BE-NEXT: li r3, 2
; CHECK-BE-NEXT: vextuhlx r3, r3, v2
; CHECK-BE-NEXT: rlwinm r3, r3, 0, 16, 31
; CHECK-BE-NEXT: clrlwi r3, r3, 16
; CHECK-BE-NEXT: mtfprwz f0, r3
; CHECK-BE-NEXT: li r3, 0
; CHECK-BE-NEXT: xscvuxdsp f0, f0
; CHECK-BE-NEXT: vextuhlx r3, r3, v2
; CHECK-BE-NEXT: rlwinm r3, r3, 0, 16, 31
; CHECK-BE-NEXT: clrlwi r3, r3, 16
; CHECK-BE-NEXT: xscvdpspn v3, f0
; CHECK-BE-NEXT: mtfprwz f0, r3
; CHECK-BE-NEXT: xscvuxdsp f0, f0
@ -81,7 +81,7 @@ define <4 x float> @test4elt(i64 %a.coerce) local_unnamed_addr #1 {
; CHECK-P8-LABEL: test4elt:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r4, r2, .LCPI1_0@toc@ha
; CHECK-P8-NEXT: mtvsrd f0, r3
; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: addi r3, r4, .LCPI1_0@toc@l
; CHECK-P8-NEXT: xxlxor v4, v4, v4
; CHECK-P8-NEXT: xxswapd v2, vs0
@ -92,7 +92,7 @@ define <4 x float> @test4elt(i64 %a.coerce) local_unnamed_addr #1 {
;
; CHECK-P9-LABEL: test4elt:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: addis r3, r2, .LCPI1_0@toc@ha
; CHECK-P9-NEXT: addi r3, r3, .LCPI1_0@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r3
@ -264,8 +264,8 @@ entry:
define i64 @test2elt_signed(i32 %a.coerce) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt_signed:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtvsrd f0, r3
; CHECK-P8-NEXT: mfvsrd r3, f0
; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: clrldi r4, r3, 48
; CHECK-P8-NEXT: rldicl r3, r3, 48, 48
; CHECK-P8-NEXT: extsh r4, r4
@ -280,7 +280,7 @@ define i64 @test2elt_signed(i32 %a.coerce) local_unnamed_addr #0 {
; CHECK-P8-NEXT: xxsldwi v3, vs1, vs1, 1
; CHECK-P8-NEXT: vmrglw v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mfvsrd r3, f0
; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr
;
; CHECK-P9-LABEL: test2elt_signed:
@ -332,7 +332,7 @@ entry:
define <4 x float> @test4elt_signed(i64 %a.coerce) local_unnamed_addr #1 {
; CHECK-P8-LABEL: test4elt_signed:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtvsrd f0, r3
; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: vspltisw v3, 8
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: vadduwm v3, v3, v3
@ -344,7 +344,7 @@ define <4 x float> @test4elt_signed(i64 %a.coerce) local_unnamed_addr #1 {
;
; CHECK-P9-LABEL: test4elt_signed:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: vmrglh v2, v2, v2
; CHECK-P9-NEXT: vextsh2w v2, v2

12
test/CodeGen/PowerPC/vec_conv_i16_to_fp64_elts.ll
View File

@ -13,7 +13,7 @@ define <2 x double> @test2elt(i32 %a.coerce) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r4, r2, .LCPI0_0@toc@ha
; CHECK-P8-NEXT: mtvsrd f0, r3
; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: addi r3, r4, .LCPI0_0@toc@l
; CHECK-P8-NEXT: xxlxor v4, v4, v4
; CHECK-P8-NEXT: xxswapd v2, vs0
@ -53,7 +53,7 @@ define void @test4elt(<4 x double>* noalias nocapture sret %agg.result, i64 %a.c
; CHECK-P8-LABEL: test4elt:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r5, r2, .LCPI1_0@toc@ha
; CHECK-P8-NEXT: mtvsrd f0, r4
; CHECK-P8-NEXT: mtfprd f0, r4
; CHECK-P8-NEXT: addis r4, r2, .LCPI1_1@toc@ha
; CHECK-P8-NEXT: addi r5, r5, .LCPI1_0@toc@l
; CHECK-P8-NEXT: addi r4, r4, .LCPI1_1@toc@l
@ -74,7 +74,7 @@ define void @test4elt(<4 x double>* noalias nocapture sret %agg.result, i64 %a.c
;
; CHECK-P9-LABEL: test4elt:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrd f0, r4
; CHECK-P9-NEXT: mtfprd f0, r4
; CHECK-P9-NEXT: addis r4, r2, .LCPI1_0@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI1_0@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r4
@ -370,7 +370,7 @@ define <2 x double> @test2elt_signed(i32 %a.coerce) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt_signed:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r4, r2, .LCPI4_0@toc@ha
; CHECK-P8-NEXT: mtvsrd f0, r3
; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: addi r3, r4, .LCPI4_0@toc@l
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: lvx v3, 0, r3
@ -415,7 +415,7 @@ define void @test4elt_signed(<4 x double>* noalias nocapture sret %agg.result, i
; CHECK-P8-LABEL: test4elt_signed:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r5, r2, .LCPI5_0@toc@ha
; CHECK-P8-NEXT: mtvsrd f0, r4
; CHECK-P8-NEXT: mtfprd f0, r4
; CHECK-P8-NEXT: addis r4, r2, .LCPI5_2@toc@ha
; CHECK-P8-NEXT: addi r5, r5, .LCPI5_0@toc@l
; CHECK-P8-NEXT: addi r4, r4, .LCPI5_2@toc@l
@ -443,7 +443,7 @@ define void @test4elt_signed(<4 x double>* noalias nocapture sret %agg.result, i
;
; CHECK-P9-LABEL: test4elt_signed:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrd f0, r4
; CHECK-P9-NEXT: mtfprd f0, r4
; CHECK-P9-NEXT: addis r4, r2, .LCPI5_0@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI5_0@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r4

12
test/CodeGen/PowerPC/vec_conv_i32_to_fp64_elts.ll
View File

@ -12,7 +12,7 @@
define <2 x double> @test2elt(i64 %a.coerce) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtvsrd f0, r3
; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxmrglw v2, v2, v2
; CHECK-P8-NEXT: xvcvuxwdp v2, v2
@ -20,7 +20,7 @@ define <2 x double> @test2elt(i64 %a.coerce) local_unnamed_addr #0 {
;
; CHECK-P9-LABEL: test2elt:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: xxmrglw v2, v2, v2
; CHECK-P9-NEXT: xvcvuxwdp v2, v2
@ -28,7 +28,7 @@ define <2 x double> @test2elt(i64 %a.coerce) local_unnamed_addr #0 {
;
; CHECK-BE-LABEL: test2elt:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrd f0, r3
; CHECK-BE-NEXT: mtfprd f0, r3
; CHECK-BE-NEXT: xxmrghw v2, vs0, vs0
; CHECK-BE-NEXT: xvcvuxwdp v2, v2
; CHECK-BE-NEXT: blr
@ -266,7 +266,7 @@ entry:
define <2 x double> @test2elt_signed(i64 %a.coerce) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt_signed:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtvsrd f0, r3
; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxmrglw v2, v2, v2
; CHECK-P8-NEXT: xvcvsxwdp v2, v2
@ -274,7 +274,7 @@ define <2 x double> @test2elt_signed(i64 %a.coerce) local_unnamed_addr #0 {
;
; CHECK-P9-LABEL: test2elt_signed:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: xxmrglw v2, v2, v2
; CHECK-P9-NEXT: xvcvsxwdp v2, v2
@ -282,7 +282,7 @@ define <2 x double> @test2elt_signed(i64 %a.coerce) local_unnamed_addr #0 {
;
; CHECK-BE-LABEL: test2elt_signed:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrd f0, r3
; CHECK-BE-NEXT: mtfprd f0, r3
; CHECK-BE-NEXT: xxmrghw v2, vs0, vs0
; CHECK-BE-NEXT: xvcvsxwdp v2, v2
; CHECK-BE-NEXT: blr

4
test/CodeGen/PowerPC/vec_conv_i64_to_fp32_elts.ll
View File

@ -22,7 +22,7 @@ define i64 @test2elt(<2 x i64> %a) local_unnamed_addr #0 {
; CHECK-P8-NEXT: xxsldwi v2, vs0, vs0, 1
; CHECK-P8-NEXT: vmrglw v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mfvsrd r3, f0
; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr
;
; CHECK-P9-LABEL: test2elt:
@ -315,7 +315,7 @@ define i64 @test2elt_signed(<2 x i64> %a) local_unnamed_addr #0 {
; CHECK-P8-NEXT: xxsldwi v2, vs0, vs0, 1
; CHECK-P8-NEXT: vmrglw v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mfvsrd r3, f0
; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr
;
; CHECK-P9-LABEL: test2elt_signed:

36
test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll
View File

@ -12,12 +12,12 @@
define i64 @test2elt(i16 %a.coerce) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtvsrd f0, r3
; CHECK-P8-NEXT: mfvsrd r3, f0
; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: clrldi r4, r3, 56
; CHECK-P8-NEXT: rldicl r3, r3, 56, 56
; CHECK-P8-NEXT: rlwinm r4, r4, 0, 24, 31
; CHECK-P8-NEXT: rlwinm r3, r3, 0, 24, 31
; CHECK-P8-NEXT: clrlwi r4, r4, 24
; CHECK-P8-NEXT: clrlwi r3, r3, 24
; CHECK-P8-NEXT: mtfprwz f0, r4
; CHECK-P8-NEXT: mtfprwz f1, r3
; CHECK-P8-NEXT: xscvuxdsp f0, f0
@ -28,7 +28,7 @@ define i64 @test2elt(i16 %a.coerce) local_unnamed_addr #0 {
; CHECK-P8-NEXT: xxsldwi v3, vs1, vs1, 1
; CHECK-P8-NEXT: vmrglw v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mfvsrd r3, f0
; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr
;
; CHECK-P9-LABEL: test2elt:
@ -36,13 +36,13 @@ define i64 @test2elt(i16 %a.coerce) local_unnamed_addr #0 {
; CHECK-P9-NEXT: mtvsrws v2, r3
; CHECK-P9-NEXT: li r3, 0
; CHECK-P9-NEXT: vextubrx r3, r3, v2
; CHECK-P9-NEXT: rlwinm r3, r3, 0, 24, 31
; CHECK-P9-NEXT: clrlwi r3, r3, 24
; CHECK-P9-NEXT: mtfprwz f0, r3
; CHECK-P9-NEXT: li r3, 1
; CHECK-P9-NEXT: xscvuxdsp f0, f0
; CHECK-P9-NEXT: xscvdpspn vs0, f0
; CHECK-P9-NEXT: vextubrx r3, r3, v2
; CHECK-P9-NEXT: rlwinm r3, r3, 0, 24, 31
; CHECK-P9-NEXT: clrlwi r3, r3, 24
; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 1
; CHECK-P9-NEXT: mtfprwz f0, r3
; CHECK-P9-NEXT: xscvuxdsp f0, f0
@ -57,12 +57,12 @@ define i64 @test2elt(i16 %a.coerce) local_unnamed_addr #0 {
; CHECK-BE-NEXT: mtvsrws v2, r3
; CHECK-BE-NEXT: li r3, 1
; CHECK-BE-NEXT: vextublx r3, r3, v2
; CHECK-BE-NEXT: rlwinm r3, r3, 0, 24, 31
; CHECK-BE-NEXT: clrlwi r3, r3, 24
; CHECK-BE-NEXT: mtfprwz f0, r3
; CHECK-BE-NEXT: li r3, 0
; CHECK-BE-NEXT: xscvuxdsp f0, f0
; CHECK-BE-NEXT: vextublx r3, r3, v2
; CHECK-BE-NEXT: rlwinm r3, r3, 0, 24, 31
; CHECK-BE-NEXT: clrlwi r3, r3, 24
; CHECK-BE-NEXT: xscvdpspn v3, f0
; CHECK-BE-NEXT: mtfprwz f0, r3
; CHECK-BE-NEXT: xscvuxdsp f0, f0
@ -81,7 +81,7 @@ define <4 x float> @test4elt(i32 %a.coerce) local_unnamed_addr #1 {
; CHECK-P8-LABEL: test4elt:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r4, r2, .LCPI1_0@toc@ha
; CHECK-P8-NEXT: mtvsrd f0, r3
; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: addi r3, r4, .LCPI1_0@toc@l
; CHECK-P8-NEXT: xxlxor v4, v4, v4
; CHECK-P8-NEXT: xxswapd v2, vs0
@ -121,7 +121,7 @@ define void @test8elt(<8 x float>* noalias nocapture sret %agg.result, i64 %a.co
; CHECK-P8-LABEL: test8elt:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r5, r2, .LCPI2_0@toc@ha
; CHECK-P8-NEXT: mtvsrd f0, r4
; CHECK-P8-NEXT: mtfprd f0, r4
; CHECK-P8-NEXT: addis r4, r2, .LCPI2_1@toc@ha
; CHECK-P8-NEXT: addi r5, r5, .LCPI2_0@toc@l
; CHECK-P8-NEXT: addi r4, r4, .LCPI2_1@toc@l
@ -140,7 +140,7 @@ define void @test8elt(<8 x float>* noalias nocapture sret %agg.result, i64 %a.co
;
; CHECK-P9-LABEL: test8elt:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrd f0, r4
; CHECK-P9-NEXT: mtfprd f0, r4
; CHECK-P9-NEXT: addis r4, r2, .LCPI2_0@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI2_0@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r4
@ -280,8 +280,8 @@ entry:
define i64 @test2elt_signed(i16 %a.coerce) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt_signed:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtvsrd f0, r3
; CHECK-P8-NEXT: mfvsrd r3, f0
; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: clrldi r4, r3, 56
; CHECK-P8-NEXT: rldicl r3, r3, 56, 56
; CHECK-P8-NEXT: extsb r4, r4
@ -296,7 +296,7 @@ define i64 @test2elt_signed(i16 %a.coerce) local_unnamed_addr #0 {
; CHECK-P8-NEXT: xxsldwi v3, vs1, vs1, 1
; CHECK-P8-NEXT: vmrglw v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mfvsrd r3, f0
; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr
;
; CHECK-P9-LABEL: test2elt_signed:
@ -349,7 +349,7 @@ define <4 x float> @test4elt_signed(i32 %a.coerce) local_unnamed_addr #1 {
; CHECK-P8-LABEL: test4elt_signed:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r4, r2, .LCPI5_0@toc@ha
; CHECK-P8-NEXT: mtvsrd f0, r3
; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: addi r3, r4, .LCPI5_0@toc@l
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: lvx v3, 0, r3
@ -392,7 +392,7 @@ define void @test8elt_signed(<8 x float>* noalias nocapture sret %agg.result, i6
; CHECK-P8-LABEL: test8elt_signed:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r5, r2, .LCPI6_0@toc@ha
; CHECK-P8-NEXT: mtvsrd f0, r4
; CHECK-P8-NEXT: mtfprd f0, r4
; CHECK-P8-NEXT: addis r4, r2, .LCPI6_1@toc@ha
; CHECK-P8-NEXT: vspltisw v5, 12
; CHECK-P8-NEXT: addi r5, r5, .LCPI6_0@toc@l
@ -416,7 +416,7 @@ define void @test8elt_signed(<8 x float>* noalias nocapture sret %agg.result, i6
;
; CHECK-P9-LABEL: test8elt_signed:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrd f0, r4
; CHECK-P9-NEXT: mtfprd f0, r4
; CHECK-P9-NEXT: addis r4, r2, .LCPI6_0@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI6_0@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r4

16
test/CodeGen/PowerPC/vec_conv_i8_to_fp64_elts.ll
View File

@ -13,7 +13,7 @@ define <2 x double> @test2elt(i16 %a.coerce) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r4, r2, .LCPI0_0@toc@ha
; CHECK-P8-NEXT: mtvsrd f0, r3
; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: addi r3, r4, .LCPI0_0@toc@l
; CHECK-P8-NEXT: xxlxor v4, v4, v4
; CHECK-P8-NEXT: xxswapd v2, vs0
@ -53,7 +53,7 @@ define void @test4elt(<4 x double>* noalias nocapture sret %agg.result, i32 %a.c
; CHECK-P8-LABEL: test4elt:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r5, r2, .LCPI1_0@toc@ha
; CHECK-P8-NEXT: mtvsrd f0, r4
; CHECK-P8-NEXT: mtfprd f0, r4
; CHECK-P8-NEXT: addis r4, r2, .LCPI1_1@toc@ha
; CHECK-P8-NEXT: addi r5, r5, .LCPI1_0@toc@l
; CHECK-P8-NEXT: addi r4, r4, .LCPI1_1@toc@l
@ -118,7 +118,7 @@ define void @test8elt(<8 x double>* noalias nocapture sret %agg.result, i64 %a.c
; CHECK-P8-LABEL: test8elt:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r5, r2, .LCPI2_0@toc@ha
; CHECK-P8-NEXT: mtvsrd f0, r4
; CHECK-P8-NEXT: mtfprd f0, r4
; CHECK-P8-NEXT: addis r4, r2, .LCPI2_2@toc@ha
; CHECK-P8-NEXT: addi r5, r5, .LCPI2_0@toc@l
; CHECK-P8-NEXT: addi r4, r4, .LCPI2_2@toc@l
@ -155,7 +155,7 @@ define void @test8elt(<8 x double>* noalias nocapture sret %agg.result, i64 %a.c
;
; CHECK-P9-LABEL: test8elt:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrd f0, r4
; CHECK-P9-NEXT: mtfprd f0, r4
; CHECK-P9-NEXT: addis r4, r2, .LCPI2_0@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI2_0@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r4
@ -404,7 +404,7 @@ define <2 x double> @test2elt_signed(i16 %a.coerce) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt_signed:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r4, r2, .LCPI4_0@toc@ha
; CHECK-P8-NEXT: mtvsrd f0, r3
; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: addi r3, r4, .LCPI4_0@toc@l
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: lvx v3, 0, r3
@ -449,7 +449,7 @@ define void @test4elt_signed(<4 x double>* noalias nocapture sret %agg.result, i
; CHECK-P8-LABEL: test4elt_signed:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r5, r2, .LCPI5_0@toc@ha
; CHECK-P8-NEXT: mtvsrd f0, r4
; CHECK-P8-NEXT: mtfprd f0, r4
; CHECK-P8-NEXT: addis r4, r2, .LCPI5_2@toc@ha
; CHECK-P8-NEXT: addi r5, r5, .LCPI5_0@toc@l
; CHECK-P8-NEXT: addi r4, r4, .LCPI5_2@toc@l
@ -523,7 +523,7 @@ entry:
define void @test8elt_signed(<8 x double>* noalias nocapture sret %agg.result, i64 %a.coerce) local_unnamed_addr #1 {
; CHECK-P8-LABEL: test8elt_signed:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtvsrd f0, r4
; CHECK-P8-NEXT: mtfprd f0, r4
; CHECK-P8-NEXT: addis r4, r2, .LCPI6_2@toc@ha
; CHECK-P8-NEXT: addis r5, r2, .LCPI6_0@toc@ha
; CHECK-P8-NEXT: addis r6, r2, .LCPI6_3@toc@ha
@ -572,7 +572,7 @@ define void @test8elt_signed(<8 x double>* noalias nocapture sret %agg.result, i
;
; CHECK-P9-LABEL: test8elt_signed:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrd f0, r4
; CHECK-P9-NEXT: mtfprd f0, r4
; CHECK-P9-NEXT: addis r4, r2, .LCPI6_0@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI6_0@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r4

20
test/CodeGen/PowerPC/vec_conv_i_to_fp_4byte_elts.ll
View File

@ -12,16 +12,16 @@
define i64 @test2elt(i64 %a.coerce) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtvsrd f0, r3
; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xvcvuxwsp vs0, v2
; CHECK-P8-NEXT: xxswapd vs0, vs0
; CHECK-P8-NEXT: mfvsrd r3, f0
; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr
;
; CHECK-P9-LABEL: test2elt:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: xvcvuxwsp vs0, v2
; CHECK-P9-NEXT: mfvsrld r3, vs0
@ -29,9 +29,9 @@ define i64 @test2elt(i64 %a.coerce) local_unnamed_addr #0 {
;
; CHECK-BE-LABEL: test2elt:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrd f0, r3
; CHECK-BE-NEXT: mtfprd f0, r3
; CHECK-BE-NEXT: xvcvuxwsp vs0, vs0
; CHECK-BE-NEXT: mfvsrd r3, f0
; CHECK-BE-NEXT: mffprd r3, f0
; CHECK-BE-NEXT: blr
entry:
%0 = bitcast i64 %a.coerce to <2 x i32>
@ -159,16 +159,16 @@ entry:
define i64 @test2elt_signed(i64 %a.coerce) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt_signed:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtvsrd f0, r3
; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xvcvsxwsp vs0, v2
; CHECK-P8-NEXT: xxswapd vs0, vs0
; CHECK-P8-NEXT: mfvsrd r3, f0
; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr
;
; CHECK-P9-LABEL: test2elt_signed:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrd f0, r3
; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: xvcvsxwsp vs0, v2
; CHECK-P9-NEXT: mfvsrld r3, vs0
@ -176,9 +176,9 @@ define i64 @test2elt_signed(i64 %a.coerce) local_unnamed_addr #0 {
;
; CHECK-BE-LABEL: test2elt_signed:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrd f0, r3
; CHECK-BE-NEXT: mtfprd f0, r3
; CHECK-BE-NEXT: xvcvsxwsp vs0, vs0
; CHECK-BE-NEXT: mfvsrd r3, f0
; CHECK-BE-NEXT: mffprd r3, f0
; CHECK-BE-NEXT: blr
entry:
%0 = bitcast i64 %a.coerce to <2 x i32>

2
test/CodeGen/PowerPC/vsx.ll
View File

@ -2437,7 +2437,7 @@ define <2 x i32> @test80(i32 %v) {
;
; CHECK-LE-LABEL: test80:
; CHECK-LE: # %bb.0:
; CHECK-LE-NEXT: mtvsrd f0, r3
; CHECK-LE-NEXT: mtfprd f0, r3
; CHECK-LE-NEXT: addis r4, r2, .LCPI65_0@toc@ha
; CHECK-LE-NEXT: addi r3, r4, .LCPI65_0@toc@l
; CHECK-LE-NEXT: xxswapd vs0, vs0

8
test/CodeGen/PowerPC/xray-conditional-return.ll
View File

@ -2,8 +2,8 @@
define void @Foo(i32 signext %a, i32 signext %b) #0 {
; CHECK-LABEL: @Foo
; CHECK: cmpw [[CR:[0-9]+]]
; CHECK-NEXT: ble [[CR]], [[LABEL:\.[a-zA-Z0-9]+]]
; CHECK: cmpw
; CHECK-NEXT: ble 0, [[LABEL:\.[a-zA-Z0-9]+]]
; CHECK-NEXT: .p2align 3
; CHECK-NEXT: {{\.[a-zA-Z0-9]+}}:
; CHECK-NEXT: blr
@ -39,8 +39,8 @@ return:
define void @Foo2(i32 signext %a, i32 signext %b) #0 {
; CHECK-LABEL: @Foo2
; CHECK: cmpw [[CR:[0-9]+]]
; CHECK-NEXT: bge [[CR]], [[LABEL:\.[a-zA-Z0-9]+]]
; CHECK: cmpw
; CHECK-NEXT: bge 0, [[LABEL:\.[a-zA-Z0-9]+]]
; CHECK-NEXT: .p2align 3
; CHECK-NEXT: {{\.[a-zA-Z0-9]+}}:
; CHECK-NEXT: blr