mirror of
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Fix typos found by http://github.com/lyda/misspell-check
llvm-svn: 157885
This commit is contained in:
Benjamin Kramer
parent
4246540c22
commit
bb30e1face
@ -110,7 +110,7 @@ indicates greater chance to be taken.</p>
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<h4><tt>if</tt> statement</h4>
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<div>
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<p>The <tt>exp</tt> parameter is the condition. The <tt>c</tt> parameter is
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the expected comparision value. If it is equal to 1 (true), the condition is
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the expected comparison value. If it is equal to 1 (true), the condition is
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likely to be true, in other case condition is likely to be false. For example:
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</p>
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</div>
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@ -331,7 +331,7 @@
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<dt><b>LLVM_TABLEGEN</b>:STRING</dt>
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<dd>Full path to a native TableGen executable (usually
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named <i>tblgen</i>). This is intented for cross-compiling: if the
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named <i>tblgen</i>). This is intended for cross-compiling: if the
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user sets this variable, no native TableGen will be created.</dd>
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<dt><b>LLVM_LIT_ARGS</b>:STRING</dt>
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@ -442,7 +442,7 @@ following format.
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... log message ...
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<log delineator>
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where <test name> should be the name of a preceeding reported test, <log
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where <test name> should be the name of a preceding reported test, <log
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delineator> is a string of '\*' characters *at least* four characters long (the
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recommended length is 20), and <trailing delineator> is an arbitrary (unparsed)
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string.
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@ -61,7 +61,7 @@ OPTIONS
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Write out new *LLVMBuild.txt* files based on the loaded components. This is
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useful for auto-upgrading the schema of the files. **llvm-build** will try to a
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limited extent to preserve the comments which were written in the original
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source file, although at this time it only preserves block comments that preceed
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source file, although at this time it only preserves block comments that precede
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the section names in the *LLVMBuild* files.
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@ -1617,7 +1617,7 @@ if (X < 3) {</pre>
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</h3>
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<div>
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<p>
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This file demotes all registers to memory references. It is intented to be
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This file demotes all registers to memory references. It is intended to be
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the inverse of <a href="#mem2reg"><tt>-mem2reg</tt></a>. By converting to
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<tt>load</tt> instructions, the only values live across basic blocks are
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<tt>alloca</tt> instructions and <tt>load</tt> instructions before
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@ -2712,7 +2712,7 @@ HashData[hash_data_count]
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has address attributes: DW_AT_low_pc, DW_AT_high_pc, DW_AT_ranges or
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DW_AT_entry_pc. It also contains DW_TAG_variable DIEs that have a DW_OP_addr
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in the location (global and static variables). All global and static variables
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should be included, including those scoped withing functions and classes. For
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should be included, including those scoped within functions and classes. For
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example using the following code:</p>
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<div class="doc_code">
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<pre>
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@ -13,7 +13,7 @@ industrial strength compilers to specialized JIT applications to small
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research projects.
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Similarly, documentation is broken down into several high-level groupings
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targetted at different audiences:
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targeted at different audiences:
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* **Design & Overview**
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@ -1257,7 +1257,7 @@ llvm::Function *createCatchWrappedInvokeFunction(llvm::Module &module,
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// FIXME: Redundant storage which, beyond utilizing value of
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// caughtResultStore for unwindException storage, may be alleviated
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// alltogether with a block rearrangement
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// altogether with a block rearrangement
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builder.CreateStore(caughtResult, caughtResultStorage);
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builder.CreateStore(unwindException, exceptionStorage);
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builder.CreateStore(ourExceptionThrownState, exceptionCaughtFlag);
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@ -2115,7 +2115,7 @@ LLVMBasicBlockRef LLVMGetInstructionParent(LLVMValueRef Inst);
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LLVMValueRef LLVMGetNextInstruction(LLVMValueRef Inst);
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/**
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* Obtain the instruction that occured before this one.
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* Obtain the instruction that occurred before this one.
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*
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* If the instruction is the first instruction in a basic block, NULL
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* will be returned.
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@ -217,7 +217,7 @@ class BlockFrequencyImpl {
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divBlockFreq(BB, BranchProbability(Numerator, EntryFreq));
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}
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/// doLoop - Propagate block frequency down throught the loop.
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/// doLoop - Propagate block frequency down through the loop.
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void doLoop(BlockT *Head, BlockT *Tail) {
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DEBUG(dbgs() << "doLoop(" << getBlockName(Head) << ", "
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<< getBlockName(Tail) << ")\n");
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@ -177,7 +177,7 @@ namespace llvm {
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/// @param OffsetInBits Member offset.
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/// @param Flags Flags to encode member attribute, e.g. private
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/// @param Ty Parent type.
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/// @param PropertyName Name of the Objective C property assoicated with
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/// @param PropertyName Name of the Objective C property associated with
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/// this ivar.
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/// @param GetterName Name of the Objective C property getter selector.
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/// @param SetterName Name of the Objective C property setter selector.
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@ -582,7 +582,7 @@ namespace ISD {
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// TRAP - Trapping instruction
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TRAP,
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// DEBUGTRAP - Trap intented to get the attention of a debugger.
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// DEBUGTRAP - Trap intended to get the attention of a debugger.
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DEBUGTRAP,
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// PREFETCH - This corresponds to a prefetch intrinsic. It takes chains are
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@ -230,7 +230,7 @@ namespace llvm {
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///
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LoopDependencies LoopRegs;
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/// DbgValues - Remember instruction that preceeds DBG_VALUE.
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/// DbgValues - Remember instruction that precedes DBG_VALUE.
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/// These are generated by buildSchedGraph but persist so they can be
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/// referenced when emitting the final schedule.
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typedef std::vector<std::pair<MachineInstr *, MachineInstr *> >
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@ -576,7 +576,7 @@ namespace llvm {
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nextItr = getIndexAfter(mi).listEntry();
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prevItr = prior(nextItr);
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} else {
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// Insert mi's index immediately after the preceeding instruction.
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// Insert mi's index immediately after the preceding instruction.
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prevItr = getIndexBefore(mi).listEntry();
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nextItr = llvm::next(prevItr);
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}
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@ -2239,7 +2239,7 @@ public:
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/// getNumClauses - Get the number of clauses for this landing pad.
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unsigned getNumClauses() const { return getNumOperands() - 1; }
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/// reserveClauses - Grow the size of the operand list to accomodate the new
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/// reserveClauses - Grow the size of the operand list to accommodate the new
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/// number of clauses.
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void reserveClauses(unsigned Size) { growOperands(Size); }
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@ -90,7 +90,7 @@ public:
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/// @brief Create a Binary from Source, autodetecting the file type.
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///
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/// @param Source The data to create the Binary from. Ownership is transfered
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/// @param Source The data to create the Binary from. Ownership is transferred
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/// to Result if successful. If an error is returned, Source is destroyed
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/// by createBinary before returning.
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/// @param Result A pointer to the resulting Binary if no error occured.
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@ -217,7 +217,7 @@ struct Elf_Verdef_Impl {
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}
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};
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/// Elf_Verdaux: This is the structure of auxilary data in the SHT_GNU_verdef
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/// Elf_Verdaux: This is the structure of auxiliary data in the SHT_GNU_verdef
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/// section (.gnu.version_d). This structure is identical for ELF32 and ELF64.
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template<support::endianness target_endianness, bool is64Bits>
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struct Elf_Verdaux_Impl {
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@ -102,7 +102,7 @@ public:
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return (const APInt&)ConstantIntVal->getValue();
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}
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// Propogate APInt operators.
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// Propagate APInt operators.
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// Note, that
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// /,/=,>>,>>= are not implemented in APInt.
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// <<= is implemented for unsigned RHS, but not implemented for APInt RHS.
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@ -178,7 +178,7 @@ bool CallAnalyzer::lookupSROAArgAndCost(
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/// \brief Disable SROA for the candidate marked by this cost iterator.
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///
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/// This markes the candidate as no longer viable for SROA, and adds the cost
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/// This marks the candidate as no longer viable for SROA, and adds the cost
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/// savings associated with it back into the inline cost measurement.
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void CallAnalyzer::disableSROA(DenseMap<Value *, int>::iterator CostIt) {
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// If we're no longer able to perform SROA we need to undo its cost savings
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@ -906,7 +906,7 @@ getNonLocalPointerDepFromBB(const PHITransAddr &Pointer,
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if (!Pair.second) {
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if (CacheInfo->Size < Loc.Size) {
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// The query's Size is greater than the cached one. Throw out the
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// cached data and procede with the query at the greater size.
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// cached data and proceed with the query at the greater size.
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CacheInfo->Pair = BBSkipFirstBlockPair();
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CacheInfo->Size = Loc.Size;
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for (NonLocalDepInfo::iterator DI = CacheInfo->NonLocalDeps.begin(),
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@ -1838,7 +1838,7 @@ static uint64_t umul_ov(uint64_t i, uint64_t j, bool &Overflow) {
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/// Compute the result of "n choose k", the binomial coefficient. If an
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/// intermediate computation overflows, Overflow will be set and the return will
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/// be garbage. Overflow is not cleared on absense of overflow.
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/// be garbage. Overflow is not cleared on absence of overflow.
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static uint64_t Choose(uint64_t n, uint64_t k, bool &Overflow) {
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// We use the multiplicative formula:
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// n(n-1)(n-2)...(n-(k-1)) / k(k-1)(k-2)...1 .
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@ -1466,7 +1466,7 @@ static MachineBasicBlock *findFalseBlock(MachineBasicBlock *BB,
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}
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/// findHoistingInsertPosAndDeps - Find the location to move common instructions
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/// in successors to. The location is ususally just before the terminator,
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/// in successors to. The location is usually just before the terminator,
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/// however if the terminator is a conditional branch and its previous
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/// instruction is the flag setting instruction, the previous instruction is
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/// the preferred location. This function also gathers uses and defs of the
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@ -201,7 +201,7 @@ bool CodePlacementOpt::EliminateUnconditionalJumpsToTop(MachineFunction &MF,
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// fallthrough edge.
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if (!Prior->isSuccessor(End))
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goto next_pred;
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// Otherwise we can stop scanning and procede to move the blocks.
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// Otherwise we can stop scanning and proceed to move the blocks.
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break;
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}
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// If we hit a switch or something complicated, don't move anything
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@ -228,7 +228,7 @@ void CriticalAntiDepBreaker::PrescanInstruction(MachineInstr *MI) {
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void CriticalAntiDepBreaker::ScanInstruction(MachineInstr *MI,
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unsigned Count) {
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// Update liveness.
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// Proceding upwards, registers that are defed but not used in this
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// Proceeding upwards, registers that are defed but not used in this
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// instruction are now dead.
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if (!TII->isPredicated(MI)) {
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@ -59,7 +59,7 @@ struct DomainValue {
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// Pointer to the next DomainValue in a chain. When two DomainValues are
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// merged, Victim.Next is set to point to Victor, so old DomainValue
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// references can be updated by folowing the chain.
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// references can be updated by following the chain.
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DomainValue *Next;
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// Twiddleable instructions using or defining these registers.
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@ -11,7 +11,7 @@
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// structure and branch probability estimates.
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//
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// The pass strives to preserve the structure of the CFG (that is, retain
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// a topological ordering of basic blocks) in the absense of a *strong* signal
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// a topological ordering of basic blocks) in the absence of a *strong* signal
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// to the contrary from probabilities. However, within the CFG structure, it
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// attempts to choose an ordering which favors placing more likely sequences of
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// blocks adjacent to each other.
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@ -180,7 +180,7 @@ class MachineBlockPlacement : public MachineFunctionPass {
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/// \brief Allocator and owner of BlockChain structures.
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///
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/// We build BlockChains lazily by merging together high probability BB
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/// sequences acording to the "Algo2" in the paper mentioned at the top of
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/// sequences according to the "Algo2" in the paper mentioned at the top of
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/// the file. To reduce malloc traffic, we allocate them using this slab-like
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/// allocator, and destroy them after the pass completes.
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SpecificBumpPtrAllocator<BlockChain> ChainAllocator;
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@ -329,7 +329,7 @@ MachineBasicBlock *MachineBlockPlacement::selectBestSuccessor(
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// the MBPI analysis, we manually compute probabilities using the edge
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// weights. This is suboptimal as it means that the somewhat subtle
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// definition of edge weight semantics is encoded here as well. We should
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// improve the MBPI interface to effeciently support query patterns such as
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// improve the MBPI interface to efficiently support query patterns such as
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// this.
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uint32_t BestWeight = 0;
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uint32_t WeightScale = 0;
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@ -1053,7 +1053,7 @@ namespace {
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///
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/// A separate pass to compute interesting statistics for evaluating block
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/// placement. This is separate from the actual placement pass so that they can
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/// be computed in the absense of any placement transformations or when using
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/// be computed in the absence of any placement transformations or when using
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/// alternative placement strategies.
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class MachineBlockPlacementStats : public MachineFunctionPass {
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/// \brief A handle to the branch probability pass.
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@ -50,7 +50,7 @@ ResourcePriorityQueue::ResourcePriorityQueue(SelectionDAGISel *IS) :
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const TargetMachine &tm = (*IS->MF).getTarget();
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ResourcesModel = tm.getInstrInfo()->CreateTargetScheduleState(&tm,NULL);
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// This hard requirment could be relaxed, but for now
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// This hard requirement could be relaxed, but for now
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// do not let it procede.
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assert (ResourcesModel && "Unimplemented CreateTargetScheduleState.");
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@ -353,7 +353,7 @@ signed ResourcePriorityQueue::rawRegPressureDelta(SUnit *SU, unsigned RCId) {
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}
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/// Estimates change in reg pressure from this SU.
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/// It is acheived by trivial tracking of defined
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/// It is achieved by trivial tracking of defined
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/// and used vregs in dependent instructions.
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/// The RawPressure flag makes this function to ignore
|
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/// existing reg file sizes, and report raw def/use
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@ -844,7 +844,7 @@ void SelectionDAGBuilder::clear() {
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}
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/// clearDanglingDebugInfo - Clear the dangling debug information
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/// map. This function is seperated from the clear so that debug
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/// map. This function is separated from the clear so that debug
|
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/// information that is dangling in a basic block can be properly
|
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/// resolved in a different basic block. This allows the
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/// SelectionDAG to resolve dangling debug information attached
|
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@ -2810,7 +2810,7 @@ void SelectionDAGBuilder::visitExtractElement(const User &I) {
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}
|
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// Utility for visitShuffleVector - Return true if every element in Mask,
|
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// begining from position Pos and ending in Pos+Size, falls within the
|
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// beginning from position Pos and ending in Pos+Size, falls within the
|
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// specified sequential range [L, L+Pos). or is undef.
|
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static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
|
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unsigned Pos, unsigned Size, int Low) {
|
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|
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@ -340,7 +340,7 @@ public:
|
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void clear();
|
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|
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/// clearDanglingDebugInfo - Clear the dangling debug information
|
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/// map. This function is seperated from the clear so that debug
|
||||
/// map. This function is separated from the clear so that debug
|
||||
/// information that is dangling in a basic block can be properly
|
||||
/// resolved in a different basic block. This allows the
|
||||
/// SelectionDAG to resolve dangling debug information attached
|
||||
|
||||
@ -2008,7 +2008,7 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
|
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}
|
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}
|
||||
|
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// Make sure we're not loosing bits from the constant.
|
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// Make sure we're not losing bits from the constant.
|
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if (MinBits < C1.getBitWidth() && MinBits > C1.getActiveBits()) {
|
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EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits);
|
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if (isTypeDesirableForOp(ISD::SETCC, MinVT)) {
|
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|
||||
@ -145,7 +145,7 @@ protected:
|
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// in the relocation list where it's stored.
|
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typedef SmallVector<RelocationEntry, 64> RelocationList;
|
||||
// Relocations to sections already loaded. Indexed by SectionID which is the
|
||||
// source of the address. The target where the address will be writen is
|
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// source of the address. The target where the address will be written is
|
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// SectionID/Offset in the relocation itself.
|
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DenseMap<unsigned, RelocationList> Relocations;
|
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|
||||
|
||||
@ -472,7 +472,7 @@ bool AsmParser::EnterIncludeFile(const std::string &Filename) {
|
||||
}
|
||||
|
||||
/// Process the specified .incbin file by seaching for it in the include paths
|
||||
/// then just emiting the byte contents of the file to the streamer. This
|
||||
/// then just emitting the byte contents of the file to the streamer. This
|
||||
/// returns true on failure.
|
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bool AsmParser::ProcessIncbinFile(const std::string &Filename) {
|
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std::string IncludedFile;
|
||||
|
||||
@ -2698,7 +2698,7 @@ defm STRHT : AI3strT<0b1011, "strht">;
|
||||
multiclass arm_ldst_mult<string asm, string sfx, bit L_bit, bit P_bit, Format f,
|
||||
InstrItinClass itin, InstrItinClass itin_upd> {
|
||||
// IA is the default, so no need for an explicit suffix on the
|
||||
// mnemonic here. Without it is the cannonical spelling.
|
||||
// mnemonic here. Without it is the canonical spelling.
|
||||
def IA :
|
||||
AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
|
||||
IndexModeNone, f, itin,
|
||||
@ -3412,7 +3412,7 @@ class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
|
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|
||||
// FIXME: The v5 pseudos are only necessary for the additional Constraint
|
||||
// property. Remove them when it's possible to add those properties
|
||||
// on an individual MachineInstr, not just an instuction description.
|
||||
// on an individual MachineInstr, not just an instruction description.
|
||||
let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in {
|
||||
def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd),
|
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(ins GPRnopc:$Rn, GPRnopc:$Rm),
|
||||
|
||||
@ -1403,7 +1403,7 @@ def : InstAlias<"nop", (tMOVr R8, R8, 14, 0)>,Requires<[IsThumb, IsThumb1Only]>;
|
||||
|
||||
// For round-trip assembly/disassembly, we have to handle a CPS instruction
|
||||
// without any iflags. That's not, strictly speaking, valid syntax, but it's
|
||||
// a useful extention and assembles to defined behaviour (the insn does
|
||||
// a useful extension and assembles to defined behaviour (the insn does
|
||||
// nothing).
|
||||
def : tInstAlias<"cps$imod", (tCPS imod_op:$imod, 0)>;
|
||||
def : tInstAlias<"cps$imod", (tCPS imod_op:$imod, 0)>;
|
||||
|
||||
@ -6789,8 +6789,8 @@ processInstruction(MCInst &Inst,
|
||||
case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
|
||||
case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
|
||||
}
|
||||
unsigned Ammount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
|
||||
if (Ammount == 32) Ammount = 0;
|
||||
unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
|
||||
if (Amount == 32) Amount = 0;
|
||||
TmpInst.setOpcode(newOpc);
|
||||
TmpInst.addOperand(Inst.getOperand(0)); // Rd
|
||||
if (isNarrow)
|
||||
@ -6798,7 +6798,7 @@ processInstruction(MCInst &Inst,
|
||||
Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
|
||||
TmpInst.addOperand(Inst.getOperand(1)); // Rn
|
||||
if (newOpc != ARM::t2RRX)
|
||||
TmpInst.addOperand(MCOperand::CreateImm(Ammount));
|
||||
TmpInst.addOperand(MCOperand::CreateImm(Amount));
|
||||
TmpInst.addOperand(Inst.getOperand(3)); // CondCode
|
||||
TmpInst.addOperand(Inst.getOperand(4));
|
||||
if (!isNarrow)
|
||||
@ -7400,7 +7400,7 @@ MatchAndEmitInstruction(SMLoc IDLoc,
|
||||
return Error(IDLoc, "invalid instruction",
|
||||
((ARMOperand*)Operands[0])->getLocRange());
|
||||
case Match_ConversionFail:
|
||||
// The converter function will have already emited a diagnostic.
|
||||
// The converter function will have already emitted a diagnostic.
|
||||
return true;
|
||||
case Match_RequiresNotITBlock:
|
||||
return Error(IDLoc, "flag setting instruction only valid outside IT block");
|
||||
|
||||
@ -491,7 +491,7 @@ bool HexagonHardwareLoops::convertToHardwareLoop(MachineLoop *L) {
|
||||
TII->get(Hexagon::NEG), CountReg).addReg(CountReg1);
|
||||
}
|
||||
|
||||
// Add the Loop instruction to the begining of the loop.
|
||||
// Add the Loop instruction to the beginning of the loop.
|
||||
BuildMI(*Preheader, InsertPos, InsertPos->getDebugLoc(),
|
||||
TII->get(Hexagon::LOOP0_r)).addMBB(LoopStart).addReg(CountReg);
|
||||
} else {
|
||||
|
||||
@ -508,7 +508,7 @@ HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
|
||||
|
||||
// Build a sequence of copy-to-reg nodes chained together with token
|
||||
// chain and flag operands which copy the outgoing args into registers.
|
||||
// The InFlag in necessary since all emited instructions must be
|
||||
// The InFlag in necessary since all emitted instructions must be
|
||||
// stuck together.
|
||||
SDValue InFlag;
|
||||
if (!isTailCall) {
|
||||
@ -528,7 +528,7 @@ HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
|
||||
// than necessary, because it means that each store effectively depends
|
||||
// on every argument instead of just those arguments it would clobber.
|
||||
//
|
||||
// Do not flag preceeding copytoreg stuff together with the following stuff.
|
||||
// Do not flag preceding copytoreg stuff together with the following stuff.
|
||||
InFlag = SDValue();
|
||||
for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
|
||||
Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
|
||||
|
||||
@ -371,7 +371,7 @@ def s4_3ImmPred : PatLeaf<(i32 imm), [{
|
||||
def u64ImmPred : PatLeaf<(i64 imm), [{
|
||||
// immS16 predicate - True if the immediate fits in a 16-bit sign extended
|
||||
// field.
|
||||
// Adding "N ||" to supress gcc unused warning.
|
||||
// Adding "N ||" to suppress gcc unused warning.
|
||||
return (N || true);
|
||||
}]>;
|
||||
|
||||
|
||||
@ -3029,7 +3029,7 @@ def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i8)),
|
||||
(i64 (SXTW (i32 (SXTB (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
|
||||
subreg_loreg))))))>;
|
||||
|
||||
// We want to prevent emiting pnot's as much as possible.
|
||||
// We want to prevent emitting pnot's as much as possible.
|
||||
// Map brcond with an unsupported setcc to a JMP_cNot.
|
||||
def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
|
||||
bb:$offset),
|
||||
|
||||
@ -9,9 +9,9 @@
|
||||
//
|
||||
// This implements NewValueJump pass in Hexagon.
|
||||
// Ideally, we should merge this as a Peephole pass prior to register
|
||||
// allocation, but becuase we have a spill in between the feeder and new value
|
||||
// allocation, but because we have a spill in between the feeder and new value
|
||||
// jump instructions, we are forced to write after register allocation.
|
||||
// Having said that, we should re-attempt to pull this ealier at some piont
|
||||
// Having said that, we should re-attempt to pull this earlier at some point
|
||||
// in future.
|
||||
|
||||
// The basic approach looks for sequence of predicated jump, compare instruciton
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
//===- HexagonRemoveExtendArgs.cpp - Remove unecessary argument sign extends =//
|
||||
//===- HexagonRemoveExtendArgs.cpp - Remove unnecessary argument sign extends //
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
|
||||
@ -16,7 +16,7 @@
|
||||
#include "llvm/MC/MCInstPrinter.h"
|
||||
|
||||
namespace llvm {
|
||||
// These enumeration declarations were orignally in MipsInstrInfo.h but
|
||||
// These enumeration declarations were originally in MipsInstrInfo.h but
|
||||
// had to be moved here to avoid circular dependencies between
|
||||
// LLVMMipsCodeGen and LLVMMipsAsmPrinter.
|
||||
namespace Mips {
|
||||
|
||||
@ -190,7 +190,7 @@ void MipsDAGToDAGISel::InitGlobalBaseReg(MachineFunction &MF) {
|
||||
// We emit only the last instruction here.
|
||||
//
|
||||
// GNU linker requires that the first two instructions appear at the beginning
|
||||
// of a funtion and no instructions be inserted before or between them.
|
||||
// of a function and no instructions be inserted before or between them.
|
||||
// The two instructions are emitted during lowering to MC layer in order to
|
||||
// avoid any reordering.
|
||||
//
|
||||
|
||||
@ -846,7 +846,7 @@ multiclass FPCONTRACT32<string OpcStr, Predicate Pred> {
|
||||
[(set Float32Regs:$dst, (fadd
|
||||
(fmul Float32Regs:$a, Float32Regs:$b),
|
||||
Float32Regs:$c))]>, Requires<[Pred]>;
|
||||
// This is to WAR a wierd bug in Tablegen that does not automatically
|
||||
// This is to WAR a weird bug in Tablegen that does not automatically
|
||||
// generate the following permutated rule rrr2 from the above rrr.
|
||||
// So we explicitly add it here. This happens to FMA32 only.
|
||||
// See the comments at FMAD32 and FMA32 for more information.
|
||||
|
||||
@ -130,7 +130,7 @@ namespace {
|
||||
// The hardware keeps track of how many FP registers are live, so we have
|
||||
// to model that exactly. Usually, each live register corresponds to an
|
||||
// FP<n> register, but when dealing with calls, returns, and inline
|
||||
// assembly, it is sometimes neccesary to have live scratch registers.
|
||||
// assembly, it is sometimes necessary to have live scratch registers.
|
||||
unsigned Stack[8]; // FP<n> Registers in each stack slot...
|
||||
unsigned StackTop; // The current top of the FP stack.
|
||||
|
||||
|
||||
@ -3191,7 +3191,7 @@ static bool isUndefOrEqual(int Val, int CmpVal) {
|
||||
return false;
|
||||
}
|
||||
|
||||
/// isSequentialOrUndefInRange - Return true if every element in Mask, begining
|
||||
/// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
|
||||
/// from position Pos and ending in Pos+Size, falls within the specified
|
||||
/// sequential range (L, L+Pos]. or is undef.
|
||||
static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
|
||||
@ -6333,7 +6333,7 @@ SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
|
||||
return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
|
||||
|
||||
if (NumElems == 4)
|
||||
// If we don't care about the second element, procede to use movss.
|
||||
// If we don't care about the second element, proceed to use movss.
|
||||
if (SVOp->getMaskElt(1) != -1)
|
||||
return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
|
||||
}
|
||||
|
||||
@ -205,7 +205,7 @@ bool VZeroUpperInserter::processBasicBlock(MachineFunction &MF,
|
||||
}
|
||||
|
||||
|
||||
// The entry MBB for the function may set the inital state to dirty if
|
||||
// The entry MBB for the function may set the initial state to dirty if
|
||||
// the function receives any YMM incoming arguments
|
||||
if (MBB == MF.begin()) {
|
||||
EntryState = ST_CLEAN;
|
||||
|
||||
@ -36,7 +36,7 @@ STATISTIC(NumCallsDeleted, "Number of call sites deleted, not inlined");
|
||||
STATISTIC(NumDeleted, "Number of functions deleted because all callers found");
|
||||
STATISTIC(NumMergedAllocas, "Number of allocas merged together");
|
||||
|
||||
// This weirdly named statistic tracks the number of times that, when attemting
|
||||
// This weirdly named statistic tracks the number of times that, when attempting
|
||||
// to inline a function A into B, we analyze the callers of B in order to see
|
||||
// if those would be more profitable and blocked inline steps.
|
||||
STATISTIC(NumCallerCallersAnalyzed, "Number of caller-callers analyzed");
|
||||
|
||||
@ -2194,7 +2194,7 @@ LSRInstance::FindUseWithSimilarFormula(const Formula &OrigF,
|
||||
return &LU;
|
||||
// This is the formula where all the registers and symbols matched;
|
||||
// there aren't going to be any others. Since we declined it, we
|
||||
// can skip the rest of the formulae and procede to the next LSRUse.
|
||||
// can skip the rest of the formulae and proceed to the next LSRUse.
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
@ -812,7 +812,7 @@ ObjCARCAliasAnalysis::getModRefInfo(ImmutableCallSite CS, const Location &Loc) {
|
||||
case IC_FusedRetainAutorelease:
|
||||
case IC_FusedRetainAutoreleaseRV:
|
||||
// These functions don't access any memory visible to the compiler.
|
||||
// Note that this doesn't include objc_retainBlock, becuase it updates
|
||||
// Note that this doesn't include objc_retainBlock, because it updates
|
||||
// pointers when it copies block data.
|
||||
return NoModRef;
|
||||
default:
|
||||
|
||||
@ -1164,7 +1164,7 @@ bool Reassociate::collectMultiplyFactors(SmallVectorImpl<ValueEntry> &Ops,
|
||||
++Count;
|
||||
if (Count == 1)
|
||||
continue;
|
||||
// Move an even number of occurences to Factors.
|
||||
// Move an even number of occurrences to Factors.
|
||||
Count &= ~1U;
|
||||
Idx -= Count;
|
||||
FactorPowerSum += Count;
|
||||
|
||||
@ -7,7 +7,7 @@
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// This file demotes all registers to memory references. It is intented to be
|
||||
// This file demotes all registers to memory references. It is intended to be
|
||||
// the inverse of PromoteMemoryToRegister. By converting to loads, the only
|
||||
// values live across basic blocks are allocas and loads before phi nodes.
|
||||
// It is intended that this should make CFG hacking much easier.
|
||||
|
||||
@ -706,7 +706,7 @@ bool llvm::EliminateDuplicatePHINodes(BasicBlock *BB) {
|
||||
CollisionMap[PN] = Old;
|
||||
break;
|
||||
}
|
||||
// Procede to the next PHI in the list.
|
||||
// Proceed to the next PHI in the list.
|
||||
OtherPN = I->second;
|
||||
}
|
||||
}
|
||||
|
||||
@ -131,7 +131,7 @@ static void ConnectProlog(Loop *L, Value *TripCount, unsigned Count,
|
||||
/// There are two value maps that are defined and used. VMap is
|
||||
/// for the values in the current loop instance. LVMap contains
|
||||
/// the values from the last loop instance. We need the LVMap values
|
||||
/// to update the inital values for the current loop instance.
|
||||
/// to update the initial values for the current loop instance.
|
||||
///
|
||||
static void CloneLoopBlocks(Loop *L,
|
||||
bool FirstCopy,
|
||||
|
||||
@ -1723,7 +1723,7 @@ bool Verifier::VerifyIntrinsicType(Type *Ty,
|
||||
}
|
||||
|
||||
case IITDescriptor::Argument:
|
||||
// Two cases here - If this is the second occurrance of an argument, verify
|
||||
// Two cases here - If this is the second occurrence of an argument, verify
|
||||
// that the later instance matches the previous instance.
|
||||
if (D.getArgumentNumber() < ArgTys.size())
|
||||
return Ty != ArgTys[D.getArgumentNumber()];
|
||||
|
||||
@ -345,7 +345,7 @@ TEST(HashingTest, HashCombineBasicTest) {
|
||||
EXPECT_EQ(hash_combine_range(arr1, arr1 + 6),
|
||||
hash_combine(i1, i2, i3, i4, i5, i6));
|
||||
|
||||
// Hashing a sequence of heterogenous types which *happen* to all produce the
|
||||
// Hashing a sequence of heterogeneous types which *happen* to all produce the
|
||||
// same data for hashing produces the same as a range-based hash of the
|
||||
// fundamental values.
|
||||
const size_t s1 = 1024, s2 = 8888, s3 = 9000000;
|
||||
|
||||
@ -324,7 +324,7 @@ namespace llvm {
|
||||
|
||||
Passes.run(M);
|
||||
// Some passes must be rerun because a pass that modified the
|
||||
// module/function was run inbetween
|
||||
// module/function was run in between
|
||||
EXPECT_EQ(2, mNDM->run);
|
||||
EXPECT_EQ(1, mNDNM->run);
|
||||
EXPECT_EQ(1, mNDM2->run);
|
||||
|
||||
@ -110,7 +110,7 @@ void CodeGenRegister::buildObjectGraph(CodeGenRegBank &RegBank) {
|
||||
if (CoveredBySubRegs && !ExplicitSubRegs.empty())
|
||||
ExplicitSubRegs.front()->LeadingSuperRegs.push_back(this);
|
||||
|
||||
// Add ad hoc alias links. This is a symmetric relationship betwen two
|
||||
// Add ad hoc alias links. This is a symmetric relationship between two
|
||||
// registers, so build a symmetric graph by adding links in both ends.
|
||||
std::vector<Record*> Aliases = TheDef->getValueAsListOfDefs("Aliases");
|
||||
for (unsigned i = 0, e = Aliases.size(); i != e; ++i) {
|
||||
@ -312,7 +312,7 @@ CodeGenRegister::computeSubRegs(CodeGenRegBank &RegBank) {
|
||||
// dsub_2 -> ssub_0
|
||||
//
|
||||
// We pick the latter composition because another register may have [dsub_0,
|
||||
// dsub_1, dsub_2] subregs without neccessarily having a qsub_1 subreg. The
|
||||
// dsub_1, dsub_2] subregs without necessarily having a qsub_1 subreg. The
|
||||
// dsub_2 -> ssub_0 composition can be shared.
|
||||
while (!Indices.empty() && !Orphans.empty()) {
|
||||
CodeGenSubRegIndex *Idx = Indices.pop_back_val();
|
||||
@ -919,7 +919,7 @@ void CodeGenRegisterClass::computeSubClasses(CodeGenRegBank &RegBank) {
|
||||
RC.SubClasses |= SubRC->SubClasses;
|
||||
}
|
||||
|
||||
// Sweep up missed clique members. They will be immediately preceeding RC.
|
||||
// Sweep up missed clique members. They will be immediately preceding RC.
|
||||
for (unsigned s = rci - 1; s && testSubClass(&RC, RegClasses[s - 1]); --s)
|
||||
RC.SubClasses.set(s - 1);
|
||||
}
|
||||
|
||||
@ -55,7 +55,7 @@ def make_install_dir(path):
|
||||
Create the given directory path for installation, including any parents.
|
||||
"""
|
||||
|
||||
# os.makedirs considers it an error to be called with an existant path.
|
||||
# os.makedirs considers it an error to be called with an existent path.
|
||||
if not os.path.exists(path):
|
||||
os.makedirs(path)
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user