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[lanai] Manually match 0/-1 with R0/R1.

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Summary: Previously 0 and -1 was matched via tablegen rules. But this could cause problems where a physical register was being used where a virtual register was expected (seen in optimizeSelect and TwoAddressInstructionPass). Instead follow AArch64 and match in DAGToDAGISel.

Reviewers: eliben, majnemer

Subscribers: llvm-commits, aemerson

Differential Revision: https://reviews.llvm.org/D27171

llvm-svn: 288215
This commit is contained in:
Jacques Pienaar 2016-11-29 23:01:09 +00:00
parent 62aef0dfee
commit bb32a0735a
3 changed files with 26 additions and 11 deletions
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24
lib/Target/Lanai/LanaiISelDAGToDAG.cpp
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@ -282,9 +282,29 @@ void LanaiDAGToDAGISel::Select(SDNode *Node) {
return; return;
} }
// Instruction Selection not handled by the auto-generated // Instruction Selection not handled by the auto-generated tablegen selection
// tablegen selection should be handled here. // should be handled here.
EVT VT = Node->getValueType(0);
switch (Opcode) { switch (Opcode) {
case ISD::Constant:
if (VT == MVT::i32) {
ConstantSDNode *ConstNode = cast<ConstantSDNode>(Node);
// Materialize zero constants as copies from R0. This allows the coalescer
// to propagate these into other instructions.
if (ConstNode->isNullValue()) {
SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
SDLoc(Node), Lanai::R0, MVT::i32);
return ReplaceNode(Node, New.getNode());
}
// Materialize all ones constants as copies from R1. This allows the
// coalescer to propagate these into other instructions.
if (ConstNode->isAllOnesValue()) {
SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
SDLoc(Node), Lanai::R1, MVT::i32);
return ReplaceNode(Node, New.getNode());
}
}
break;
case ISD::FrameIndex: case ISD::FrameIndex:
selectFrameIndex(Node); selectFrameIndex(Node);
return; return;

5
lib/Target/Lanai/LanaiInstrInfo.td
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@ -831,11 +831,6 @@ def TRAILZ : InstSpecial<0b011, (outs GPR:$Rd), (ins GPR:$Rs1),
// Non-Instruction Patterns // Non-Instruction Patterns
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// i32 0 and R0 can be used interchangeably.
def : Pat<(i32 0), (i32 R0)>;
// i32 -1 and R1 can be used interchangeably.
def : Pat<(i32 -1), (i32 R1)>;
// unsigned 16-bit immediate // unsigned 16-bit immediate
def : Pat<(i32 i32lo16z:$imm), (OR_I_LO (i32 R0), imm:$imm)>; def : Pat<(i32 i32lo16z:$imm), (OR_I_LO (i32 R0), imm:$imm)>;

8
test/CodeGen/Lanai/constant_multiply.ll
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@ -81,18 +81,18 @@ define i32 @fm8(i32 inreg %a) #0 {
} }
; CHECK-LABEL: fm9: ; CHECK-LABEL: fm9:
; CHECK: sh %r6, 0x3, %r{{[0-9]+}} ; CHECK: sub %r0, %r6, %r{{[0-9]+}}
; CHECK: sub %r{{[0-9]+}}, %r6, %r{{[0-9]+}} ; CHECK: sh %r6, 0x3, %r9
; CHECK: sub %r{{[0-9]+}}, %r{{[0-9]+}}, %rv ; CHECK: sub %r{{[0-9]+}}, %r9, %rv
define i32 @fm9(i32 inreg %a) #0 { define i32 @fm9(i32 inreg %a) #0 {
%1 = mul nsw i32 %a, -9 %1 = mul nsw i32 %a, -9
ret i32 %1 ret i32 %1
} }
; CHECK-LABEL: fm10: ; CHECK-LABEL: fm10:
; CHECK: sh %r6, 0x3, %r{{[0-9]+}}
; CHECK: sh %r6, 0x1, %r{{[0-9]+}} ; CHECK: sh %r6, 0x1, %r{{[0-9]+}}
; CHECK: sub %r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}} ; CHECK: sub %r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}
; CHECK: sh %r6, 0x3, %r{{[0-9]+}}
; CHECK: sub %r{{[0-9]+}}, %r{{[0-9]+}}, %rv ; CHECK: sub %r{{[0-9]+}}, %r{{[0-9]+}}, %rv
define i32 @fm10(i32 inreg %a) #0 { define i32 @fm10(i32 inreg %a) #0 {
%1 = mul nsw i32 %a, -10 %1 = mul nsw i32 %a, -10