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[PowerPC][Peephole] Check if extsw's second operand is a virtual register

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Summary:
When combining `extsw` and `sldi` in `PPCMIPeephole`, we have to check
if `extsw`'s second operand is a virtual register, otherwise we might
get miscompile.

Differential Revision: https://reviews.llvm.org/D65315

llvm-svn: 367645
This commit is contained in:
Kai Luo 2019-08-02 03:14:17 +00:00
parent 626ed23fe6
commit bb3575b0df
2 changed files with 9 additions and 2 deletions
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6
lib/Target/PowerPC/PPCMIPeephole.cpp
View File

@ -1426,6 +1426,12 @@ bool PPCMIPeephole::combineSEXTAndSHL(MachineInstr &MI,
if (!MRI->hasOneNonDBGUse(SrcReg))
return false;
assert(SrcMI->getNumOperands() == 2 && "EXTSW should have 2 operands");
assert(SrcMI->getOperand(1).isReg() &&
"EXTSW's second operand should be a register");
if (!Register::isVirtualRegister(SrcMI->getOperand(1).getReg()))
return false;
LLVM_DEBUG(dbgs() << "Combining pair: ");
LLVM_DEBUG(SrcMI->dump());
LLVM_DEBUG(MI.dump());

5
test/CodeGen/MIR/PowerPC/peephole-miscompile-extswsli.mir
View File

@ -20,10 +20,11 @@ body: |
; CHECK: B %bb.1
; CHECK: bb.1:
; CHECK: liveins: $x3
; CHECK: [[EXTSW:%[0-9]+]]:g8rc = EXTSW $x3
; CHECK: [[RLDICR:%[0-9]+]]:g8rc = RLDICR [[ANDIo8_]], 2, 61
; CHECK: $x3 = COPY [[RLDICR]]
; CHECK: [[EXTSWSLI:%[0-9]+]]:g8rc = EXTSWSLI $x3, 2, implicit-def $carry
; CHECK: [[ADD8_:%[0-9]+]]:g8rc = ADD8 [[COPY3]], [[EXTSWSLI]]
; CHECK: [[RLDICR1:%[0-9]+]]:g8rc = RLDICR [[EXTSW]], 2, 61
; CHECK: [[ADD8_:%[0-9]+]]:g8rc = ADD8 [[COPY3]], [[RLDICR1]]
; CHECK: $x3 = COPY [[ADD8_]]
; CHECK: BLR8 implicit $lr8, implicit $rm, implicit $x3
; CHECK: bb.2: