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[AArch64] NFC: Make some AArch64-SVE LoopVectorize tests generic.
This change moves most of `sve-inductions.ll` to non-AArch64 specific LV tests using the `-target-supports-scalable-vectors` flag, because they're not explicitly AArch64-specific. One test builds on AArch64-specific knowledge regarding masked loads/stores, and remains in sve-inductions.ll.
This commit is contained in:
Sander de Smalen
parent
2e5bfee63f
commit
bb39cd345a
@ -1,176 +1,6 @@
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; RUN: opt -mtriple aarch64-linux-gnu -mattr=+sve -loop-vectorize -scalable-vectorization=on -force-target-instruction-cost=1 -dce -instcombine < %s -S | FileCheck %s
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; RUN: opt -loop-vectorize -scalable-vectorization=on -force-target-instruction-cost=1 -dce -instcombine < %s -S | FileCheck %s
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; Test that we can add on the induction variable
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target triple = "aarch64-linux-gnu"
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; for (long long i = 0; i < n; i++) {
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; a[i] = b[i] + i;
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; }
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; with an unroll factor (interleave count) of 2.
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define void @add_ind64_unrolled(i64* noalias nocapture %a, i64* noalias nocapture readonly %b, i64 %n) {
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; CHECK-LABEL: @add_ind64_unrolled(
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; CHECK-NEXT: entry:
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; CHECK: vector.body:
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; CHECK-NEXT: %[[INDEX:.*]] = phi i64 [ 0, %vector.ph ], [ %{{.*}}, %vector.body ]
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; CHECK-NEXT: %[[STEPVEC:.*]] = call <vscale x 2 x i64> @llvm.experimental.stepvector.nxv2i64()
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; CHECK-NEXT: %[[TMP1:.*]] = insertelement <vscale x 2 x i64> poison, i64 %[[INDEX]], i32 0
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; CHECK-NEXT: %[[IDXSPLT:.*]] = shufflevector <vscale x 2 x i64> %[[TMP1]], <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
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; CHECK-NEXT: %[[VECIND1:.*]] = add <vscale x 2 x i64> %[[IDXSPLT]], %[[STEPVEC]]
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; CHECK-NEXT: %[[VSCALE:.*]] = call i64 @llvm.vscale.i64()
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; CHECK-NEXT: %[[EC:.*]] = shl i64 %[[VSCALE]], 1
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; CHECK-NEXT: %[[TMP2:.*]] = insertelement <vscale x 2 x i64> poison, i64 %[[EC]], i32 0
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; CHECK-NEXT: %[[ECSPLT:.*]] = shufflevector <vscale x 2 x i64> %[[TMP2]], <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
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; CHECK-NEXT: %[[TMP3:.*]] = add <vscale x 2 x i64> %[[ECSPLT]], %[[STEPVEC]]
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; CHECK-NEXT: %[[VECIND2:.*]] = add <vscale x 2 x i64> %[[IDXSPLT]], %[[TMP3]]
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; CHECK: %[[LOAD1:.*]] = load <vscale x 2 x i64>
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; CHECK: %[[LOAD2:.*]] = load <vscale x 2 x i64>
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; CHECK: %[[STOREVAL1:.*]] = add nsw <vscale x 2 x i64> %[[LOAD1]], %[[VECIND1]]
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; CHECK: %[[STOREVAL2:.*]] = add nsw <vscale x 2 x i64> %[[LOAD2]], %[[VECIND2]]
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; CHECK: store <vscale x 2 x i64> %[[STOREVAL1]]
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; CHECK: store <vscale x 2 x i64> %[[STOREVAL2]]
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entry:
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br label %for.body
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for.body: ; preds = %entry, %for.body
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%i.08 = phi i64 [ %inc, %for.body ], [ 0, %entry ]
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%arrayidx = getelementptr inbounds i64, i64* %b, i64 %i.08
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%0 = load i64, i64* %arrayidx, align 8
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%add = add nsw i64 %0, %i.08
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%arrayidx1 = getelementptr inbounds i64, i64* %a, i64 %i.08
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store i64 %add, i64* %arrayidx1, align 8
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%inc = add nuw nsw i64 %i.08, 1
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%exitcond.not = icmp eq i64 %inc, %n
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br i1 %exitcond.not, label %exit, label %for.body, !llvm.loop !0
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exit: ; preds = %for.body
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ret void
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}
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; Same as above, except we test with a vectorisation factor of (1, scalable)
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define void @add_ind64_unrolled_nxv1i64(i64* noalias nocapture %a, i64* noalias nocapture readonly %b, i64 %n) {
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; CHECK-LABEL: @add_ind64_unrolled_nxv1i64(
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; CHECK-NEXT: entry:
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; CHECK: vector.body:
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; CHECK-NEXT: %[[INDEX:.*]] = phi i64 [ 0, %vector.ph ], [ %{{.*}}, %vector.body ]
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; CHECK-NEXT: %[[STEPVEC:.*]] = call <vscale x 1 x i64> @llvm.experimental.stepvector.nxv1i64()
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; CHECK-NEXT: %[[TMP1:.*]] = insertelement <vscale x 1 x i64> poison, i64 %[[INDEX]], i32 0
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; CHECK-NEXT: %[[IDXSPLT:.*]] = shufflevector <vscale x 1 x i64> %[[TMP1]], <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
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; CHECK-NEXT: %[[VECIND1:.*]] = add <vscale x 1 x i64> %[[IDXSPLT]], %[[STEPVEC]]
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; CHECK-NEXT: %[[EC:.*]] = call i64 @llvm.vscale.i64()
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; CHECK-NEXT: %[[TMP2:.*]] = insertelement <vscale x 1 x i64> poison, i64 %[[EC]], i32 0
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; CHECK-NEXT: %[[ECSPLT:.*]] = shufflevector <vscale x 1 x i64> %[[TMP2]], <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
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; CHECK-NEXT: %[[TMP3:.*]] = add <vscale x 1 x i64> %[[ECSPLT]], %[[STEPVEC]]
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; CHECK-NEXT: %[[VECIND2:.*]] = add <vscale x 1 x i64> %[[IDXSPLT]], %[[TMP3]]
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; CHECK: %[[LOAD1:.*]] = load <vscale x 1 x i64>
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; CHECK: %[[LOAD2:.*]] = load <vscale x 1 x i64>
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; CHECK: %[[STOREVAL1:.*]] = add nsw <vscale x 1 x i64> %[[LOAD1]], %[[VECIND1]]
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; CHECK: %[[STOREVAL2:.*]] = add nsw <vscale x 1 x i64> %[[LOAD2]], %[[VECIND2]]
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; CHECK: store <vscale x 1 x i64> %[[STOREVAL1]]
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; CHECK: store <vscale x 1 x i64> %[[STOREVAL2]]
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entry:
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br label %for.body
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for.body: ; preds = %entry, %for.body
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%i.08 = phi i64 [ %inc, %for.body ], [ 0, %entry ]
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%arrayidx = getelementptr inbounds i64, i64* %b, i64 %i.08
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%0 = load i64, i64* %arrayidx, align 8
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%add = add nsw i64 %0, %i.08
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%arrayidx1 = getelementptr inbounds i64, i64* %a, i64 %i.08
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store i64 %add, i64* %arrayidx1, align 8
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%inc = add nuw nsw i64 %i.08, 1
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%exitcond.not = icmp eq i64 %inc, %n
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br i1 %exitcond.not, label %exit, label %for.body, !llvm.loop !9
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exit: ; preds = %for.body
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ret void
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}
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; Test that we can vectorize a separate induction variable (not used for the branch)
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; int r = 0;
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; for (long long i = 0; i < n; i++) {
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; a[i] = r;
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; r += 2;
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; }
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; with an unroll factor (interleave count) of 1.
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define void @add_unique_ind32(i32* noalias nocapture %a, i64 %n) {
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; CHECK-LABEL: @add_unique_ind32(
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; CHECK: vector.ph:
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; CHECK: %[[STEPVEC:.*]] = call <vscale x 4 x i32> @llvm.experimental.stepvector.nxv4i32()
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; CHECK-NEXT: %[[INDINIT:.*]] = shl <vscale x 4 x i32> %[[STEPVEC]], shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> undef, i32 1, i32 0), <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer)
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; CHECK-NEXT: %[[VSCALE:.*]] = call i32 @llvm.vscale.i32()
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; CHECK-NEXT: %[[INC:.*]] = shl i32 %[[VSCALE]], 3
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; CHECK-NEXT: %[[TMP:.*]] = insertelement <vscale x 4 x i32> poison, i32 %[[INC]], i32 0
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; CHECK-NEXT: %[[VECINC:.*]] = shufflevector <vscale x 4 x i32> %[[TMP]], <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
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; CHECK: vector.body:
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; CHECK: %[[VECIND:.*]] = phi <vscale x 4 x i32> [ %[[INDINIT]], %vector.ph ], [ %[[VECINDNXT:.*]], %vector.body ]
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; CHECK: store <vscale x 4 x i32> %[[VECIND]]
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; CHECK: %[[VECINDNXT]] = add <vscale x 4 x i32> %[[VECIND]], %[[VECINC]]
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entry:
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br label %for.body
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for.body: ; preds = %entry, %for.body
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%i.08 = phi i64 [ %inc, %for.body ], [ 0, %entry ]
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%r.07 = phi i32 [ %add, %for.body ], [ 0, %entry ]
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%arrayidx = getelementptr inbounds i32, i32* %a, i64 %i.08
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store i32 %r.07, i32* %arrayidx, align 4
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%add = add nuw nsw i32 %r.07, 2
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%inc = add nuw nsw i64 %i.08, 1
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%exitcond.not = icmp eq i64 %inc, %n
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br i1 %exitcond.not, label %exit, label %for.body, !llvm.loop !6
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exit: ; preds = %for.body
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ret void
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}
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; Test that we can vectorize a separate FP induction variable (not used for the branch)
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; float r = 0;
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; for (long long i = 0; i < n; i++) {
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; a[i] = r;
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; r += 2;
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; }
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; with an unroll factor (interleave count) of 1.
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define void @add_unique_indf32(float* noalias nocapture %a, i64 %n) {
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; CHECK-LABEL: @add_unique_indf32(
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; CHECK: vector.ph:
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; CHECK: %[[STEPVEC:.*]] = call <vscale x 4 x i32> @llvm.experimental.stepvector.nxv4i32()
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; CHECK-NEXT: %[[TMP1:.*]] = uitofp <vscale x 4 x i32> %[[STEPVEC]] to <vscale x 4 x float>
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; CHECK-NEXT: %[[TMP2:.*]] = fmul <vscale x 4 x float> %[[TMP1]], shufflevector (<vscale x 4 x float> insertelement (<vscale x 4 x float> poison, float 2.000000e+00, i32 0), <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer)
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; CHECK-NEXT: %[[INDINIT:.*]] = fadd <vscale x 4 x float> %[[TMP2]], shufflevector (<vscale x 4 x float> insertelement (<vscale x 4 x float> poison, float 0.000000e+00, i32 0), <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer)
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; CHECK-NEXT: %[[VSCALE:.*]] = call i32 @llvm.vscale.i32()
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; CHECK-NEXT: %[[TMP3:.*]] = shl i32 %8, 2
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; CHECK-NEXT: %[[TMP4:.*]] = sitofp i32 %[[TMP3]] to float
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; CHECK-NEXT: %[[INC:.*]] = fmul float %[[TMP4]], 2.000000e+00
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; CHECK-NEXT: %[[TMP5:.*]] = insertelement <vscale x 4 x float> poison, float %[[INC]], i32 0
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; CHECK-NEXT: %[[VECINC:.*]] = shufflevector <vscale x 4 x float> %[[TMP5]], <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
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; CHECK: vector.body:
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; CHECK: %[[VECIND:.*]] = phi <vscale x 4 x float> [ %[[INDINIT]], %vector.ph ], [ %[[VECINDNXT:.*]], %vector.body ]
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; CHECK: store <vscale x 4 x float> %[[VECIND]]
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; CHECK: %[[VECINDNXT]] = fadd <vscale x 4 x float> %[[VECIND]], %[[VECINC]]
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entry:
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br label %for.body
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for.body: ; preds = %entry, %for.body
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%i.08 = phi i64 [ %inc, %for.body ], [ 0, %entry ]
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%r.07 = phi float [ %add, %for.body ], [ 0.000000e+00, %entry ]
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%arrayidx = getelementptr inbounds float, float* %a, i64 %i.08
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store float %r.07, float* %arrayidx, align 4
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%add = fadd float %r.07, 2.000000e+00
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%inc = add nuw nsw i64 %i.08, 1
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%exitcond.not = icmp eq i64 %inc, %n
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br i1 %exitcond.not, label %exit, label %for.body, !llvm.loop !6
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exit: ; preds = %for.body
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ret void
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}
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; Test a case where the vectorised induction variable is used to
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; Test a case where the vectorised induction variable is used to
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; generate a mask:
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; generate a mask:
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@ -179,7 +9,7 @@ exit: ; preds = %for.body
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; a[i] = b[i];
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; a[i] = b[i];
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; }
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; }
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define void @cond_ind64(i32* noalias nocapture %a, i32* noalias nocapture readonly %b, i64 %n) {
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define void @cond_ind64(i32* noalias nocapture %a, i32* noalias nocapture readonly %b, i64 %n) #0 {
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; CHECK-LABEL: @cond_ind64(
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; CHECK-LABEL: @cond_ind64(
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; CHECK: vector.body:
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; CHECK: vector.body:
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; CHECK-NEXT: %[[INDEX:.*]] = phi i64 [ 0, %vector.ph ], [ %{{.*}}, %vector.body ]
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; CHECK-NEXT: %[[INDEX:.*]] = phi i64 [ 0, %vector.ph ], [ %{{.*}}, %vector.body ]
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@ -209,20 +39,17 @@ if.then: ; preds = %for.body
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for.inc: ; preds = %for.body, %if.then
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for.inc: ; preds = %for.body, %if.then
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%inc = add nuw nsw i64 %i.08, 1
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%inc = add nuw nsw i64 %i.08, 1
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%exitcond.not = icmp eq i64 %inc, %n
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%exitcond.not = icmp eq i64 %inc, %n
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br i1 %exitcond.not, label %exit, label %for.body, !llvm.loop !6
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br i1 %exitcond.not, label %exit, label %for.body, !llvm.loop !0
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exit: ; preds = %for.inc
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exit: ; preds = %for.inc
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ret void
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ret void
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}
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}
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attributes #0 = { "target-features"="+sve" }
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!0 = distinct !{!0, !1, !2, !3, !4, !5}
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!0 = distinct !{!0, !1, !2, !3, !4, !5}
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!1 = !{!"llvm.loop.mustprogress"}
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!1 = !{!"llvm.loop.mustprogress"}
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!2 = !{!"llvm.loop.vectorize.width", i32 2}
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!2 = !{!"llvm.loop.vectorize.scalable.enable", i1 true}
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!3 = !{!"llvm.loop.vectorize.scalable.enable", i1 true}
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!3 = !{!"llvm.loop.vectorize.enable", i1 true}
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!4 = !{!"llvm.loop.interleave.count", i32 2}
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!4 = !{!"llvm.loop.vectorize.width", i32 4}
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!5 = !{!"llvm.loop.vectorize.enable", i1 true}
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!5 = !{!"llvm.loop.interleave.count", i32 1}
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!6 = distinct !{!6, !1, !7, !3, !8, !5}
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!7 = !{!"llvm.loop.vectorize.width", i32 4}
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!8 = !{!"llvm.loop.interleave.count", i32 1}
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!9 = distinct !{!9, !1, !10, !3, !4, !5}
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!10 = !{!"llvm.loop.vectorize.width", i32 1}
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185
test/Transforms/LoopVectorize/scalable-inductions.ll
Normal file
185
test/Transforms/LoopVectorize/scalable-inductions.ll
Normal file
@ -0,0 +1,185 @@
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; RUN: opt -loop-vectorize -scalable-vectorization=on -force-target-instruction-cost=1 -force-target-supports-scalable-vectors -dce -instcombine < %s -S | FileCheck %s
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; Test that we can add on the induction variable
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; for (long long i = 0; i < n; i++) {
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; a[i] = b[i] + i;
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; }
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; with an unroll factor (interleave count) of 2.
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define void @add_ind64_unrolled(i64* noalias nocapture %a, i64* noalias nocapture readonly %b, i64 %n) {
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; CHECK-LABEL: @add_ind64_unrolled(
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; CHECK-NEXT: entry:
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; CHECK: vector.body:
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; CHECK-NEXT: %[[INDEX:.*]] = phi i64 [ 0, %vector.ph ], [ %{{.*}}, %vector.body ]
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; CHECK-NEXT: %[[STEPVEC:.*]] = call <vscale x 2 x i64> @llvm.experimental.stepvector.nxv2i64()
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; CHECK-NEXT: %[[TMP1:.*]] = insertelement <vscale x 2 x i64> poison, i64 %[[INDEX]], i32 0
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; CHECK-NEXT: %[[IDXSPLT:.*]] = shufflevector <vscale x 2 x i64> %[[TMP1]], <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
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; CHECK-NEXT: %[[VECIND1:.*]] = add <vscale x 2 x i64> %[[IDXSPLT]], %[[STEPVEC]]
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; CHECK-NEXT: %[[VSCALE:.*]] = call i64 @llvm.vscale.i64()
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; CHECK-NEXT: %[[EC:.*]] = shl i64 %[[VSCALE]], 1
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; CHECK-NEXT: %[[TMP2:.*]] = insertelement <vscale x 2 x i64> poison, i64 %[[EC]], i32 0
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; CHECK-NEXT: %[[ECSPLT:.*]] = shufflevector <vscale x 2 x i64> %[[TMP2]], <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
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; CHECK-NEXT: %[[TMP3:.*]] = add <vscale x 2 x i64> %[[ECSPLT]], %[[STEPVEC]]
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; CHECK-NEXT: %[[VECIND2:.*]] = add <vscale x 2 x i64> %[[IDXSPLT]], %[[TMP3]]
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; CHECK: %[[LOAD1:.*]] = load <vscale x 2 x i64>
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||||||
|
; CHECK: %[[LOAD2:.*]] = load <vscale x 2 x i64>
|
||||||
|
; CHECK: %[[STOREVAL1:.*]] = add nsw <vscale x 2 x i64> %[[LOAD1]], %[[VECIND1]]
|
||||||
|
; CHECK: %[[STOREVAL2:.*]] = add nsw <vscale x 2 x i64> %[[LOAD2]], %[[VECIND2]]
|
||||||
|
; CHECK: store <vscale x 2 x i64> %[[STOREVAL1]]
|
||||||
|
; CHECK: store <vscale x 2 x i64> %[[STOREVAL2]]
|
||||||
|
|
||||||
|
entry:
|
||||||
|
br label %for.body
|
||||||
|
|
||||||
|
for.body: ; preds = %entry, %for.body
|
||||||
|
%i.08 = phi i64 [ %inc, %for.body ], [ 0, %entry ]
|
||||||
|
%arrayidx = getelementptr inbounds i64, i64* %b, i64 %i.08
|
||||||
|
%0 = load i64, i64* %arrayidx, align 8
|
||||||
|
%add = add nsw i64 %0, %i.08
|
||||||
|
%arrayidx1 = getelementptr inbounds i64, i64* %a, i64 %i.08
|
||||||
|
store i64 %add, i64* %arrayidx1, align 8
|
||||||
|
%inc = add nuw nsw i64 %i.08, 1
|
||||||
|
%exitcond.not = icmp eq i64 %inc, %n
|
||||||
|
br i1 %exitcond.not, label %exit, label %for.body, !llvm.loop !0
|
||||||
|
|
||||||
|
exit: ; preds = %for.body
|
||||||
|
ret void
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
; Same as above, except we test with a vectorisation factor of (1, scalable)
|
||||||
|
|
||||||
|
define void @add_ind64_unrolled_nxv1i64(i64* noalias nocapture %a, i64* noalias nocapture readonly %b, i64 %n) {
|
||||||
|
; CHECK-LABEL: @add_ind64_unrolled_nxv1i64(
|
||||||
|
; CHECK-NEXT: entry:
|
||||||
|
; CHECK: vector.body:
|
||||||
|
; CHECK-NEXT: %[[INDEX:.*]] = phi i64 [ 0, %vector.ph ], [ %{{.*}}, %vector.body ]
|
||||||
|
; CHECK-NEXT: %[[STEPVEC:.*]] = call <vscale x 1 x i64> @llvm.experimental.stepvector.nxv1i64()
|
||||||
|
; CHECK-NEXT: %[[TMP1:.*]] = insertelement <vscale x 1 x i64> poison, i64 %[[INDEX]], i32 0
|
||||||
|
; CHECK-NEXT: %[[IDXSPLT:.*]] = shufflevector <vscale x 1 x i64> %[[TMP1]], <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
|
||||||
|
; CHECK-NEXT: %[[VECIND1:.*]] = add <vscale x 1 x i64> %[[IDXSPLT]], %[[STEPVEC]]
|
||||||
|
; CHECK-NEXT: %[[EC:.*]] = call i64 @llvm.vscale.i64()
|
||||||
|
; CHECK-NEXT: %[[TMP2:.*]] = insertelement <vscale x 1 x i64> poison, i64 %[[EC]], i32 0
|
||||||
|
; CHECK-NEXT: %[[ECSPLT:.*]] = shufflevector <vscale x 1 x i64> %[[TMP2]], <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
|
||||||
|
; CHECK-NEXT: %[[TMP3:.*]] = add <vscale x 1 x i64> %[[ECSPLT]], %[[STEPVEC]]
|
||||||
|
; CHECK-NEXT: %[[VECIND2:.*]] = add <vscale x 1 x i64> %[[IDXSPLT]], %[[TMP3]]
|
||||||
|
; CHECK: %[[LOAD1:.*]] = load <vscale x 1 x i64>
|
||||||
|
; CHECK: %[[LOAD2:.*]] = load <vscale x 1 x i64>
|
||||||
|
; CHECK: %[[STOREVAL1:.*]] = add nsw <vscale x 1 x i64> %[[LOAD1]], %[[VECIND1]]
|
||||||
|
; CHECK: %[[STOREVAL2:.*]] = add nsw <vscale x 1 x i64> %[[LOAD2]], %[[VECIND2]]
|
||||||
|
; CHECK: store <vscale x 1 x i64> %[[STOREVAL1]]
|
||||||
|
; CHECK: store <vscale x 1 x i64> %[[STOREVAL2]]
|
||||||
|
|
||||||
|
entry:
|
||||||
|
br label %for.body
|
||||||
|
|
||||||
|
for.body: ; preds = %entry, %for.body
|
||||||
|
%i.08 = phi i64 [ %inc, %for.body ], [ 0, %entry ]
|
||||||
|
%arrayidx = getelementptr inbounds i64, i64* %b, i64 %i.08
|
||||||
|
%0 = load i64, i64* %arrayidx, align 8
|
||||||
|
%add = add nsw i64 %0, %i.08
|
||||||
|
%arrayidx1 = getelementptr inbounds i64, i64* %a, i64 %i.08
|
||||||
|
store i64 %add, i64* %arrayidx1, align 8
|
||||||
|
%inc = add nuw nsw i64 %i.08, 1
|
||||||
|
%exitcond.not = icmp eq i64 %inc, %n
|
||||||
|
br i1 %exitcond.not, label %exit, label %for.body, !llvm.loop !9
|
||||||
|
|
||||||
|
exit: ; preds = %for.body
|
||||||
|
ret void
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
; Test that we can vectorize a separate induction variable (not used for the branch)
|
||||||
|
; int r = 0;
|
||||||
|
; for (long long i = 0; i < n; i++) {
|
||||||
|
; a[i] = r;
|
||||||
|
; r += 2;
|
||||||
|
; }
|
||||||
|
; with an unroll factor (interleave count) of 1.
|
||||||
|
|
||||||
|
|
||||||
|
define void @add_unique_ind32(i32* noalias nocapture %a, i64 %n) {
|
||||||
|
; CHECK-LABEL: @add_unique_ind32(
|
||||||
|
; CHECK: vector.ph:
|
||||||
|
; CHECK: %[[STEPVEC:.*]] = call <vscale x 4 x i32> @llvm.experimental.stepvector.nxv4i32()
|
||||||
|
; CHECK-NEXT: %[[INDINIT:.*]] = shl <vscale x 4 x i32> %[[STEPVEC]], shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> undef, i32 1, i32 0), <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer)
|
||||||
|
; CHECK-NEXT: %[[VSCALE:.*]] = call i32 @llvm.vscale.i32()
|
||||||
|
; CHECK-NEXT: %[[INC:.*]] = shl i32 %[[VSCALE]], 3
|
||||||
|
; CHECK-NEXT: %[[TMP:.*]] = insertelement <vscale x 4 x i32> poison, i32 %[[INC]], i32 0
|
||||||
|
; CHECK-NEXT: %[[VECINC:.*]] = shufflevector <vscale x 4 x i32> %[[TMP]], <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
|
||||||
|
; CHECK: vector.body:
|
||||||
|
; CHECK: %[[VECIND:.*]] = phi <vscale x 4 x i32> [ %[[INDINIT]], %vector.ph ], [ %[[VECINDNXT:.*]], %vector.body ]
|
||||||
|
; CHECK: store <vscale x 4 x i32> %[[VECIND]]
|
||||||
|
; CHECK: %[[VECINDNXT]] = add <vscale x 4 x i32> %[[VECIND]], %[[VECINC]]
|
||||||
|
entry:
|
||||||
|
br label %for.body
|
||||||
|
|
||||||
|
for.body: ; preds = %entry, %for.body
|
||||||
|
%i.08 = phi i64 [ %inc, %for.body ], [ 0, %entry ]
|
||||||
|
%r.07 = phi i32 [ %add, %for.body ], [ 0, %entry ]
|
||||||
|
%arrayidx = getelementptr inbounds i32, i32* %a, i64 %i.08
|
||||||
|
store i32 %r.07, i32* %arrayidx, align 4
|
||||||
|
%add = add nuw nsw i32 %r.07, 2
|
||||||
|
%inc = add nuw nsw i64 %i.08, 1
|
||||||
|
%exitcond.not = icmp eq i64 %inc, %n
|
||||||
|
br i1 %exitcond.not, label %exit, label %for.body, !llvm.loop !6
|
||||||
|
|
||||||
|
exit: ; preds = %for.body
|
||||||
|
ret void
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
; Test that we can vectorize a separate FP induction variable (not used for the branch)
|
||||||
|
; float r = 0;
|
||||||
|
; for (long long i = 0; i < n; i++) {
|
||||||
|
; a[i] = r;
|
||||||
|
; r += 2;
|
||||||
|
; }
|
||||||
|
; with an unroll factor (interleave count) of 1.
|
||||||
|
|
||||||
|
define void @add_unique_indf32(float* noalias nocapture %a, i64 %n) {
|
||||||
|
; CHECK-LABEL: @add_unique_indf32(
|
||||||
|
; CHECK: vector.ph:
|
||||||
|
; CHECK: %[[STEPVEC:.*]] = call <vscale x 4 x i32> @llvm.experimental.stepvector.nxv4i32()
|
||||||
|
; CHECK-NEXT: %[[TMP1:.*]] = uitofp <vscale x 4 x i32> %[[STEPVEC]] to <vscale x 4 x float>
|
||||||
|
; CHECK-NEXT: %[[TMP2:.*]] = fmul <vscale x 4 x float> %[[TMP1]], shufflevector (<vscale x 4 x float> insertelement (<vscale x 4 x float> poison, float 2.000000e+00, i32 0), <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer)
|
||||||
|
; CHECK-NEXT: %[[INDINIT:.*]] = fadd <vscale x 4 x float> %[[TMP2]], shufflevector (<vscale x 4 x float> insertelement (<vscale x 4 x float> poison, float 0.000000e+00, i32 0), <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer)
|
||||||
|
; CHECK-NEXT: %[[VSCALE:.*]] = call i32 @llvm.vscale.i32()
|
||||||
|
; CHECK-NEXT: %[[TMP3:.*]] = shl i32 %8, 2
|
||||||
|
; CHECK-NEXT: %[[TMP4:.*]] = sitofp i32 %[[TMP3]] to float
|
||||||
|
; CHECK-NEXT: %[[INC:.*]] = fmul float %[[TMP4]], 2.000000e+00
|
||||||
|
; CHECK-NEXT: %[[TMP5:.*]] = insertelement <vscale x 4 x float> poison, float %[[INC]], i32 0
|
||||||
|
; CHECK-NEXT: %[[VECINC:.*]] = shufflevector <vscale x 4 x float> %[[TMP5]], <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
|
||||||
|
; CHECK: vector.body:
|
||||||
|
; CHECK: %[[VECIND:.*]] = phi <vscale x 4 x float> [ %[[INDINIT]], %vector.ph ], [ %[[VECINDNXT:.*]], %vector.body ]
|
||||||
|
; CHECK: store <vscale x 4 x float> %[[VECIND]]
|
||||||
|
; CHECK: %[[VECINDNXT]] = fadd <vscale x 4 x float> %[[VECIND]], %[[VECINC]]
|
||||||
|
|
||||||
|
entry:
|
||||||
|
br label %for.body
|
||||||
|
|
||||||
|
for.body: ; preds = %entry, %for.body
|
||||||
|
%i.08 = phi i64 [ %inc, %for.body ], [ 0, %entry ]
|
||||||
|
%r.07 = phi float [ %add, %for.body ], [ 0.000000e+00, %entry ]
|
||||||
|
%arrayidx = getelementptr inbounds float, float* %a, i64 %i.08
|
||||||
|
store float %r.07, float* %arrayidx, align 4
|
||||||
|
%add = fadd float %r.07, 2.000000e+00
|
||||||
|
%inc = add nuw nsw i64 %i.08, 1
|
||||||
|
%exitcond.not = icmp eq i64 %inc, %n
|
||||||
|
br i1 %exitcond.not, label %exit, label %for.body, !llvm.loop !6
|
||||||
|
|
||||||
|
exit: ; preds = %for.body
|
||||||
|
ret void
|
||||||
|
}
|
||||||
|
|
||||||
|
!0 = distinct !{!0, !1, !2, !3, !4, !5}
|
||||||
|
!1 = !{!"llvm.loop.mustprogress"}
|
||||||
|
!2 = !{!"llvm.loop.vectorize.width", i32 2}
|
||||||
|
!3 = !{!"llvm.loop.vectorize.scalable.enable", i1 true}
|
||||||
|
!4 = !{!"llvm.loop.interleave.count", i32 2}
|
||||||
|
!5 = !{!"llvm.loop.vectorize.enable", i1 true}
|
||||||
|
!6 = distinct !{!6, !1, !7, !3, !8, !5}
|
||||||
|
!7 = !{!"llvm.loop.vectorize.width", i32 4}
|
||||||
|
!8 = !{!"llvm.loop.interleave.count", i32 1}
|
||||||
|
!9 = distinct !{!9, !1, !10, !3, !4, !5}
|
||||||
|
!10 = !{!"llvm.loop.vectorize.width", i32 1}
|
||||||
Loading…
Reference in New Issue
Block a user