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X86: Generate mir checks in sqrt test

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Matt Arsenault 2020-02-12 17:50:52 -05:00 committed by Matt Arsenault
parent 81cfd93bf4
commit bb3d51d74e
1 changed files with 43 additions and 35 deletions
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78
test/CodeGen/X86/sqrt-fastmath-mir.ll
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@ -1,48 +1,56 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx2,fma -stop-after=finalize-isel 2>&1 | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx2,fma -stop-after=finalize-isel 2>&1 | FileCheck %s
declare float @llvm.sqrt.f32(float) #0 declare float @llvm.sqrt.f32(float) #0
define float @foo(float %f) #0 { define float @foo(float %f) #0 {
; CHECK: {{name: *foo}} ; CHECK-LABEL: name: foo
; CHECK: body: ; CHECK: bb.0 (%ir-block.0):
; CHECK: %0:fr32 = COPY $xmm0 ; CHECK: liveins: $xmm0
; CHECK: %1:fr32 = VRSQRTSSr killed %2, %0 ; CHECK: [[COPY:%[0-9]+]]:fr32 = COPY $xmm0
; CHECK: %3:fr32 = nofpexcept VMULSSrr %0, %1 ; CHECK: [[DEF:%[0-9]+]]:fr32 = IMPLICIT_DEF
; CHECK: %4:fr32 = VMOVSSrm ; CHECK: [[VRSQRTSSr:%[0-9]+]]:fr32 = VRSQRTSSr killed [[DEF]], [[COPY]]
; CHECK: %5:fr32 = nofpexcept VFMADD213SSr %1, killed %3, %4 ; CHECK: %3:fr32 = nofpexcept VMULSSrr [[COPY]], [[VRSQRTSSr]], implicit $mxcsr
; CHECK: %6:fr32 = VMOVSSrm ; CHECK: [[VMOVSSrm_alt:%[0-9]+]]:fr32 = VMOVSSrm_alt $rip, 1, $noreg, %const.0, $noreg :: (load 4 from constant-pool)
; CHECK: %7:fr32 = nofpexcept VMULSSrr %1, %6 ; CHECK: %5:fr32 = nofpexcept VFMADD213SSr [[VRSQRTSSr]], killed %3, [[VMOVSSrm_alt]], implicit $mxcsr
; CHECK: %8:fr32 = nofpexcept VMULSSrr killed %7, killed %5 ; CHECK: [[VMOVSSrm_alt1:%[0-9]+]]:fr32 = VMOVSSrm_alt $rip, 1, $noreg, %const.1, $noreg :: (load 4 from constant-pool)
; CHECK: %9:fr32 = nofpexcept VMULSSrr %0, %8 ; CHECK: %7:fr32 = nofpexcept VMULSSrr [[VRSQRTSSr]], [[VMOVSSrm_alt1]], implicit $mxcsr
; CHECK: %10:fr32 = nofpexcept VFMADD213SSr %8, %9, %4 ; CHECK: %8:fr32 = nofpexcept VMULSSrr killed %7, killed %5, implicit $mxcsr
; CHECK: %11:fr32 = nofpexcept VMULSSrr %9, %6 ; CHECK: %9:fr32 = nofpexcept VMULSSrr [[COPY]], %8, implicit $mxcsr
; CHECK: %12:fr32 = nofpexcept VMULSSrr killed %11, killed %10 ; CHECK: %10:fr32 = nofpexcept VFMADD213SSr %8, %9, [[VMOVSSrm_alt]], implicit $mxcsr
; CHECK: %14:fr32 = FsFLD0SS ; CHECK: %11:fr32 = nofpexcept VMULSSrr %9, [[VMOVSSrm_alt1]], implicit $mxcsr
; CHECK: %15:fr32 = nofpexcept VCMPSSrr %0, killed %14, 0 ; CHECK: %12:fr32 = nofpexcept VMULSSrr killed %11, killed %10, implicit $mxcsr
; CHECK: %17:vr128 = VPANDNrr killed %16, killed %13 ; CHECK: [[COPY1:%[0-9]+]]:vr128 = COPY %12
; CHECK: $xmm0 = COPY %18 ; CHECK: [[FsFLD0SS:%[0-9]+]]:fr32 = FsFLD0SS
; CHECK: RET 0, $xmm0 ; CHECK: %15:fr32 = nofpexcept VCMPSSrr [[COPY]], killed [[FsFLD0SS]], 0, implicit $mxcsr
; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY %15
; CHECK: [[VPANDNrr:%[0-9]+]]:vr128 = VPANDNrr killed [[COPY2]], killed [[COPY1]]
; CHECK: [[COPY3:%[0-9]+]]:fr32 = COPY [[VPANDNrr]]
; CHECK: $xmm0 = COPY [[COPY3]]
; CHECK: RET 0, $xmm0
%call = tail call float @llvm.sqrt.f32(float %f) #1 %call = tail call float @llvm.sqrt.f32(float %f) #1
ret float %call ret float %call
} }
define float @rfoo(float %f) #0 { define float @rfoo(float %f) #0 {
; CHECK: {{name: *rfoo}} ; CHECK-LABEL: name: rfoo
; CHECK: body: | ; CHECK: bb.0 (%ir-block.0):
; CHECK: %0:fr32 = COPY $xmm0 ; CHECK: liveins: $xmm0
; CHECK: %1:fr32 = VRSQRTSSr killed %2, %0 ; CHECK: [[COPY:%[0-9]+]]:fr32 = COPY $xmm0
; CHECK: %3:fr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept VMULSSrr %0, %1 ; CHECK: [[DEF:%[0-9]+]]:fr32 = IMPLICIT_DEF
; CHECK: %4:fr32 = VMOVSSrm ; CHECK: [[VRSQRTSSr:%[0-9]+]]:fr32 = VRSQRTSSr killed [[DEF]], [[COPY]]
; CHECK: %5:fr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept VFMADD213SSr %1, killed %3, %4 ; CHECK: %3:fr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept VMULSSrr [[COPY]], [[VRSQRTSSr]], implicit $mxcsr
; CHECK: %6:fr32 = VMOVSSrm ; CHECK: [[VMOVSSrm_alt:%[0-9]+]]:fr32 = VMOVSSrm_alt $rip, 1, $noreg, %const.0, $noreg :: (load 4 from constant-pool)
; CHECK: %7:fr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept VMULSSrr %1, %6 ; CHECK: %5:fr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept VFMADD213SSr [[VRSQRTSSr]], killed %3, [[VMOVSSrm_alt]], implicit $mxcsr
; CHECK: %8:fr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept VMULSSrr killed %7, killed %5 ; CHECK: [[VMOVSSrm_alt1:%[0-9]+]]:fr32 = VMOVSSrm_alt $rip, 1, $noreg, %const.1, $noreg :: (load 4 from constant-pool)
; CHECK: %9:fr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept VMULSSrr %0, %8 ; CHECK: %7:fr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept VMULSSrr [[VRSQRTSSr]], [[VMOVSSrm_alt1]], implicit $mxcsr
; CHECK: %10:fr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept VFMADD213SSr %8, killed %9, %4 ; CHECK: %8:fr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept VMULSSrr killed %7, killed %5, implicit $mxcsr
; CHECK: %11:fr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept VMULSSrr %8, %6 ; CHECK: %9:fr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept VMULSSrr [[COPY]], %8, implicit $mxcsr
; CHECK: %12:fr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept VMULSSrr killed %11, killed %10 ; CHECK: %10:fr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept VFMADD213SSr %8, killed %9, [[VMOVSSrm_alt]], implicit $mxcsr
; CHECK: $xmm0 = COPY %12 ; CHECK: %11:fr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept VMULSSrr %8, [[VMOVSSrm_alt1]], implicit $mxcsr
; CHECK: RET 0, $xmm0 ; CHECK: %12:fr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept VMULSSrr killed %11, killed %10, implicit $mxcsr
; CHECK: $xmm0 = COPY %12
; CHECK: RET 0, $xmm0
%sqrt = tail call float @llvm.sqrt.f32(float %f) %sqrt = tail call float @llvm.sqrt.f32(float %f)
%div = fdiv fast float 1.0, %sqrt %div = fdiv fast float 1.0, %sqrt
ret float %div ret float %div