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[mips] Split long lines in the code. NFC
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@ -4013,8 +4013,8 @@ bool MipsAsmParser::expandCondBranches(MCInst &Inst, SMLoc IDLoc,
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// D(S)DivMacro.
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bool MipsAsmParser::expandDivRem(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
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const MCSubtargetInfo *STI, const bool IsMips64,
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const bool Signed) {
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const MCSubtargetInfo *STI,
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const bool IsMips64, const bool Signed) {
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MipsTargetStreamer &TOut = getTargetStreamer();
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warnIfNoMacro(IDLoc);
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@ -446,16 +446,16 @@ static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
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const void *Decoder);
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template <typename InsnType>
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static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn,
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uint64_t Address, const void *Decoder);
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template <typename InsnType>
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static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address,
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const void *Decoder);
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template <typename InsnType>
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static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn,
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uint64_t Address, const void *Decoder);
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template <typename InsnType>
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static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address,
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@ -630,8 +630,8 @@ static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
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}
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template <typename InsnType>
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static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address,
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const void *Decoder) {
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static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn,
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uint64_t Address, const void *Decoder) {
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InsnType Rs = fieldFromInstruction(insn, 16, 5);
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InsnType Imm = fieldFromInstruction(insn, 0, 16);
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MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
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@ -1091,8 +1091,10 @@ static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address,
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InsnType Rs = fieldFromInstruction(Insn, 21, 5);
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InsnType Rt = fieldFromInstruction(Insn, 16, 5);
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MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt)));
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MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs)));
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MI.addOperand(
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MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt)));
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MI.addOperand(
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MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs)));
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MI.addOperand(MCOperand::createImm(Pos));
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MI.addOperand(MCOperand::createImm(Size));
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@ -1132,8 +1134,10 @@ static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address,
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InsnType Rt = fieldFromInstruction(Insn, 16, 5);
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MI.setOpcode(Mips::DINS);
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MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt)));
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MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs)));
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MI.addOperand(
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MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt)));
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MI.addOperand(
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MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs)));
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MI.addOperand(MCOperand::createImm(Pos));
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MI.addOperand(MCOperand::createImm(Size));
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@ -1256,8 +1260,8 @@ DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
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LLVM_DEBUG(
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dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n");
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// Calling the auto-generated decoder function.
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Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn, Address,
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this, STI);
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Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn,
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Address, this, STI);
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if (Result != MCDisassembler::Fail) {
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Size = 4;
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return Result;
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@ -585,6 +585,8 @@ MCAsmBackend *llvm::createMipsAsmBackend(const Target &T,
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const MCSubtargetInfo &STI,
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const MCRegisterInfo &MRI,
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const MCTargetOptions &Options) {
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MipsABIInfo ABI = MipsABIInfo::computeTargetABI(STI.getTargetTriple(), STI.getCPU(), Options);
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return new MipsAsmBackend(T, MRI, STI.getTargetTriple(), STI.getCPU(), ABI.IsN32());
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MipsABIInfo ABI = MipsABIInfo::computeTargetABI(STI.getTargetTriple(),
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STI.getCPU(), Options);
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return new MipsAsmBackend(T, MRI, STI.getTargetTriple(), STI.getCPU(),
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ABI.IsN32());
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}
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@ -600,7 +600,8 @@ getExprOpValue(const MCExpr *Expr, SmallVectorImpl<MCFixup> &Fixups,
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}
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if (Kind == MCExpr::Binary) {
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unsigned Res = getExprOpValue(cast<MCBinaryExpr>(Expr)->getLHS(), Fixups, STI);
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unsigned Res =
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getExprOpValue(cast<MCBinaryExpr>(Expr)->getLHS(), Fixups, STI);
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Res += getExprOpValue(cast<MCBinaryExpr>(Expr)->getRHS(), Fixups, STI);
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return Res;
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}
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@ -729,7 +730,8 @@ getExprOpValue(const MCExpr *Expr, SmallVectorImpl<MCFixup> &Fixups,
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default: llvm_unreachable("Unknown fixup kind!");
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break;
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case MCSymbolRefExpr::VK_None:
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FixupKind = Mips::fixup_Mips_32; // FIXME: This is ok for O32/N32 but not N64.
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// FIXME: This is ok for O32/N32 but not N64.
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FixupKind = Mips::fixup_Mips_32;
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break;
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} // switch
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@ -768,7 +770,8 @@ unsigned MipsMCCodeEmitter::getMemEncoding(const MCInst &MI, unsigned OpNo,
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const MCSubtargetInfo &STI) const {
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// Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
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assert(MI.getOperand(OpNo).isReg());
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unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups, STI) << 16;
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unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI)
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<< 16;
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unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
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// Apply the scale factor if there is one.
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@ -857,7 +860,8 @@ getMemEncodingMMImm9(const MCInst &MI, unsigned OpNo,
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assert(MI.getOperand(OpNo).isReg());
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unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups,
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STI) << 16;
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unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo + 1), Fixups, STI);
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unsigned OffBits =
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getMachineOpValue(MI, MI.getOperand(OpNo + 1), Fixups, STI);
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return (OffBits & 0x1FF) | RegBits;
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}
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@ -892,7 +896,8 @@ getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo,
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// Base register is encoded in bits 20-16, offset is encoded in bits 11-0.
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assert(MI.getOperand(OpNo).isReg());
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unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) << 16;
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unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI)
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<< 16;
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unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
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return (OffBits & 0x0FFF) | RegBits;
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@ -211,7 +211,8 @@ MipsMCExpr::evaluateAsRelocatableImpl(MCValue &Res,
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// The value of getKind() that is given to MCValue is only intended to aid
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// debugging when inspecting MCValue objects. It shouldn't be relied upon
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// for decision making.
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Res = MCValue::get(Res.getSymA(), Res.getSymB(), Res.getConstant(), getKind());
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Res =
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MCValue::get(Res.getSymA(), Res.getSymB(), Res.getConstant(), getKind());
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return true;
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}
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@ -234,7 +234,8 @@ class POOL32A_FM_MMR6<bits<10> funct> : MipsR6Inst {
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let Inst{9-0} = funct;
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}
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class POOL32A_PAUSE_FM_MMR6<string instr_asm, bits<5> op> : MMR6Arch<instr_asm> {
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class POOL32A_PAUSE_FM_MMR6<string instr_asm, bits<5> op>
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: MMR6Arch<instr_asm> {
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bits<32> Inst;
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let Inst{31-26} = 0;
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@ -512,7 +513,8 @@ class BARRIER_MMR6_ENC<string instr_asm, bits<5> op> : MMR6Arch<instr_asm> {
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class POOL32A_EIDI_MMR6_ENC<string instr_asm, bits<10> funct>
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: MMR6Arch<instr_asm> {
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bits<32> Inst;
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bits<5> rt; // Actually rs but we're sharing code with the standard encodings which call it rt
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bits<5> rt; // Actually rs but we're sharing code with the standard encodings
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// which call it rt
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let Inst{31-26} = 0x00;
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let Inst{25-21} = 0x00;
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@ -521,7 +523,8 @@ class POOL32A_EIDI_MMR6_ENC<string instr_asm, bits<10> funct>
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let Inst{5-0} = 0x3c;
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}
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class SHIFT_MMR6_ENC<string instr_asm, bits<10> funct, bit rotate> : MMR6Arch<instr_asm> {
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class SHIFT_MMR6_ENC<string instr_asm, bits<10> funct, bit rotate>
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: MMR6Arch<instr_asm> {
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bits<5> rd;
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bits<5> rt;
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bits<5> shamt;
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@ -809,8 +812,8 @@ class POOL32F_RECIP_ROUND_FM_MMR6<string instr_asm, bits<1> fmt, bits<8> funct>
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let Inst{5-0} = 0b111011;
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}
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class POOL32F_RINT_FM_MMR6<string instr_asm, bits<2> fmt>
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: MMR6Arch<instr_asm>, MipsR6Inst {
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class POOL32F_RINT_FM_MMR6<string instr_asm, bits<2> fmt> : MMR6Arch<instr_asm>,
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MipsR6Inst {
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bits<5> fs;
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bits<5> fd;
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@ -1012,8 +1015,8 @@ class POOL32B_LDWC2_SDWC2_FM_MMR6<string instr_asm, bits<4> funct>
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}
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class POOL32C_LL_E_SC_E_FM_MMR6<string instr_asm, bits<4> majorFunc,
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bits<3> minorFunc>
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: MMR6Arch<instr_asm>, MipsR6Inst {
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bits<3> minorFunc> : MMR6Arch<instr_asm>,
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MipsR6Inst {
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bits<5> rt;
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bits<21> addr;
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bits<5> base = addr{20-16};
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@ -341,7 +341,8 @@ class BNEC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bnec", brtarget_lsl2_mm,
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GPR32Opnd>;
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class ADD_MMR6_DESC : ArithLogicR<"add", GPR32Opnd, 1, II_ADD>;
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class ADDIU_MMR6_DESC : ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16, add>;
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class ADDIU_MMR6_DESC
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: ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16, add>;
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class ADDU_MMR6_DESC : ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU>;
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class MUL_MMR6_DESC : ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>;
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class MUH_MMR6_DESC : ArithLogicR<"muh", GPR32Opnd, 1, II_MUH, mulhs>;
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@ -1045,8 +1046,8 @@ class TRUNC_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.d", FGR32Opnd,
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FGR64Opnd, II_TRUNC>;
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class SQRT_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.s", FGR32Opnd, FGR32Opnd,
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II_SQRT_S, fsqrt>;
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class SQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.d", AFGR64Opnd, AFGR64Opnd,
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II_SQRT_D, fsqrt>;
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class SQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.d", AFGR64Opnd,
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AFGR64Opnd, II_SQRT_D, fsqrt>;
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class ROUND_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.l.s", FGR64Opnd,
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FGR32Opnd, II_ROUND>;
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class ROUND_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.l.d", FGR64Opnd,
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@ -1101,14 +1102,16 @@ class SLL16_MMR6_DESC : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>,
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MMR6Arch<"sll16">;
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class SRL16_MMR6_DESC : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>,
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MMR6Arch<"srl16">;
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class BREAK16_MMR6_DESC : BrkSdbbp16MM<"break16", II_BREAK>, MMR6Arch<"break16">;
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class BREAK16_MMR6_DESC : BrkSdbbp16MM<"break16", II_BREAK>,
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MMR6Arch<"break16">;
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class LI16_MMR6_DESC : LoadImmMM16<"li16", li16_imm, GPRMM16Opnd>,
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MMR6Arch<"li16">, IsAsCheapAsAMove;
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class MOVE16_MMR6_DESC : MoveMM16<"move16", GPR32Opnd>, MMR6Arch<"move16">;
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class MOVEP_MMR6_DESC : MovePMM16<"movep", GPRMM16OpndMovePPairFirst,
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GPRMM16OpndMovePPairSecond, GPRMM16OpndMoveP>,
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MMR6Arch<"movep">;
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class SDBBP16_MMR6_DESC : BrkSdbbp16MM<"sdbbp16", II_SDBBP>, MMR6Arch<"sdbbp16">;
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class SDBBP16_MMR6_DESC : BrkSdbbp16MM<"sdbbp16", II_SDBBP>,
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MMR6Arch<"sdbbp16">;
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class SUBU16_MMR6_DESC : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
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MMR6Arch<"subu16"> {
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int AddedComplexity = 1;
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@ -1439,7 +1442,8 @@ def SYNCI_MMR6 : StdMMR6Rel, SYNCI_MMR6_DESC, SYNCI_MMR6_ENC, ISA_MICROMIPS32R6;
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def RDPGPR_MMR6 : R6MMR6Rel, RDPGPR_MMR6_DESC, RDPGPR_MMR6_ENC,
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ISA_MICROMIPS32R6;
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def SDBBP_MMR6 : R6MMR6Rel, SDBBP_MMR6_DESC, SDBBP_MMR6_ENC, ISA_MICROMIPS32R6;
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def SIGRIE_MMR6 : R6MMR6Rel, SIGRIE_MMR6_DESC, SIGRIE_MMR6_ENC, ISA_MICROMIPS32R6;
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def SIGRIE_MMR6 : R6MMR6Rel, SIGRIE_MMR6_DESC, SIGRIE_MMR6_ENC,
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ISA_MICROMIPS32R6;
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def XOR_MMR6 : StdMMR6Rel, XOR_MMR6_DESC, XOR_MMR6_ENC, ISA_MICROMIPS32R6;
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def XORI_MMR6 : StdMMR6Rel, XORI_MMR6_DESC, XORI_MMR6_ENC, ISA_MICROMIPS32R6;
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let DecoderMethod = "DecodeMemMMImm16" in {
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@ -1557,7 +1561,8 @@ def INS_MMR6 : StdMMR6Rel, INS_MMR6_ENC, INS_MMR6_DESC, ISA_MICROMIPS32R6;
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def JALRC_MMR6 : R6MMR6Rel, JALRC_MMR6_ENC, JALRC_MMR6_DESC, ISA_MICROMIPS32R6;
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def RINT_S_MMR6 : StdMMR6Rel, RINT_S_MMR6_ENC, RINT_S_MMR6_DESC,
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ISA_MICROMIPS32R6;
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def RINT_D_MMR6 : StdMMR6Rel, RINT_D_MMR6_ENC, RINT_D_MMR6_DESC, ISA_MICROMIPS32R6;
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def RINT_D_MMR6 : StdMMR6Rel, RINT_D_MMR6_ENC, RINT_D_MMR6_DESC,
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ISA_MICROMIPS32R6;
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def ROUND_L_S_MMR6 : StdMMR6Rel, ROUND_L_S_MMR6_ENC, ROUND_L_S_MMR6_DESC,
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ISA_MICROMIPS32R6;
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def ROUND_L_D_MMR6 : StdMMR6Rel, ROUND_L_D_MMR6_ENC, ROUND_L_D_MMR6_DESC,
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@ -1751,7 +1756,8 @@ defm S_MMR6 : Cmp_Pats<f32, NOR_MMR6, ZERO>, ISA_MICROMIPS32R6;
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defm D_MMR6 : Cmp_Pats<f64, NOR_MMR6, ZERO>, ISA_MICROMIPS32R6;
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def : MipsPat<(f32 fpimm0), (MTC1_MMR6 ZERO)>, ISA_MICROMIPS32R6;
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def : MipsPat<(f32 fpimm0neg), (FNEG_S_MMR6 (MTC1_MMR6 ZERO))>, ISA_MICROMIPS32R6;
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def : MipsPat<(f32 fpimm0neg), (FNEG_S_MMR6(MTC1_MMR6 ZERO))>,
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ISA_MICROMIPS32R6;
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def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src),
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(TRUNC_W_D_MMR6 FGR64Opnd:$src)>, ISA_MICROMIPS32R6;
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def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src),
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@ -230,7 +230,8 @@ let DecoderNamespace = "MicroMips" in {
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def FSQRT_S_MM : MMRel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, II_SQRT_S,
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fsqrt>, ROUND_W_FM_MM<0, 0x28>, ISA_MICROMIPS;
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def MTHC1_D32_MM : MMRel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>,
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def MTHC1_D32_MM : MMRel,
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MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>,
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MFC1_FM_MM<0xe0>, ISA_MICROMIPS, FGR_32;
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def MFHC1_D32_MM : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>,
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MFC1_FM_MM<0xc0>, ISA_MICROMIPS, FGR_32;
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@ -506,7 +506,8 @@ class LoadWordIndexedScaledMM<string opstr, RegisterOperand RO,
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class PrefetchIndexed<string opstr> :
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InstSE<(outs), (ins PtrRC:$base, PtrRC:$index, uimm5:$hint),
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!strconcat(opstr, "\t$hint, ${index}(${base})"), [], II_PREF, FrmOther>;
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!strconcat(opstr, "\t$hint, ${index}(${base})"),
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[], II_PREF, FrmOther>;
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class AddImmUPC<string opstr, RegisterOperand RO> :
|
||||
InstSE<(outs RO:$rs), (ins simm23_lsl2:$imm),
|
||||
|
@ -192,17 +192,18 @@ def FeatureGINV : SubtargetFeature<"ginv", "HasGINV", "true",
|
||||
def FeatureMicroMips : SubtargetFeature<"micromips", "InMicroMipsMode", "true",
|
||||
"microMips mode">;
|
||||
|
||||
def FeatureCnMips : SubtargetFeature<"cnmips", "HasCnMips",
|
||||
"true", "Octeon cnMIPS Support",
|
||||
[FeatureMips64r2]>;
|
||||
def FeatureCnMips : SubtargetFeature<"cnmips", "HasCnMips",
|
||||
"true", "Octeon cnMIPS Support",
|
||||
[FeatureMips64r2]>;
|
||||
|
||||
def FeatureUseTCCInDIV : SubtargetFeature<
|
||||
"use-tcc-in-div",
|
||||
"UseTCCInDIV", "false",
|
||||
"Force the assembler to use trapping">;
|
||||
|
||||
def FeatureMadd4 : SubtargetFeature<"nomadd4", "DisableMadd4", "true",
|
||||
"Disable 4-operand madd.fmt and related instructions">;
|
||||
def FeatureMadd4
|
||||
: SubtargetFeature<"nomadd4", "DisableMadd4", "true",
|
||||
"Disable 4-operand madd.fmt and related instructions">;
|
||||
|
||||
def FeatureMT : SubtargetFeature<"mt", "HasMT", "true", "Mips MT ASE">;
|
||||
|
||||
|
@ -418,8 +418,9 @@ unsigned Mips16InstrInfo::loadImmediate(unsigned FrameReg, int64_t Imm,
|
||||
else
|
||||
Available.reset(SpReg);
|
||||
copyPhysReg(MBB, II, DL, SpReg, Mips::SP, false);
|
||||
BuildMI(MBB, II, DL, get(Mips:: AdduRxRyRz16), Reg).addReg(SpReg, RegState::Kill)
|
||||
.addReg(Reg);
|
||||
BuildMI(MBB, II, DL, get(Mips::AdduRxRyRz16), Reg)
|
||||
.addReg(SpReg, RegState::Kill)
|
||||
.addReg(Reg);
|
||||
}
|
||||
else
|
||||
BuildMI(MBB, II, DL, get(Mips:: AdduRxRyRz16), Reg).addReg(FrameReg)
|
||||
|
@ -996,13 +996,15 @@ def : MipsInstAlias<"evp", (EVP ZERO), 0>, ISA_MIPS32R6;
|
||||
let AdditionalPredicates = [NotInMicroMips] in {
|
||||
def : MipsInstAlias<"sdbbp", (SDBBP_R6 0)>, ISA_MIPS32R6;
|
||||
def : MipsInstAlias<"sigrie", (SIGRIE 0)>, ISA_MIPS32R6;
|
||||
def : MipsInstAlias<"jr $rs", (JALR ZERO, GPR32Opnd:$rs), 1>, ISA_MIPS32R6, GPR_32;
|
||||
def : MipsInstAlias<"jr $rs", (JALR ZERO, GPR32Opnd:$rs), 1>,
|
||||
ISA_MIPS32R6, GPR_32;
|
||||
}
|
||||
|
||||
def : MipsInstAlias<"jrc $rs", (JIC GPR32Opnd:$rs, 0), 1>, ISA_MIPS32R6, GPR_32;
|
||||
|
||||
let AdditionalPredicates = [NotInMicroMips] in {
|
||||
def : MipsInstAlias<"jalrc $rs", (JIALC GPR32Opnd:$rs, 0), 1>, ISA_MIPS32R6, GPR_32;
|
||||
def : MipsInstAlias<"jalrc $rs", (JIALC GPR32Opnd:$rs, 0), 1>,
|
||||
ISA_MIPS32R6, GPR_32;
|
||||
}
|
||||
|
||||
def : MipsInstAlias<"div $rs, $rt", (DIV GPR32Opnd:$rs, GPR32Opnd:$rs,
|
||||
|
@ -395,11 +395,11 @@ let AdditionalPredicates = [NotInMicroMips] in {
|
||||
}
|
||||
|
||||
let isCodeGenOnly = 1, AdditionalPredicates = [NotInMicroMips] in {
|
||||
def DEXT64_32 : InstSE<(outs GPR64Opnd:$rt),
|
||||
(ins GPR32Opnd:$rs, uimm5_report_uimm6:$pos,
|
||||
uimm5_plus1:$size),
|
||||
"dext $rt, $rs, $pos, $size", [], II_EXT, FrmR, "dext">,
|
||||
EXT_FM<3>, ISA_MIPS64R2;
|
||||
def DEXT64_32
|
||||
: InstSE<(outs GPR64Opnd:$rt),
|
||||
(ins GPR32Opnd:$rs, uimm5_report_uimm6:$pos, uimm5_plus1:$size),
|
||||
"dext $rt, $rs, $pos, $size", [], II_EXT, FrmR, "dext">,
|
||||
EXT_FM<3>, ISA_MIPS64R2;
|
||||
}
|
||||
|
||||
let isCodeGenOnly = 1, rs = 0, shamt = 0 in {
|
||||
@ -1027,8 +1027,10 @@ let AdditionalPredicates = [NotInMicroMips] in {
|
||||
(DMTGC0 COP0Opnd:$rd, GPR64Opnd:$rt, 0), 0>,
|
||||
ISA_MIPS64R5, ASE_VIRT;
|
||||
}
|
||||
def : MipsInstAlias<"dmfc2 $rt, $rd", (DMFC2 GPR64Opnd:$rt, COP2Opnd:$rd, 0), 0>;
|
||||
def : MipsInstAlias<"dmtc2 $rt, $rd", (DMTC2 COP2Opnd:$rd, GPR64Opnd:$rt, 0), 0>;
|
||||
def : MipsInstAlias<"dmfc2 $rt, $rd",
|
||||
(DMFC2 GPR64Opnd:$rt, COP2Opnd:$rd, 0), 0>;
|
||||
def : MipsInstAlias<"dmtc2 $rt, $rd",
|
||||
(DMTC2 COP2Opnd:$rd, GPR64Opnd:$rt, 0), 0>;
|
||||
|
||||
def : MipsInstAlias<"synciobdma", (SYNC 0x2), 0>, ASE_MIPS64_CNMIPS;
|
||||
def : MipsInstAlias<"syncs", (SYNC 0x6), 0>, ASE_MIPS64_CNMIPS;
|
||||
|
@ -48,7 +48,8 @@ class CRC32CD_ENC : SPECIAL3_2R_SZ_CRC<3,1>;
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
class AHI_ATI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, InstrItinClass itin> {
|
||||
class AHI_ATI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
|
||||
InstrItinClass itin> {
|
||||
dag OutOperandList = (outs GPROpnd:$rs);
|
||||
dag InOperandList = (ins GPROpnd:$rt, uimm16_altrelaxed:$imm);
|
||||
string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $imm");
|
||||
|
@ -623,8 +623,10 @@ bool MipsAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
|
||||
assert(OpNum + 1 < MI->getNumOperands() && "Insufficient operands");
|
||||
const MachineOperand &BaseMO = MI->getOperand(OpNum);
|
||||
const MachineOperand &OffsetMO = MI->getOperand(OpNum + 1);
|
||||
assert(BaseMO.isReg() && "Unexpected base pointer for inline asm memory operand.");
|
||||
assert(OffsetMO.isImm() && "Unexpected offset for inline asm memory operand.");
|
||||
assert(BaseMO.isReg() &&
|
||||
"Unexpected base pointer for inline asm memory operand.");
|
||||
assert(OffsetMO.isImm() &&
|
||||
"Unexpected offset for inline asm memory operand.");
|
||||
int Offset = OffsetMO.getImm();
|
||||
|
||||
// Currently we are expecting either no ExtraCode or 'D','M','L'.
|
||||
|
@ -655,7 +655,8 @@ bool MipsCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
|
||||
MipsCCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs,
|
||||
F.getContext());
|
||||
|
||||
CCInfo.AnalyzeCallResult(Ins, TLI.CCAssignFnForReturn(), Info.OrigRet.Ty, Call);
|
||||
CCInfo.AnalyzeCallResult(Ins, TLI.CCAssignFnForReturn(), Info.OrigRet.Ty,
|
||||
Call);
|
||||
setLocInfo(ArgLocs, Ins);
|
||||
|
||||
CallReturnHandler Handler(MIRBuilder, MF.getRegInfo(), MIB);
|
||||
|
@ -139,7 +139,8 @@ def CC_MipsN : CallingConv<[
|
||||
CCIfType<[i8, i16, i32], CCIfOrigArgWasNotFloat<CCPromoteToType<i64>>>,
|
||||
|
||||
// The only i32's we have left are soft-float arguments.
|
||||
CCIfSubtarget<"useSoftFloat()", CCIfType<[i32], CCDelegateTo<CC_MipsN_SoftFloat>>>,
|
||||
CCIfSubtarget<"useSoftFloat()", CCIfType<[i32],
|
||||
CCDelegateTo<CC_MipsN_SoftFloat>>>,
|
||||
|
||||
// Integer arguments are passed in integer registers.
|
||||
CCIfType<[i64], CCAssignToRegWithShadow<[A0_64, A1_64, A2_64, A3_64,
|
||||
|
@ -116,8 +116,8 @@ let AdditionalPredicates = [NotInMicroMips] in {
|
||||
ADD_FM<0, 0xa>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
|
||||
}
|
||||
|
||||
def MOVN_I_I : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd, II_MOVN>,
|
||||
ADD_FM<0, 0xb>, INSN_MIPS4_32_NOT_32R6_64R6;
|
||||
def MOVN_I_I : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd, II_MOVN>,
|
||||
ADD_FM<0, 0xb>, INSN_MIPS4_32_NOT_32R6_64R6;
|
||||
|
||||
let isCodeGenOnly = 1 in {
|
||||
def MOVN_I_I64 : CMov_I_I_FT<"movn", GPR32Opnd, GPR64Opnd, II_MOVN>,
|
||||
@ -226,8 +226,8 @@ let AdditionalPredicates = [NotInMicroMips] in {
|
||||
GPR_64;
|
||||
defm : MovnPats<GPR64, GPR32, MOVN_I64_I, XOR64>, INSN_MIPS4_32_NOT_32R6_64R6,
|
||||
GPR_64;
|
||||
defm : MovnPats<GPR64, GPR64, MOVN_I64_I64, XOR64>, INSN_MIPS4_32_NOT_32R6_64R6,
|
||||
GPR_64;
|
||||
defm : MovnPats<GPR64, GPR64, MOVN_I64_I64, XOR64>,
|
||||
INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
|
||||
|
||||
defm : MovzPats0<GPR32, FGR32, MOVZ_I_S, SLT, SLTu, SLTi, SLTiu>,
|
||||
INSN_MIPS4_32_NOT_32R6_64R6;
|
||||
@ -236,8 +236,8 @@ let AdditionalPredicates = [NotInMicroMips] in {
|
||||
|
||||
defm : MovzPats0<GPR64, FGR32, MOVZ_I_S, SLT64, SLTu64, SLTi64, SLTiu64>,
|
||||
INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
|
||||
defm : MovzPats1<GPR64, FGR32, MOVZ_I64_S, XOR64>, INSN_MIPS4_32_NOT_32R6_64R6,
|
||||
GPR_64;
|
||||
defm : MovzPats1<GPR64, FGR32, MOVZ_I64_S, XOR64>,
|
||||
INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
|
||||
defm : MovnPats<GPR64, FGR32, MOVN_I64_S, XOR64>, INSN_MIPS4_32_NOT_32R6_64R6,
|
||||
GPR_64;
|
||||
|
||||
@ -258,8 +258,8 @@ let AdditionalPredicates = [NotInMicroMips] in {
|
||||
INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;
|
||||
defm : MovnPats<GPR32, FGR64, MOVN_I_D64, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,
|
||||
FGR_64;
|
||||
defm : MovnPats<GPR64, FGR64, MOVN_I64_D64, XOR64>, INSN_MIPS4_32_NOT_32R6_64R6,
|
||||
FGR_64;
|
||||
defm : MovnPats<GPR64, FGR64, MOVN_I64_D64, XOR64>,
|
||||
INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;
|
||||
}
|
||||
// For targets that don't have conditional-move instructions
|
||||
// we have to match SELECT nodes with pseudo instructions.
|
||||
|
@ -127,9 +127,9 @@ static unsigned int longformBranchOpcode(unsigned int Opcode) {
|
||||
llvm_unreachable("Unknown branch type");
|
||||
}
|
||||
|
||||
// FIXME: need to go through this whole constant islands port and check the math
|
||||
// for branch ranges and clean this up and make some functions to calculate things
|
||||
// that are done many times identically.
|
||||
// FIXME: need to go through this whole constant islands port and check
|
||||
// the math for branch ranges and clean this up and make some functions
|
||||
// to calculate things that are done many times identically.
|
||||
// Need to refactor some of the code to call this routine.
|
||||
static unsigned int branchMaxOffsets(unsigned int Opcode) {
|
||||
unsigned Bits, Scale;
|
||||
@ -1519,8 +1519,8 @@ MipsConstantIslands::fixupUnconditionalBr(ImmBranch &Br) {
|
||||
// we know that RA is saved because we always save it right now.
|
||||
// this requirement will be relaxed later but we also have an alternate
|
||||
// way to implement this that I will implement that does not need jal.
|
||||
// We should have a way to back out this alignment restriction if we "can" later.
|
||||
// but it is not harmful.
|
||||
// We should have a way to back out this alignment restriction
|
||||
// if we "can" later. but it is not harmful.
|
||||
//
|
||||
DestBB->setAlignment(Align(4));
|
||||
Br.MaxDisp = ((1<<24)-1) * 2;
|
||||
|
@ -376,7 +376,7 @@ class LX_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
|
||||
|
||||
class ADDUH_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
|
||||
InstrItinClass itin, RegisterOperand ROD,
|
||||
RegisterOperand ROS = ROD, RegisterOperand ROT = ROD> {
|
||||
RegisterOperand ROS = ROD, RegisterOperand ROT = ROD> {
|
||||
dag OutOperandList = (outs ROD:$rd);
|
||||
dag InOperandList = (ins ROS:$rs, ROT:$rt);
|
||||
string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
|
||||
@ -386,7 +386,8 @@ class ADDUH_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
|
||||
}
|
||||
|
||||
class APPEND_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
|
||||
Operand ImmOp, SDPatternOperator Imm, InstrItinClass itin> {
|
||||
Operand ImmOp, SDPatternOperator Imm,
|
||||
InstrItinClass itin> {
|
||||
dag OutOperandList = (outs GPR32Opnd:$rt);
|
||||
dag InOperandList = (ins GPR32Opnd:$rs, ImmOp:$sa, GPR32Opnd:$src);
|
||||
string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa");
|
||||
@ -511,7 +512,8 @@ class MFHI_DESC_BASE<string instr_asm, RegisterOperand RO, SDNode OpNode,
|
||||
bit isMoveReg = 1;
|
||||
}
|
||||
|
||||
class MTHI_DESC_BASE<string instr_asm, RegisterOperand RO, InstrItinClass itin> {
|
||||
class MTHI_DESC_BASE<string instr_asm, RegisterOperand RO,
|
||||
InstrItinClass itin> {
|
||||
dag OutOperandList = (outs RO:$ac);
|
||||
dag InOperandList = (ins GPR32Opnd:$rs);
|
||||
string AsmString = !strconcat(instr_asm, "\t$rs, $ac");
|
||||
@ -1304,7 +1306,8 @@ let DecoderNamespace = "MipsDSP", Arch = "dsp",
|
||||
// Pseudo CMP and PICK instructions.
|
||||
class PseudoCMP<Instruction RealInst> :
|
||||
PseudoDSP<(outs DSPCC:$cmp), (ins DSPROpnd:$rs, DSPROpnd:$rt), []>,
|
||||
PseudoInstExpansion<(RealInst DSPROpnd:$rs, DSPROpnd:$rt)>, NeverHasSideEffects;
|
||||
PseudoInstExpansion<(RealInst DSPROpnd:$rs, DSPROpnd:$rt)>,
|
||||
NeverHasSideEffects;
|
||||
|
||||
class PseudoPICK<Instruction RealInst> :
|
||||
PseudoDSP<(outs DSPROpnd:$rd), (ins DSPCC:$cmp, DSPROpnd:$rs, DSPROpnd:$rt), []>,
|
||||
|
@ -91,15 +91,14 @@ enum CompactBranchPolicy {
|
||||
};
|
||||
|
||||
static cl::opt<CompactBranchPolicy> MipsCompactBranchPolicy(
|
||||
"mips-compact-branches",cl::Optional,
|
||||
cl::init(CB_Optimal),
|
||||
cl::desc("MIPS Specific: Compact branch policy."),
|
||||
cl::values(
|
||||
clEnumValN(CB_Never, "never", "Do not use compact branches if possible."),
|
||||
clEnumValN(CB_Optimal, "optimal", "Use compact branches where appropiate (default)."),
|
||||
clEnumValN(CB_Always, "always", "Always use compact branches if possible.")
|
||||
)
|
||||
);
|
||||
"mips-compact-branches", cl::Optional, cl::init(CB_Optimal),
|
||||
cl::desc("MIPS Specific: Compact branch policy."),
|
||||
cl::values(clEnumValN(CB_Never, "never",
|
||||
"Do not use compact branches if possible."),
|
||||
clEnumValN(CB_Optimal, "optimal",
|
||||
"Use compact branches where appropiate (default)."),
|
||||
clEnumValN(CB_Always, "always",
|
||||
"Always use compact branches if possible.")));
|
||||
|
||||
namespace {
|
||||
|
||||
@ -927,4 +926,6 @@ bool MipsDelaySlotFiller::terminateSearch(const MachineInstr &Candidate) const {
|
||||
|
||||
/// createMipsDelaySlotFillerPass - Returns a pass that fills in delay
|
||||
/// slots in Mips MachineFunctions
|
||||
FunctionPass *llvm::createMipsDelaySlotFillerPass() { return new MipsDelaySlotFiller(); }
|
||||
FunctionPass *llvm::createMipsDelaySlotFillerPass() {
|
||||
return new MipsDelaySlotFiller();
|
||||
}
|
||||
|
@ -604,8 +604,14 @@ bool MipsExpandPseudo::expandAtomicBinOp(MachineBasicBlock &BB,
|
||||
BuildMI(loopMBB, DL, TII->get(OR), Scratch).addReg(Incr).addReg(ZERO);
|
||||
}
|
||||
|
||||
BuildMI(loopMBB, DL, TII->get(SC), Scratch).addReg(Scratch).addReg(Ptr).addImm(0);
|
||||
BuildMI(loopMBB, DL, TII->get(BEQ)).addReg(Scratch).addReg(ZERO).addMBB(loopMBB);
|
||||
BuildMI(loopMBB, DL, TII->get(SC), Scratch)
|
||||
.addReg(Scratch)
|
||||
.addReg(Ptr)
|
||||
.addImm(0);
|
||||
BuildMI(loopMBB, DL, TII->get(BEQ))
|
||||
.addReg(Scratch)
|
||||
.addReg(ZERO)
|
||||
.addMBB(loopMBB);
|
||||
|
||||
NMBBI = BB.end();
|
||||
I->eraseFromParent();
|
||||
|
@ -528,8 +528,9 @@ MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM,
|
||||
isMicroMips = Subtarget.inMicroMipsMode();
|
||||
}
|
||||
|
||||
const MipsTargetLowering *MipsTargetLowering::create(const MipsTargetMachine &TM,
|
||||
const MipsSubtarget &STI) {
|
||||
const MipsTargetLowering *
|
||||
MipsTargetLowering::create(const MipsTargetMachine &TM,
|
||||
const MipsSubtarget &STI) {
|
||||
if (STI.inMips16Mode())
|
||||
return createMips16TargetLowering(TM, STI);
|
||||
|
||||
@ -2804,7 +2805,8 @@ static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
|
||||
// allocate a register directly.
|
||||
Reg = State.AllocateReg(IntRegs);
|
||||
}
|
||||
} else if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
|
||||
} else if (ValVT == MVT::i32 ||
|
||||
(ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
|
||||
Reg = State.AllocateReg(IntRegs);
|
||||
// If this is the first part of an i64 arg,
|
||||
// the allocated register must be either A0 or A2.
|
||||
@ -3625,8 +3627,8 @@ MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
|
||||
return CCInfo.CheckReturn(Outs, RetCC_Mips);
|
||||
}
|
||||
|
||||
bool
|
||||
MipsTargetLowering::shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
|
||||
bool MipsTargetLowering::shouldSignExtendTypeInLibCall(EVT Type,
|
||||
bool IsSigned) const {
|
||||
if ((ABI.IsN32() || ABI.IsN64()) && Type == MVT::i32)
|
||||
return true;
|
||||
|
||||
@ -4113,7 +4115,8 @@ void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
|
||||
|
||||
bool MipsTargetLowering::isLegalAddressingMode(const DataLayout &DL,
|
||||
const AddrMode &AM, Type *Ty,
|
||||
unsigned AS, Instruction *I) const {
|
||||
unsigned AS,
|
||||
Instruction *I) const {
|
||||
// No global is ever allowed as a base.
|
||||
if (AM.BaseGV)
|
||||
return false;
|
||||
@ -4489,8 +4492,9 @@ MachineBasicBlock *MipsTargetLowering::emitPseudoSELECT(MachineInstr &MI,
|
||||
return BB;
|
||||
}
|
||||
|
||||
MachineBasicBlock *MipsTargetLowering::emitPseudoD_SELECT(MachineInstr &MI,
|
||||
MachineBasicBlock *BB) const {
|
||||
MachineBasicBlock *
|
||||
MipsTargetLowering::emitPseudoD_SELECT(MachineInstr &MI,
|
||||
MachineBasicBlock *BB) const {
|
||||
assert(!(Subtarget.hasMips4() || Subtarget.hasMips32()) &&
|
||||
"Subtarget already supports SELECT nodes with the use of"
|
||||
"conditional-move instructions.");
|
||||
@ -4566,8 +4570,9 @@ MachineBasicBlock *MipsTargetLowering::emitPseudoD_SELECT(MachineInstr &MI,
|
||||
|
||||
// FIXME? Maybe this could be a TableGen attribute on some registers and
|
||||
// this table could be generated automatically from RegInfo.
|
||||
Register MipsTargetLowering::getRegisterByName(const char* RegName, EVT VT,
|
||||
const MachineFunction &MF) const {
|
||||
Register
|
||||
MipsTargetLowering::getRegisterByName(const char *RegName, EVT VT,
|
||||
const MachineFunction &MF) const {
|
||||
// Named registers is expected to be fairly rare. For now, just support $28
|
||||
// since the linux kernel uses it.
|
||||
if (Subtarget.isGP64bit()) {
|
||||
|
@ -129,8 +129,9 @@ class ABSS_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
|
||||
HARDFLOAT,
|
||||
NeverHasSideEffects;
|
||||
|
||||
class CVT_PS_S_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, InstrItinClass Itin, bit IsComm,
|
||||
SDPatternOperator OpNode= null_frag> :
|
||||
class CVT_PS_S_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
|
||||
InstrItinClass Itin, bit IsComm,
|
||||
SDPatternOperator OpNode = null_frag> :
|
||||
InstSE<(outs DstRC:$fd), (ins SrcRC:$fs, SrcRC:$ft),
|
||||
!strconcat(opstr, "\t$fd, $fs, $ft"),
|
||||
[(set DstRC:$fd, (OpNode SrcRC:$fs, SrcRC:$ft))], Itin, FrmFR, opstr>,
|
||||
@ -142,7 +143,8 @@ multiclass ABSS_M<string opstr, InstrItinClass Itin,
|
||||
SDPatternOperator OpNode= null_frag> {
|
||||
def _D32 : MMRel, ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>,
|
||||
FGR_32;
|
||||
def _D64 : StdMMR6Rel, ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>, FGR_64 {
|
||||
def _D64 : StdMMR6Rel, ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>,
|
||||
FGR_64 {
|
||||
string DecoderNamespace = "MipsFP64";
|
||||
}
|
||||
}
|
||||
@ -362,17 +364,21 @@ defm D64 : C_COND_M<"d", FGR64Opnd, 17, II_C_CC_D>, ISA_MIPS1_NOT_32R6_64R6,
|
||||
// Floating Point Instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
let AdditionalPredicates = [NotInMicroMips] in {
|
||||
def ROUND_W_S : MMRel, StdMMR6Rel, ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, II_ROUND>,
|
||||
ABSS_FM<0xc, 16>, ISA_MIPS2;
|
||||
defm ROUND_W : ROUND_M<"round.w.d", II_ROUND>, ABSS_FM<0xc, 17>, ISA_MIPS2;
|
||||
def TRUNC_W_S : MMRel, StdMMR6Rel, ABSS_FT<"trunc.w.s", FGR32Opnd, FGR32Opnd, II_TRUNC>,
|
||||
ABSS_FM<0xd, 16>, ISA_MIPS2;
|
||||
def CEIL_W_S : MMRel, StdMMR6Rel, ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, II_CEIL>,
|
||||
ABSS_FM<0xe, 16>, ISA_MIPS2;
|
||||
def FLOOR_W_S : MMRel, StdMMR6Rel, ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd, II_FLOOR>,
|
||||
ABSS_FM<0xf, 16>, ISA_MIPS2;
|
||||
def CVT_W_S : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>,
|
||||
ABSS_FM<0x24, 16>, ISA_MIPS1;
|
||||
def ROUND_W_S : MMRel, StdMMR6Rel,
|
||||
ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, II_ROUND>,
|
||||
ABSS_FM<0xc, 16>, ISA_MIPS2;
|
||||
defm ROUND_W : ROUND_M<"round.w.d", II_ROUND>, ABSS_FM<0xc, 17>, ISA_MIPS2;
|
||||
def TRUNC_W_S : MMRel, StdMMR6Rel,
|
||||
ABSS_FT<"trunc.w.s", FGR32Opnd, FGR32Opnd, II_TRUNC>,
|
||||
ABSS_FM<0xd, 16>, ISA_MIPS2;
|
||||
def CEIL_W_S : MMRel, StdMMR6Rel,
|
||||
ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, II_CEIL>,
|
||||
ABSS_FM<0xe, 16>, ISA_MIPS2;
|
||||
def FLOOR_W_S : MMRel, StdMMR6Rel,
|
||||
ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd, II_FLOOR>,
|
||||
ABSS_FM<0xf, 16>, ISA_MIPS2;
|
||||
def CVT_W_S : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>,
|
||||
ABSS_FM<0x24, 16>, ISA_MIPS1;
|
||||
|
||||
defm TRUNC_W : ROUND_M<"trunc.w.d", II_TRUNC>, ABSS_FM<0xd, 17>, ISA_MIPS2;
|
||||
defm CEIL_W : ROUND_M<"ceil.w.d", II_CEIL>, ABSS_FM<0xe, 17>, ISA_MIPS2;
|
||||
@ -536,7 +542,8 @@ let AdditionalPredicates = [NotInMicroMips] in {
|
||||
let DecoderNamespace = "MipsFP64";
|
||||
}
|
||||
|
||||
def MTHC1_D32 : MMRel, StdMMR6Rel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>,
|
||||
def MTHC1_D32 : MMRel, StdMMR6Rel,
|
||||
MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>,
|
||||
MFC1_FM<7>, ISA_MIPS32R2, FGR_32;
|
||||
def MTHC1_D64 : MTC1_64_FT<"mthc1", FGR64Opnd, GPR32Opnd, II_MTHC1>,
|
||||
MFC1_FM<7>, ISA_MIPS32R2, FGR_64 {
|
||||
@ -950,9 +957,12 @@ multiclass NMADD_NMSUB<Instruction Nmadd, Instruction Nmsub, RegisterOperand RC>
|
||||
}
|
||||
|
||||
let AdditionalPredicates = [NoNaNsFPMath, HasMadd4, NotInMicroMips] in {
|
||||
defm : NMADD_NMSUB<NMADD_S, NMSUB_S, FGR32Opnd>, INSN_MIPS4_32R2_NOT_32R6_64R6;
|
||||
defm : NMADD_NMSUB<NMADD_D32, NMSUB_D32, AFGR64Opnd>, FGR_32, INSN_MIPS4_32R2_NOT_32R6_64R6;
|
||||
defm : NMADD_NMSUB<NMADD_D64, NMSUB_D64, FGR64Opnd>, FGR_64, INSN_MIPS4_32R2_NOT_32R6_64R6;
|
||||
defm : NMADD_NMSUB<NMADD_S, NMSUB_S, FGR32Opnd>,
|
||||
INSN_MIPS4_32R2_NOT_32R6_64R6;
|
||||
defm : NMADD_NMSUB<NMADD_D32, NMSUB_D32, AFGR64Opnd>,
|
||||
FGR_32, INSN_MIPS4_32R2_NOT_32R6_64R6;
|
||||
defm : NMADD_NMSUB<NMADD_D64, NMSUB_D64, FGR64Opnd>,
|
||||
FGR_64, INSN_MIPS4_32R2_NOT_32R6_64R6;
|
||||
}
|
||||
|
||||
// Patterns for loads/stores with a reg+imm operand.
|
||||
|
@ -275,7 +275,8 @@ MipsInstrInfo::BranchType MipsInstrInfo::analyzeBranch(
|
||||
return BT_CondUncond;
|
||||
}
|
||||
|
||||
bool MipsInstrInfo::isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const {
|
||||
bool MipsInstrInfo::isBranchOffsetInRange(unsigned BranchOpc,
|
||||
int64_t BrOffset) const {
|
||||
switch (BranchOpc) {
|
||||
case Mips::B:
|
||||
case Mips::BAL:
|
||||
@ -433,7 +434,6 @@ bool MipsInstrInfo::isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset)
|
||||
llvm_unreachable("Unknown branch instruction!");
|
||||
}
|
||||
|
||||
|
||||
/// Return the corresponding compact (no delay slot) form of a branch.
|
||||
unsigned MipsInstrInfo::getEquivalentCompactForm(
|
||||
const MachineBasicBlock::iterator I) const {
|
||||
|
@ -2069,10 +2069,10 @@ let AdditionalPredicates = [NotInMicroMips] in {
|
||||
ISA_MIPS1;
|
||||
|
||||
/// Arithmetic Instructions (3-Operand, R-Type)
|
||||
def ADDu : MMRel, StdMMR6Rel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
|
||||
ADD_FM<0, 0x21>, ISA_MIPS1;
|
||||
def SUBu : MMRel, StdMMR6Rel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
|
||||
ADD_FM<0, 0x23>, ISA_MIPS1;
|
||||
def ADDu : MMRel, StdMMR6Rel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
|
||||
ADD_FM<0, 0x21>, ISA_MIPS1;
|
||||
def SUBu : MMRel, StdMMR6Rel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
|
||||
ADD_FM<0, 0x23>, ISA_MIPS1;
|
||||
|
||||
let Defs = [HI0, LO0] in
|
||||
def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,
|
||||
@ -2137,7 +2137,8 @@ let AdditionalPredicates = [NotInMicroMips] in {
|
||||
LW_FM<0x28>, ISA_MIPS1;
|
||||
def SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>,
|
||||
ISA_MIPS1;
|
||||
def SW : StdMMR6Rel, Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>, ISA_MIPS1;
|
||||
def SW : StdMMR6Rel, Store<"sw", GPR32Opnd, store, II_SW>,
|
||||
MMRel, LW_FM<0x2b>, ISA_MIPS1;
|
||||
}
|
||||
|
||||
/// load/store left/right
|
||||
@ -2238,7 +2239,8 @@ def J : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>,
|
||||
IsBranch, ISA_MIPS1;
|
||||
|
||||
let AdditionalPredicates = [NotInMicroMips] in {
|
||||
def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>, ISA_MIPS1_NOT_32R6_64R6;
|
||||
def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>,
|
||||
ISA_MIPS1_NOT_32R6_64R6;
|
||||
def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>,
|
||||
ISA_MIPS1;
|
||||
def BEQL : MMRel, CBranchLikely<"beql", brtarget, GPR32Opnd>,
|
||||
@ -2396,7 +2398,8 @@ let AdditionalPredicates = [NotInMicroMips] in {
|
||||
// add op with mem ComplexPattern is used and the stack address copy
|
||||
// can be matched. It's similar to Sparc LEA_ADDRi
|
||||
let AdditionalPredicates = [NotInMicroMips] in
|
||||
def LEA_ADDiu : MMRel, EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>, ISA_MIPS1;
|
||||
def LEA_ADDiu : MMRel, EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>,
|
||||
ISA_MIPS1;
|
||||
|
||||
// MADD*/MSUB*
|
||||
def MADD : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>,
|
||||
@ -2572,9 +2575,11 @@ def DROLImm : MipsAsmPseudoInst<(outs),
|
||||
(ins GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm),
|
||||
"drol\t$rs, $rt, $imm">, ISA_MIPS64;
|
||||
def : MipsInstAlias<"drol $rd, $rs",
|
||||
(DROL GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rs), 0>, ISA_MIPS64;
|
||||
(DROL GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rs), 0>,
|
||||
ISA_MIPS64;
|
||||
def : MipsInstAlias<"drol $rd, $imm",
|
||||
(DROLImm GPR32Opnd:$rd, GPR32Opnd:$rd, simm16:$imm), 0>, ISA_MIPS64;
|
||||
(DROLImm GPR32Opnd:$rd, GPR32Opnd:$rd, simm16:$imm), 0>,
|
||||
ISA_MIPS64;
|
||||
|
||||
def DROR : MipsAsmPseudoInst<(outs),
|
||||
(ins GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rd),
|
||||
@ -2583,9 +2588,11 @@ def DRORImm : MipsAsmPseudoInst<(outs),
|
||||
(ins GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm),
|
||||
"dror\t$rs, $rt, $imm">, ISA_MIPS64;
|
||||
def : MipsInstAlias<"dror $rd, $rs",
|
||||
(DROR GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rs), 0>, ISA_MIPS64;
|
||||
(DROR GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rs), 0>,
|
||||
ISA_MIPS64;
|
||||
def : MipsInstAlias<"dror $rd, $imm",
|
||||
(DRORImm GPR32Opnd:$rd, GPR32Opnd:$rd, simm16:$imm), 0>, ISA_MIPS64;
|
||||
(DRORImm GPR32Opnd:$rd, GPR32Opnd:$rd, simm16:$imm), 0>,
|
||||
ISA_MIPS64;
|
||||
|
||||
def ABSMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), (ins GPR32Opnd:$rs),
|
||||
"abs\t$rd, $rs">;
|
||||
@ -2762,7 +2769,8 @@ let AdditionalPredicates = [NotInMicroMips] in {
|
||||
|
||||
def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>, ISA_MIPS1;
|
||||
|
||||
defm : OneOrTwoOperandMacroImmediateAlias<"add", ADDi>, ISA_MIPS1_NOT_32R6_64R6;
|
||||
defm : OneOrTwoOperandMacroImmediateAlias<"add", ADDi>,
|
||||
ISA_MIPS1_NOT_32R6_64R6;
|
||||
|
||||
defm : OneOrTwoOperandMacroImmediateAlias<"addu", ADDiu>, ISA_MIPS1;
|
||||
|
||||
@ -3089,7 +3097,8 @@ multiclass MaterializeImms<ValueType VT, Register ZEROReg,
|
||||
// observed.
|
||||
|
||||
// Arbitrary immediates
|
||||
def : MipsPat<(VT LUiORiPred:$imm), (ORiOp (LUiOp (HI16 imm:$imm)), (LO16 imm:$imm))>;
|
||||
def : MipsPat<(VT LUiORiPred:$imm),
|
||||
(ORiOp (LUiOp (HI16 imm:$imm)), (LO16 imm:$imm))>;
|
||||
|
||||
// Bits 32-16 set, sign/zero extended.
|
||||
def : MipsPat<(VT LUiPred:$imm), (LUiOp (HI16 imm:$imm))>;
|
||||
|
@ -139,8 +139,9 @@ bool MipsInstructionSelector::materialize32BitImm(Register DestReg, APInt Imm,
|
||||
assert(Imm.getBitWidth() == 32 && "Unsupported immediate size.");
|
||||
// Ori zero extends immediate. Used for values with zeros in high 16 bits.
|
||||
if (Imm.getHiBits(16).isNullValue()) {
|
||||
MachineInstr *Inst = B.buildInstr(Mips::ORi, {DestReg}, {Register(Mips::ZERO)})
|
||||
.addImm(Imm.getLoBits(16).getLimitedValue());
|
||||
MachineInstr *Inst =
|
||||
B.buildInstr(Mips::ORi, {DestReg}, {Register(Mips::ZERO)})
|
||||
.addImm(Imm.getLoBits(16).getLimitedValue());
|
||||
return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI);
|
||||
}
|
||||
// Lui places immediate in high 16 bits and sets low 16 bits to zero.
|
||||
@ -151,8 +152,9 @@ bool MipsInstructionSelector::materialize32BitImm(Register DestReg, APInt Imm,
|
||||
}
|
||||
// ADDiu sign extends immediate. Used for values with 1s in high 17 bits.
|
||||
if (Imm.isSignedIntN(16)) {
|
||||
MachineInstr *Inst = B.buildInstr(Mips::ADDiu, {DestReg}, {Register(Mips::ZERO)})
|
||||
.addImm(Imm.getLoBits(16).getLimitedValue());
|
||||
MachineInstr *Inst =
|
||||
B.buildInstr(Mips::ADDiu, {DestReg}, {Register(Mips::ZERO)})
|
||||
.addImm(Imm.getLoBits(16).getLimitedValue());
|
||||
return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI);
|
||||
}
|
||||
// Values that cannot be materialized with single immediate instruction.
|
||||
|
@ -234,8 +234,8 @@ void MipsSEDAGToDAGISel::selectAddE(SDNode *Node, const SDLoc &DL) const {
|
||||
|
||||
SDValue OuFlag = CurDAG->getTargetConstant(20, DL, MVT::i32);
|
||||
|
||||
SDNode *DSPCtrlField =
|
||||
CurDAG->getMachineNode(Mips::RDDSP, DL, MVT::i32, MVT::Glue, CstOne, InFlag);
|
||||
SDNode *DSPCtrlField = CurDAG->getMachineNode(Mips::RDDSP, DL, MVT::i32,
|
||||
MVT::Glue, CstOne, InFlag);
|
||||
|
||||
SDNode *Carry = CurDAG->getMachineNode(
|
||||
Mips::EXT, DL, MVT::i32, SDValue(DSPCtrlField, 0), OuFlag, CstOne);
|
||||
@ -253,7 +253,8 @@ void MipsSEDAGToDAGISel::selectAddE(SDNode *Node, const SDLoc &DL) const {
|
||||
SDValue Zero = CurDAG->getRegister(Mips::ZERO, MVT::i32);
|
||||
|
||||
SDValue InsOps[4] = {Zero, OuFlag, CstOne, SDValue(DSPCFWithCarry, 0)};
|
||||
SDNode *DSPCtrlFinal = CurDAG->getMachineNode(Mips::INS, DL, MVT::i32, InsOps);
|
||||
SDNode *DSPCtrlFinal =
|
||||
CurDAG->getMachineNode(Mips::INS, DL, MVT::i32, InsOps);
|
||||
|
||||
SDNode *WrDSP = CurDAG->getMachineNode(Mips::WRDSP, DL, MVT::Glue,
|
||||
SDValue(DSPCtrlFinal, 0), CstOne);
|
||||
@ -1074,7 +1075,8 @@ bool MipsSEDAGToDAGISel::trySelect(SDNode *Node) {
|
||||
Hi ? SDValue(Res, 0) : ZeroVal, LoVal);
|
||||
|
||||
assert((Hi || Lo) && "Zero case reached 32 bit case splat synthesis!");
|
||||
Res = CurDAG->getMachineNode(Mips::FILL_W, DL, MVT::v4i32, SDValue(Res, 0));
|
||||
Res =
|
||||
CurDAG->getMachineNode(Mips::FILL_W, DL, MVT::v4i32, SDValue(Res, 0));
|
||||
|
||||
} else if (SplatValue.isSignedIntN(32) && SplatBitSize == 64 &&
|
||||
(ABI.IsN32() || ABI.IsN64())) {
|
||||
@ -1117,8 +1119,8 @@ bool MipsSEDAGToDAGISel::trySelect(SDNode *Node) {
|
||||
// $res4 = insert.w $res3[1], $res fill.d $res
|
||||
// splat.d $res4, 0
|
||||
//
|
||||
// The ability to use dinsu is guaranteed as MSA requires MIPSR5. This saves
|
||||
// having to materialize the value by shifts and ors.
|
||||
// The ability to use dinsu is guaranteed as MSA requires MIPSR5.
|
||||
// This saves having to materialize the value by shifts and ors.
|
||||
//
|
||||
// FIXME: Implement the preferred sequence for MIPS64R6:
|
||||
//
|
||||
@ -1239,7 +1241,8 @@ bool MipsSEDAGToDAGISel::trySelect(SDNode *Node) {
|
||||
llvm_unreachable(
|
||||
"Zero splat value handled by non-zero 64bit splat synthesis!");
|
||||
|
||||
Res = CurDAG->getMachineNode(Mips::FILL_D, DL, MVT::v2i64, SDValue(Res, 0));
|
||||
Res = CurDAG->getMachineNode(Mips::FILL_D, DL, MVT::v2i64,
|
||||
SDValue(Res, 0));
|
||||
} else
|
||||
llvm_unreachable("Unknown ABI in MipsISelDAGToDAG!");
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user