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[mips] Split long lines in the code. NFC

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This commit is contained in:
Simon Atanasyan 2019-11-02 16:33:10 +03:00
parent 50ba5815e2
commit bb3e46c8fe
28 changed files with 216 additions and 143 deletions
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4
lib/Target/Mips/AsmParser/MipsAsmParser.cpp
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@ -4013,8 +4013,8 @@ bool MipsAsmParser::expandCondBranches(MCInst &Inst, SMLoc IDLoc,
// D(S)DivMacro.
bool MipsAsmParser::expandDivRem(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
const MCSubtargetInfo *STI, const bool IsMips64,
const bool Signed) {
const MCSubtargetInfo *STI,
const bool IsMips64, const bool Signed) {
MipsTargetStreamer &TOut = getTargetStreamer();
warnIfNoMacro(IDLoc);

28
lib/Target/Mips/Disassembler/MipsDisassembler.cpp
View File

@ -446,16 +446,16 @@ static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
const void *Decoder);
template <typename InsnType>
static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn,
uint64_t Address, const void *Decoder);
template <typename InsnType>
static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address,
const void *Decoder);
template <typename InsnType>
static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn,
uint64_t Address, const void *Decoder);
template <typename InsnType>
static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address,
@ -630,8 +630,8 @@ static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
}
template <typename InsnType>
static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address,
const void *Decoder) {
static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn,
uint64_t Address, const void *Decoder) {
InsnType Rs = fieldFromInstruction(insn, 16, 5);
InsnType Imm = fieldFromInstruction(insn, 0, 16);
MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
@ -1091,8 +1091,10 @@ static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address,
InsnType Rs = fieldFromInstruction(Insn, 21, 5);
InsnType Rt = fieldFromInstruction(Insn, 16, 5);
MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt)));
MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs)));
MI.addOperand(
MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt)));
MI.addOperand(
MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs)));
MI.addOperand(MCOperand::createImm(Pos));
MI.addOperand(MCOperand::createImm(Size));
@ -1132,8 +1134,10 @@ static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address,
InsnType Rt = fieldFromInstruction(Insn, 16, 5);
MI.setOpcode(Mips::DINS);
MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt)));
MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs)));
MI.addOperand(
MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt)));
MI.addOperand(
MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs)));
MI.addOperand(MCOperand::createImm(Pos));
MI.addOperand(MCOperand::createImm(Size));
@ -1256,8 +1260,8 @@ DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
LLVM_DEBUG(
dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n");
// Calling the auto-generated decoder function.
Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn, Address,
this, STI);
Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn,
Address, this, STI);
if (Result != MCDisassembler::Fail) {
Size = 4;
return Result;

6
lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
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@ -585,6 +585,8 @@ MCAsmBackend *llvm::createMipsAsmBackend(const Target &T,
const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI,
const MCTargetOptions &Options) {
MipsABIInfo ABI = MipsABIInfo::computeTargetABI(STI.getTargetTriple(), STI.getCPU(), Options);
return new MipsAsmBackend(T, MRI, STI.getTargetTriple(), STI.getCPU(), ABI.IsN32());
MipsABIInfo ABI = MipsABIInfo::computeTargetABI(STI.getTargetTriple(),
STI.getCPU(), Options);
return new MipsAsmBackend(T, MRI, STI.getTargetTriple(), STI.getCPU(),
ABI.IsN32());
}

15
lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
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@ -600,7 +600,8 @@ getExprOpValue(const MCExpr *Expr, SmallVectorImpl<MCFixup> &Fixups,
}
if (Kind == MCExpr::Binary) {
unsigned Res = getExprOpValue(cast<MCBinaryExpr>(Expr)->getLHS(), Fixups, STI);
unsigned Res =
getExprOpValue(cast<MCBinaryExpr>(Expr)->getLHS(), Fixups, STI);
Res += getExprOpValue(cast<MCBinaryExpr>(Expr)->getRHS(), Fixups, STI);
return Res;
}
@ -729,7 +730,8 @@ getExprOpValue(const MCExpr *Expr, SmallVectorImpl<MCFixup> &Fixups,
default: llvm_unreachable("Unknown fixup kind!");
break;
case MCSymbolRefExpr::VK_None:
FixupKind = Mips::fixup_Mips_32; // FIXME: This is ok for O32/N32 but not N64.
// FIXME: This is ok for O32/N32 but not N64.
FixupKind = Mips::fixup_Mips_32;
break;
} // switch
@ -768,7 +770,8 @@ unsigned MipsMCCodeEmitter::getMemEncoding(const MCInst &MI, unsigned OpNo,
const MCSubtargetInfo &STI) const {
// Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
assert(MI.getOperand(OpNo).isReg());
unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups, STI) << 16;
unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI)
<< 16;
unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
// Apply the scale factor if there is one.
@ -857,7 +860,8 @@ getMemEncodingMMImm9(const MCInst &MI, unsigned OpNo,
assert(MI.getOperand(OpNo).isReg());
unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups,
STI) << 16;
unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo + 1), Fixups, STI);
unsigned OffBits =
getMachineOpValue(MI, MI.getOperand(OpNo + 1), Fixups, STI);
return (OffBits & 0x1FF) | RegBits;
}
@ -892,7 +896,8 @@ getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo,
// Base register is encoded in bits 20-16, offset is encoded in bits 11-0.
assert(MI.getOperand(OpNo).isReg());
unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) << 16;
unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI)
<< 16;
unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
return (OffBits & 0x0FFF) | RegBits;

3
lib/Target/Mips/MCTargetDesc/MipsMCExpr.cpp
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@ -211,7 +211,8 @@ MipsMCExpr::evaluateAsRelocatableImpl(MCValue &Res,
// The value of getKind() that is given to MCValue is only intended to aid
// debugging when inspecting MCValue objects. It shouldn't be relied upon
// for decision making.
Res = MCValue::get(Res.getSymA(), Res.getSymB(), Res.getConstant(), getKind());
Res =
MCValue::get(Res.getSymA(), Res.getSymB(), Res.getConstant(), getKind());
return true;
}

17
lib/Target/Mips/MicroMips32r6InstrFormats.td
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@ -234,7 +234,8 @@ class POOL32A_FM_MMR6<bits<10> funct> : MipsR6Inst {
let Inst{9-0} = funct;
}
class POOL32A_PAUSE_FM_MMR6<string instr_asm, bits<5> op> : MMR6Arch<instr_asm> {
class POOL32A_PAUSE_FM_MMR6<string instr_asm, bits<5> op>
: MMR6Arch<instr_asm> {
bits<32> Inst;
let Inst{31-26} = 0;
@ -512,7 +513,8 @@ class BARRIER_MMR6_ENC<string instr_asm, bits<5> op> : MMR6Arch<instr_asm> {
class POOL32A_EIDI_MMR6_ENC<string instr_asm, bits<10> funct>
: MMR6Arch<instr_asm> {
bits<32> Inst;
bits<5> rt; // Actually rs but we're sharing code with the standard encodings which call it rt
bits<5> rt; // Actually rs but we're sharing code with the standard encodings
// which call it rt
let Inst{31-26} = 0x00;
let Inst{25-21} = 0x00;
@ -521,7 +523,8 @@ class POOL32A_EIDI_MMR6_ENC<string instr_asm, bits<10> funct>
let Inst{5-0} = 0x3c;
}
class SHIFT_MMR6_ENC<string instr_asm, bits<10> funct, bit rotate> : MMR6Arch<instr_asm> {
class SHIFT_MMR6_ENC<string instr_asm, bits<10> funct, bit rotate>
: MMR6Arch<instr_asm> {
bits<5> rd;
bits<5> rt;
bits<5> shamt;
@ -809,8 +812,8 @@ class POOL32F_RECIP_ROUND_FM_MMR6<string instr_asm, bits<1> fmt, bits<8> funct>
let Inst{5-0} = 0b111011;
}
class POOL32F_RINT_FM_MMR6<string instr_asm, bits<2> fmt>
: MMR6Arch<instr_asm>, MipsR6Inst {
class POOL32F_RINT_FM_MMR6<string instr_asm, bits<2> fmt> : MMR6Arch<instr_asm>,
MipsR6Inst {
bits<5> fs;
bits<5> fd;
@ -1012,8 +1015,8 @@ class POOL32B_LDWC2_SDWC2_FM_MMR6<string instr_asm, bits<4> funct>
}
class POOL32C_LL_E_SC_E_FM_MMR6<string instr_asm, bits<4> majorFunc,
bits<3> minorFunc>
: MMR6Arch<instr_asm>, MipsR6Inst {
bits<3> minorFunc> : MMR6Arch<instr_asm>,
MipsR6Inst {
bits<5> rt;
bits<21> addr;
bits<5> base = addr{20-16};

22
lib/Target/Mips/MicroMips32r6InstrInfo.td
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@ -341,7 +341,8 @@ class BNEC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bnec", brtarget_lsl2_mm,
GPR32Opnd>;
class ADD_MMR6_DESC : ArithLogicR<"add", GPR32Opnd, 1, II_ADD>;
class ADDIU_MMR6_DESC : ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16, add>;
class ADDIU_MMR6_DESC
: ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16, add>;
class ADDU_MMR6_DESC : ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU>;
class MUL_MMR6_DESC : ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>;
class MUH_MMR6_DESC : ArithLogicR<"muh", GPR32Opnd, 1, II_MUH, mulhs>;
@ -1045,8 +1046,8 @@ class TRUNC_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.d", FGR32Opnd,
FGR64Opnd, II_TRUNC>;
class SQRT_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.s", FGR32Opnd, FGR32Opnd,
II_SQRT_S, fsqrt>;
class SQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.d", AFGR64Opnd, AFGR64Opnd,
II_SQRT_D, fsqrt>;
class SQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.d", AFGR64Opnd,
AFGR64Opnd, II_SQRT_D, fsqrt>;
class ROUND_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.l.s", FGR64Opnd,
FGR32Opnd, II_ROUND>;
class ROUND_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.l.d", FGR64Opnd,
@ -1101,14 +1102,16 @@ class SLL16_MMR6_DESC : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>,
MMR6Arch<"sll16">;
class SRL16_MMR6_DESC : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>,
MMR6Arch<"srl16">;
class BREAK16_MMR6_DESC : BrkSdbbp16MM<"break16", II_BREAK>, MMR6Arch<"break16">;
class BREAK16_MMR6_DESC : BrkSdbbp16MM<"break16", II_BREAK>,
MMR6Arch<"break16">;
class LI16_MMR6_DESC : LoadImmMM16<"li16", li16_imm, GPRMM16Opnd>,
MMR6Arch<"li16">, IsAsCheapAsAMove;
class MOVE16_MMR6_DESC : MoveMM16<"move16", GPR32Opnd>, MMR6Arch<"move16">;
class MOVEP_MMR6_DESC : MovePMM16<"movep", GPRMM16OpndMovePPairFirst,
GPRMM16OpndMovePPairSecond, GPRMM16OpndMoveP>,
MMR6Arch<"movep">;
class SDBBP16_MMR6_DESC : BrkSdbbp16MM<"sdbbp16", II_SDBBP>, MMR6Arch<"sdbbp16">;
class SDBBP16_MMR6_DESC : BrkSdbbp16MM<"sdbbp16", II_SDBBP>,
MMR6Arch<"sdbbp16">;
class SUBU16_MMR6_DESC : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
MMR6Arch<"subu16"> {
int AddedComplexity = 1;
@ -1439,7 +1442,8 @@ def SYNCI_MMR6 : StdMMR6Rel, SYNCI_MMR6_DESC, SYNCI_MMR6_ENC, ISA_MICROMIPS32R6;
def RDPGPR_MMR6 : R6MMR6Rel, RDPGPR_MMR6_DESC, RDPGPR_MMR6_ENC,
ISA_MICROMIPS32R6;
def SDBBP_MMR6 : R6MMR6Rel, SDBBP_MMR6_DESC, SDBBP_MMR6_ENC, ISA_MICROMIPS32R6;
def SIGRIE_MMR6 : R6MMR6Rel, SIGRIE_MMR6_DESC, SIGRIE_MMR6_ENC, ISA_MICROMIPS32R6;
def SIGRIE_MMR6 : R6MMR6Rel, SIGRIE_MMR6_DESC, SIGRIE_MMR6_ENC,
ISA_MICROMIPS32R6;
def XOR_MMR6 : StdMMR6Rel, XOR_MMR6_DESC, XOR_MMR6_ENC, ISA_MICROMIPS32R6;
def XORI_MMR6 : StdMMR6Rel, XORI_MMR6_DESC, XORI_MMR6_ENC, ISA_MICROMIPS32R6;
let DecoderMethod = "DecodeMemMMImm16" in {
@ -1557,7 +1561,8 @@ def INS_MMR6 : StdMMR6Rel, INS_MMR6_ENC, INS_MMR6_DESC, ISA_MICROMIPS32R6;
def JALRC_MMR6 : R6MMR6Rel, JALRC_MMR6_ENC, JALRC_MMR6_DESC, ISA_MICROMIPS32R6;
def RINT_S_MMR6 : StdMMR6Rel, RINT_S_MMR6_ENC, RINT_S_MMR6_DESC,
ISA_MICROMIPS32R6;
def RINT_D_MMR6 : StdMMR6Rel, RINT_D_MMR6_ENC, RINT_D_MMR6_DESC, ISA_MICROMIPS32R6;
def RINT_D_MMR6 : StdMMR6Rel, RINT_D_MMR6_ENC, RINT_D_MMR6_DESC,
ISA_MICROMIPS32R6;
def ROUND_L_S_MMR6 : StdMMR6Rel, ROUND_L_S_MMR6_ENC, ROUND_L_S_MMR6_DESC,
ISA_MICROMIPS32R6;
def ROUND_L_D_MMR6 : StdMMR6Rel, ROUND_L_D_MMR6_ENC, ROUND_L_D_MMR6_DESC,
@ -1751,7 +1756,8 @@ defm S_MMR6 : Cmp_Pats<f32, NOR_MMR6, ZERO>, ISA_MICROMIPS32R6;
defm D_MMR6 : Cmp_Pats<f64, NOR_MMR6, ZERO>, ISA_MICROMIPS32R6;
def : MipsPat<(f32 fpimm0), (MTC1_MMR6 ZERO)>, ISA_MICROMIPS32R6;
def : MipsPat<(f32 fpimm0neg), (FNEG_S_MMR6 (MTC1_MMR6 ZERO))>, ISA_MICROMIPS32R6;
def : MipsPat<(f32 fpimm0neg), (FNEG_S_MMR6(MTC1_MMR6 ZERO))>,
ISA_MICROMIPS32R6;
def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src),
(TRUNC_W_D_MMR6 FGR64Opnd:$src)>, ISA_MICROMIPS32R6;
def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src),

3
lib/Target/Mips/MicroMipsInstrFPU.td
View File

@ -230,7 +230,8 @@ let DecoderNamespace = "MicroMips" in {
def FSQRT_S_MM : MMRel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, II_SQRT_S,
fsqrt>, ROUND_W_FM_MM<0, 0x28>, ISA_MICROMIPS;
def MTHC1_D32_MM : MMRel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>,
def MTHC1_D32_MM : MMRel,
MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>,
MFC1_FM_MM<0xe0>, ISA_MICROMIPS, FGR_32;
def MFHC1_D32_MM : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>,
MFC1_FM_MM<0xc0>, ISA_MICROMIPS, FGR_32;

3
lib/Target/Mips/MicroMipsInstrInfo.td
View File

@ -506,7 +506,8 @@ class LoadWordIndexedScaledMM<string opstr, RegisterOperand RO,
class PrefetchIndexed<string opstr> :
InstSE<(outs), (ins PtrRC:$base, PtrRC:$index, uimm5:$hint),
!strconcat(opstr, "\t$hint, ${index}(${base})"), [], II_PREF, FrmOther>;
!strconcat(opstr, "\t$hint, ${index}(${base})"),
[], II_PREF, FrmOther>;
class AddImmUPC<string opstr, RegisterOperand RO> :
InstSE<(outs RO:$rs), (ins simm23_lsl2:$imm),

3
lib/Target/Mips/Mips.td
View File

@ -201,7 +201,8 @@ def FeatureUseTCCInDIV : SubtargetFeature<
"UseTCCInDIV", "false",
"Force the assembler to use trapping">;
def FeatureMadd4 : SubtargetFeature<"nomadd4", "DisableMadd4", "true",
def FeatureMadd4
: SubtargetFeature<"nomadd4", "DisableMadd4", "true",
"Disable 4-operand madd.fmt and related instructions">;
def FeatureMT : SubtargetFeature<"mt", "HasMT", "true", "Mips MT ASE">;

3
lib/Target/Mips/Mips16InstrInfo.cpp
View File

@ -418,7 +418,8 @@ unsigned Mips16InstrInfo::loadImmediate(unsigned FrameReg, int64_t Imm,
else
Available.reset(SpReg);
copyPhysReg(MBB, II, DL, SpReg, Mips::SP, false);
BuildMI(MBB, II, DL, get(Mips:: AdduRxRyRz16), Reg).addReg(SpReg, RegState::Kill)
BuildMI(MBB, II, DL, get(Mips::AdduRxRyRz16), Reg)
.addReg(SpReg, RegState::Kill)
.addReg(Reg);
}
else

6
lib/Target/Mips/Mips32r6InstrInfo.td
View File

@ -996,13 +996,15 @@ def : MipsInstAlias<"evp", (EVP ZERO), 0>, ISA_MIPS32R6;
let AdditionalPredicates = [NotInMicroMips] in {
def : MipsInstAlias<"sdbbp", (SDBBP_R6 0)>, ISA_MIPS32R6;
def : MipsInstAlias<"sigrie", (SIGRIE 0)>, ISA_MIPS32R6;
def : MipsInstAlias<"jr $rs", (JALR ZERO, GPR32Opnd:$rs), 1>, ISA_MIPS32R6, GPR_32;
def : MipsInstAlias<"jr $rs", (JALR ZERO, GPR32Opnd:$rs), 1>,
ISA_MIPS32R6, GPR_32;
}
def : MipsInstAlias<"jrc $rs", (JIC GPR32Opnd:$rs, 0), 1>, ISA_MIPS32R6, GPR_32;
let AdditionalPredicates = [NotInMicroMips] in {
def : MipsInstAlias<"jalrc $rs", (JIALC GPR32Opnd:$rs, 0), 1>, ISA_MIPS32R6, GPR_32;
def : MipsInstAlias<"jalrc $rs", (JIALC GPR32Opnd:$rs, 0), 1>,
ISA_MIPS32R6, GPR_32;
}
def : MipsInstAlias<"div $rs, $rt", (DIV GPR32Opnd:$rs, GPR32Opnd:$rs,

12
lib/Target/Mips/Mips64InstrInfo.td
View File

@ -395,9 +395,9 @@ let AdditionalPredicates = [NotInMicroMips] in {
}
let isCodeGenOnly = 1, AdditionalPredicates = [NotInMicroMips] in {
def DEXT64_32 : InstSE<(outs GPR64Opnd:$rt),
(ins GPR32Opnd:$rs, uimm5_report_uimm6:$pos,
uimm5_plus1:$size),
def DEXT64_32
: InstSE<(outs GPR64Opnd:$rt),
(ins GPR32Opnd:$rs, uimm5_report_uimm6:$pos, uimm5_plus1:$size),
"dext $rt, $rs, $pos, $size", [], II_EXT, FrmR, "dext">,
EXT_FM<3>, ISA_MIPS64R2;
}
@ -1027,8 +1027,10 @@ let AdditionalPredicates = [NotInMicroMips] in {
(DMTGC0 COP0Opnd:$rd, GPR64Opnd:$rt, 0), 0>,
ISA_MIPS64R5, ASE_VIRT;
}
def : MipsInstAlias<"dmfc2 $rt, $rd", (DMFC2 GPR64Opnd:$rt, COP2Opnd:$rd, 0), 0>;
def : MipsInstAlias<"dmtc2 $rt, $rd", (DMTC2 COP2Opnd:$rd, GPR64Opnd:$rt, 0), 0>;
def : MipsInstAlias<"dmfc2 $rt, $rd",
(DMFC2 GPR64Opnd:$rt, COP2Opnd:$rd, 0), 0>;
def : MipsInstAlias<"dmtc2 $rt, $rd",
(DMTC2 COP2Opnd:$rd, GPR64Opnd:$rt, 0), 0>;
def : MipsInstAlias<"synciobdma", (SYNC 0x2), 0>, ASE_MIPS64_CNMIPS;
def : MipsInstAlias<"syncs", (SYNC 0x6), 0>, ASE_MIPS64_CNMIPS;

3
lib/Target/Mips/Mips64r6InstrInfo.td
View File

@ -48,7 +48,8 @@ class CRC32CD_ENC : SPECIAL3_2R_SZ_CRC<3,1>;
//
//===----------------------------------------------------------------------===//
class AHI_ATI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, InstrItinClass itin> {
class AHI_ATI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
InstrItinClass itin> {
dag OutOperandList = (outs GPROpnd:$rs);
dag InOperandList = (ins GPROpnd:$rt, uimm16_altrelaxed:$imm);
string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $imm");

6
lib/Target/Mips/MipsAsmPrinter.cpp
View File

@ -623,8 +623,10 @@ bool MipsAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
assert(OpNum + 1 < MI->getNumOperands() && "Insufficient operands");
const MachineOperand &BaseMO = MI->getOperand(OpNum);
const MachineOperand &OffsetMO = MI->getOperand(OpNum + 1);
assert(BaseMO.isReg() && "Unexpected base pointer for inline asm memory operand.");
assert(OffsetMO.isImm() && "Unexpected offset for inline asm memory operand.");
assert(BaseMO.isReg() &&
"Unexpected base pointer for inline asm memory operand.");
assert(OffsetMO.isImm() &&
"Unexpected offset for inline asm memory operand.");
int Offset = OffsetMO.getImm();
// Currently we are expecting either no ExtraCode or 'D','M','L'.

3
lib/Target/Mips/MipsCallLowering.cpp
View File

@ -655,7 +655,8 @@ bool MipsCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
MipsCCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs,
F.getContext());
CCInfo.AnalyzeCallResult(Ins, TLI.CCAssignFnForReturn(), Info.OrigRet.Ty, Call);
CCInfo.AnalyzeCallResult(Ins, TLI.CCAssignFnForReturn(), Info.OrigRet.Ty,
Call);
setLocInfo(ArgLocs, Ins);
CallReturnHandler Handler(MIRBuilder, MF.getRegInfo(), MIB);

3
lib/Target/Mips/MipsCallingConv.td
View File

@ -139,7 +139,8 @@ def CC_MipsN : CallingConv<[
CCIfType<[i8, i16, i32], CCIfOrigArgWasNotFloat<CCPromoteToType<i64>>>,
// The only i32's we have left are soft-float arguments.
CCIfSubtarget<"useSoftFloat()", CCIfType<[i32], CCDelegateTo<CC_MipsN_SoftFloat>>>,
CCIfSubtarget<"useSoftFloat()", CCIfType<[i32],
CCDelegateTo<CC_MipsN_SoftFloat>>>,
// Integer arguments are passed in integer registers.
CCIfType<[i64], CCAssignToRegWithShadow<[A0_64, A1_64, A2_64, A3_64,

12
lib/Target/Mips/MipsCondMov.td
View File

@ -226,8 +226,8 @@ let AdditionalPredicates = [NotInMicroMips] in {
GPR_64;
defm : MovnPats<GPR64, GPR32, MOVN_I64_I, XOR64>, INSN_MIPS4_32_NOT_32R6_64R6,
GPR_64;
defm : MovnPats<GPR64, GPR64, MOVN_I64_I64, XOR64>, INSN_MIPS4_32_NOT_32R6_64R6,
GPR_64;
defm : MovnPats<GPR64, GPR64, MOVN_I64_I64, XOR64>,
INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
defm : MovzPats0<GPR32, FGR32, MOVZ_I_S, SLT, SLTu, SLTi, SLTiu>,
INSN_MIPS4_32_NOT_32R6_64R6;
@ -236,8 +236,8 @@ let AdditionalPredicates = [NotInMicroMips] in {
defm : MovzPats0<GPR64, FGR32, MOVZ_I_S, SLT64, SLTu64, SLTi64, SLTiu64>,
INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
defm : MovzPats1<GPR64, FGR32, MOVZ_I64_S, XOR64>, INSN_MIPS4_32_NOT_32R6_64R6,
GPR_64;
defm : MovzPats1<GPR64, FGR32, MOVZ_I64_S, XOR64>,
INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
defm : MovnPats<GPR64, FGR32, MOVN_I64_S, XOR64>, INSN_MIPS4_32_NOT_32R6_64R6,
GPR_64;
@ -258,8 +258,8 @@ let AdditionalPredicates = [NotInMicroMips] in {
INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;
defm : MovnPats<GPR32, FGR64, MOVN_I_D64, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,
FGR_64;
defm : MovnPats<GPR64, FGR64, MOVN_I64_D64, XOR64>, INSN_MIPS4_32_NOT_32R6_64R6,
FGR_64;
defm : MovnPats<GPR64, FGR64, MOVN_I64_D64, XOR64>,
INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;
}
// For targets that don't have conditional-move instructions
// we have to match SELECT nodes with pseudo instructions.

10
lib/Target/Mips/MipsConstantIslandPass.cpp
View File

@ -127,9 +127,9 @@ static unsigned int longformBranchOpcode(unsigned int Opcode) {
llvm_unreachable("Unknown branch type");
}
// FIXME: need to go through this whole constant islands port and check the math
// for branch ranges and clean this up and make some functions to calculate things
// that are done many times identically.
// FIXME: need to go through this whole constant islands port and check
// the math for branch ranges and clean this up and make some functions
// to calculate things that are done many times identically.
// Need to refactor some of the code to call this routine.
static unsigned int branchMaxOffsets(unsigned int Opcode) {
unsigned Bits, Scale;
@ -1519,8 +1519,8 @@ MipsConstantIslands::fixupUnconditionalBr(ImmBranch &Br) {
// we know that RA is saved because we always save it right now.
// this requirement will be relaxed later but we also have an alternate
// way to implement this that I will implement that does not need jal.
// We should have a way to back out this alignment restriction if we "can" later.
// but it is not harmful.
// We should have a way to back out this alignment restriction
// if we "can" later. but it is not harmful.
//
DestBB->setAlignment(Align(4));
Br.MaxDisp = ((1<<24)-1) * 2;

9
lib/Target/Mips/MipsDSPInstrInfo.td
View File

@ -386,7 +386,8 @@ class ADDUH_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
}
class APPEND_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
Operand ImmOp, SDPatternOperator Imm, InstrItinClass itin> {
Operand ImmOp, SDPatternOperator Imm,
InstrItinClass itin> {
dag OutOperandList = (outs GPR32Opnd:$rt);
dag InOperandList = (ins GPR32Opnd:$rs, ImmOp:$sa, GPR32Opnd:$src);
string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa");
@ -511,7 +512,8 @@ class MFHI_DESC_BASE<string instr_asm, RegisterOperand RO, SDNode OpNode,
bit isMoveReg = 1;
}
class MTHI_DESC_BASE<string instr_asm, RegisterOperand RO, InstrItinClass itin> {
class MTHI_DESC_BASE<string instr_asm, RegisterOperand RO,
InstrItinClass itin> {
dag OutOperandList = (outs RO:$ac);
dag InOperandList = (ins GPR32Opnd:$rs);
string AsmString = !strconcat(instr_asm, "\t$rs, $ac");
@ -1304,7 +1306,8 @@ let DecoderNamespace = "MipsDSP", Arch = "dsp",
// Pseudo CMP and PICK instructions.
class PseudoCMP<Instruction RealInst> :
PseudoDSP<(outs DSPCC:$cmp), (ins DSPROpnd:$rs, DSPROpnd:$rt), []>,
PseudoInstExpansion<(RealInst DSPROpnd:$rs, DSPROpnd:$rt)>, NeverHasSideEffects;
PseudoInstExpansion<(RealInst DSPROpnd:$rs, DSPROpnd:$rt)>,
NeverHasSideEffects;
class PseudoPICK<Instruction RealInst> :
PseudoDSP<(outs DSPROpnd:$rd), (ins DSPCC:$cmp, DSPROpnd:$rs, DSPROpnd:$rt), []>,

19
lib/Target/Mips/MipsDelaySlotFiller.cpp
View File

@ -91,15 +91,14 @@ enum CompactBranchPolicy {
};
static cl::opt<CompactBranchPolicy> MipsCompactBranchPolicy(
"mips-compact-branches",cl::Optional,
cl::init(CB_Optimal),
"mips-compact-branches", cl::Optional, cl::init(CB_Optimal),
cl::desc("MIPS Specific: Compact branch policy."),
cl::values(
clEnumValN(CB_Never, "never", "Do not use compact branches if possible."),
clEnumValN(CB_Optimal, "optimal", "Use compact branches where appropiate (default)."),
clEnumValN(CB_Always, "always", "Always use compact branches if possible.")
)
);
cl::values(clEnumValN(CB_Never, "never",
"Do not use compact branches if possible."),
clEnumValN(CB_Optimal, "optimal",
"Use compact branches where appropiate (default)."),
clEnumValN(CB_Always, "always",
"Always use compact branches if possible.")));
namespace {
@ -927,4 +926,6 @@ bool MipsDelaySlotFiller::terminateSearch(const MachineInstr &Candidate) const {
/// createMipsDelaySlotFillerPass - Returns a pass that fills in delay
/// slots in Mips MachineFunctions
FunctionPass *llvm::createMipsDelaySlotFillerPass() { return new MipsDelaySlotFiller(); }
FunctionPass *llvm::createMipsDelaySlotFillerPass() {
return new MipsDelaySlotFiller();
}

10
lib/Target/Mips/MipsExpandPseudo.cpp
View File

@ -604,8 +604,14 @@ bool MipsExpandPseudo::expandAtomicBinOp(MachineBasicBlock &BB,
BuildMI(loopMBB, DL, TII->get(OR), Scratch).addReg(Incr).addReg(ZERO);
}
BuildMI(loopMBB, DL, TII->get(SC), Scratch).addReg(Scratch).addReg(Ptr).addImm(0);
BuildMI(loopMBB, DL, TII->get(BEQ)).addReg(Scratch).addReg(ZERO).addMBB(loopMBB);
BuildMI(loopMBB, DL, TII->get(SC), Scratch)
.addReg(Scratch)
.addReg(Ptr)
.addImm(0);
BuildMI(loopMBB, DL, TII->get(BEQ))
.addReg(Scratch)
.addReg(ZERO)
.addMBB(loopMBB);
NMBBI = BB.end();
I->eraseFromParent();

19
lib/Target/Mips/MipsISelLowering.cpp
View File

@ -528,7 +528,8 @@ MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM,
isMicroMips = Subtarget.inMicroMipsMode();
}
const MipsTargetLowering *MipsTargetLowering::create(const MipsTargetMachine &TM,
const MipsTargetLowering *
MipsTargetLowering::create(const MipsTargetMachine &TM,
const MipsSubtarget &STI) {
if (STI.inMips16Mode())
return createMips16TargetLowering(TM, STI);
@ -2804,7 +2805,8 @@ static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
// allocate a register directly.
Reg = State.AllocateReg(IntRegs);
}
} else if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
} else if (ValVT == MVT::i32 ||
(ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
Reg = State.AllocateReg(IntRegs);
// If this is the first part of an i64 arg,
// the allocated register must be either A0 or A2.
@ -3625,8 +3627,8 @@ MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
return CCInfo.CheckReturn(Outs, RetCC_Mips);
}
bool
MipsTargetLowering::shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
bool MipsTargetLowering::shouldSignExtendTypeInLibCall(EVT Type,
bool IsSigned) const {
if ((ABI.IsN32() || ABI.IsN64()) && Type == MVT::i32)
return true;
@ -4113,7 +4115,8 @@ void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
bool MipsTargetLowering::isLegalAddressingMode(const DataLayout &DL,
const AddrMode &AM, Type *Ty,
unsigned AS, Instruction *I) const {
unsigned AS,
Instruction *I) const {
// No global is ever allowed as a base.
if (AM.BaseGV)
return false;
@ -4489,7 +4492,8 @@ MachineBasicBlock *MipsTargetLowering::emitPseudoSELECT(MachineInstr &MI,
return BB;
}
MachineBasicBlock *MipsTargetLowering::emitPseudoD_SELECT(MachineInstr &MI,
MachineBasicBlock *
MipsTargetLowering::emitPseudoD_SELECT(MachineInstr &MI,
MachineBasicBlock *BB) const {
assert(!(Subtarget.hasMips4() || Subtarget.hasMips32()) &&
"Subtarget already supports SELECT nodes with the use of"
@ -4566,7 +4570,8 @@ MachineBasicBlock *MipsTargetLowering::emitPseudoD_SELECT(MachineInstr &MI,
// FIXME? Maybe this could be a TableGen attribute on some registers and
// this table could be generated automatically from RegInfo.
Register MipsTargetLowering::getRegisterByName(const char* RegName, EVT VT,
Register
MipsTargetLowering::getRegisterByName(const char *RegName, EVT VT,
const MachineFunction &MF) const {
// Named registers is expected to be fairly rare. For now, just support $28
// since the linux kernel uses it.

30
lib/Target/Mips/MipsInstrFPU.td
View File

@ -129,7 +129,8 @@ class ABSS_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
HARDFLOAT,
NeverHasSideEffects;
class CVT_PS_S_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, InstrItinClass Itin, bit IsComm,
class CVT_PS_S_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
InstrItinClass Itin, bit IsComm,
SDPatternOperator OpNode = null_frag> :
InstSE<(outs DstRC:$fd), (ins SrcRC:$fs, SrcRC:$ft),
!strconcat(opstr, "\t$fd, $fs, $ft"),
@ -142,7 +143,8 @@ multiclass ABSS_M<string opstr, InstrItinClass Itin,
SDPatternOperator OpNode= null_frag> {
def _D32 : MMRel, ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>,
FGR_32;
def _D64 : StdMMR6Rel, ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>, FGR_64 {
def _D64 : StdMMR6Rel, ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>,
FGR_64 {
string DecoderNamespace = "MipsFP64";
}
}
@ -362,14 +364,18 @@ defm D64 : C_COND_M<"d", FGR64Opnd, 17, II_C_CC_D>, ISA_MIPS1_NOT_32R6_64R6,
// Floating Point Instructions
//===----------------------------------------------------------------------===//
let AdditionalPredicates = [NotInMicroMips] in {
def ROUND_W_S : MMRel, StdMMR6Rel, ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, II_ROUND>,
def ROUND_W_S : MMRel, StdMMR6Rel,
ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, II_ROUND>,
ABSS_FM<0xc, 16>, ISA_MIPS2;
defm ROUND_W : ROUND_M<"round.w.d", II_ROUND>, ABSS_FM<0xc, 17>, ISA_MIPS2;
def TRUNC_W_S : MMRel, StdMMR6Rel, ABSS_FT<"trunc.w.s", FGR32Opnd, FGR32Opnd, II_TRUNC>,
def TRUNC_W_S : MMRel, StdMMR6Rel,
ABSS_FT<"trunc.w.s", FGR32Opnd, FGR32Opnd, II_TRUNC>,
ABSS_FM<0xd, 16>, ISA_MIPS2;
def CEIL_W_S : MMRel, StdMMR6Rel, ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, II_CEIL>,
def CEIL_W_S : MMRel, StdMMR6Rel,
ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, II_CEIL>,
ABSS_FM<0xe, 16>, ISA_MIPS2;
def FLOOR_W_S : MMRel, StdMMR6Rel, ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd, II_FLOOR>,
def FLOOR_W_S : MMRel, StdMMR6Rel,
ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd, II_FLOOR>,
ABSS_FM<0xf, 16>, ISA_MIPS2;
def CVT_W_S : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>,
ABSS_FM<0x24, 16>, ISA_MIPS1;
@ -536,7 +542,8 @@ let AdditionalPredicates = [NotInMicroMips] in {
let DecoderNamespace = "MipsFP64";
}
def MTHC1_D32 : MMRel, StdMMR6Rel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>,
def MTHC1_D32 : MMRel, StdMMR6Rel,
MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>,
MFC1_FM<7>, ISA_MIPS32R2, FGR_32;
def MTHC1_D64 : MTC1_64_FT<"mthc1", FGR64Opnd, GPR32Opnd, II_MTHC1>,
MFC1_FM<7>, ISA_MIPS32R2, FGR_64 {
@ -950,9 +957,12 @@ multiclass NMADD_NMSUB<Instruction Nmadd, Instruction Nmsub, RegisterOperand RC>
}
let AdditionalPredicates = [NoNaNsFPMath, HasMadd4, NotInMicroMips] in {
defm : NMADD_NMSUB<NMADD_S, NMSUB_S, FGR32Opnd>, INSN_MIPS4_32R2_NOT_32R6_64R6;
defm : NMADD_NMSUB<NMADD_D32, NMSUB_D32, AFGR64Opnd>, FGR_32, INSN_MIPS4_32R2_NOT_32R6_64R6;
defm : NMADD_NMSUB<NMADD_D64, NMSUB_D64, FGR64Opnd>, FGR_64, INSN_MIPS4_32R2_NOT_32R6_64R6;
defm : NMADD_NMSUB<NMADD_S, NMSUB_S, FGR32Opnd>,
INSN_MIPS4_32R2_NOT_32R6_64R6;
defm : NMADD_NMSUB<NMADD_D32, NMSUB_D32, AFGR64Opnd>,
FGR_32, INSN_MIPS4_32R2_NOT_32R6_64R6;
defm : NMADD_NMSUB<NMADD_D64, NMSUB_D64, FGR64Opnd>,
FGR_64, INSN_MIPS4_32R2_NOT_32R6_64R6;
}
// Patterns for loads/stores with a reg+imm operand.

4
lib/Target/Mips/MipsInstrInfo.cpp
View File

@ -275,7 +275,8 @@ MipsInstrInfo::BranchType MipsInstrInfo::analyzeBranch(
return BT_CondUncond;
}
bool MipsInstrInfo::isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const {
bool MipsInstrInfo::isBranchOffsetInRange(unsigned BranchOpc,
int64_t BrOffset) const {
switch (BranchOpc) {
case Mips::B:
case Mips::BAL:
@ -433,7 +434,6 @@ bool MipsInstrInfo::isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset)
llvm_unreachable("Unknown branch instruction!");
}
/// Return the corresponding compact (no delay slot) form of a branch.
unsigned MipsInstrInfo::getEquivalentCompactForm(
const MachineBasicBlock::iterator I) const {

27
lib/Target/Mips/MipsInstrInfo.td
View File

@ -2137,7 +2137,8 @@ let AdditionalPredicates = [NotInMicroMips] in {
LW_FM<0x28>, ISA_MIPS1;
def SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>,
ISA_MIPS1;
def SW : StdMMR6Rel, Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>, ISA_MIPS1;
def SW : StdMMR6Rel, Store<"sw", GPR32Opnd, store, II_SW>,
MMRel, LW_FM<0x2b>, ISA_MIPS1;
}
/// load/store left/right
@ -2238,7 +2239,8 @@ def J : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>,
IsBranch, ISA_MIPS1;
let AdditionalPredicates = [NotInMicroMips] in {
def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>, ISA_MIPS1_NOT_32R6_64R6;
def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>,
ISA_MIPS1_NOT_32R6_64R6;
def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>,
ISA_MIPS1;
def BEQL : MMRel, CBranchLikely<"beql", brtarget, GPR32Opnd>,
@ -2396,7 +2398,8 @@ let AdditionalPredicates = [NotInMicroMips] in {
// add op with mem ComplexPattern is used and the stack address copy
// can be matched. It's similar to Sparc LEA_ADDRi
let AdditionalPredicates = [NotInMicroMips] in
def LEA_ADDiu : MMRel, EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>, ISA_MIPS1;
def LEA_ADDiu : MMRel, EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>,
ISA_MIPS1;
// MADD*/MSUB*
def MADD : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>,
@ -2572,9 +2575,11 @@ def DROLImm : MipsAsmPseudoInst<(outs),
(ins GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm),
"drol\t$rs, $rt, $imm">, ISA_MIPS64;
def : MipsInstAlias<"drol $rd, $rs",
(DROL GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rs), 0>, ISA_MIPS64;
(DROL GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rs), 0>,
ISA_MIPS64;
def : MipsInstAlias<"drol $rd, $imm",
(DROLImm GPR32Opnd:$rd, GPR32Opnd:$rd, simm16:$imm), 0>, ISA_MIPS64;
(DROLImm GPR32Opnd:$rd, GPR32Opnd:$rd, simm16:$imm), 0>,
ISA_MIPS64;
def DROR : MipsAsmPseudoInst<(outs),
(ins GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rd),
@ -2583,9 +2588,11 @@ def DRORImm : MipsAsmPseudoInst<(outs),
(ins GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm),
"dror\t$rs, $rt, $imm">, ISA_MIPS64;
def : MipsInstAlias<"dror $rd, $rs",
(DROR GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rs), 0>, ISA_MIPS64;
(DROR GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rs), 0>,
ISA_MIPS64;
def : MipsInstAlias<"dror $rd, $imm",
(DRORImm GPR32Opnd:$rd, GPR32Opnd:$rd, simm16:$imm), 0>, ISA_MIPS64;
(DRORImm GPR32Opnd:$rd, GPR32Opnd:$rd, simm16:$imm), 0>,
ISA_MIPS64;
def ABSMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), (ins GPR32Opnd:$rs),
"abs\t$rd, $rs">;
@ -2762,7 +2769,8 @@ let AdditionalPredicates = [NotInMicroMips] in {
def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>, ISA_MIPS1;
defm : OneOrTwoOperandMacroImmediateAlias<"add", ADDi>, ISA_MIPS1_NOT_32R6_64R6;
defm : OneOrTwoOperandMacroImmediateAlias<"add", ADDi>,
ISA_MIPS1_NOT_32R6_64R6;
defm : OneOrTwoOperandMacroImmediateAlias<"addu", ADDiu>, ISA_MIPS1;
@ -3089,7 +3097,8 @@ multiclass MaterializeImms<ValueType VT, Register ZEROReg,
// observed.
// Arbitrary immediates
def : MipsPat<(VT LUiORiPred:$imm), (ORiOp (LUiOp (HI16 imm:$imm)), (LO16 imm:$imm))>;
def : MipsPat<(VT LUiORiPred:$imm),
(ORiOp (LUiOp (HI16 imm:$imm)), (LO16 imm:$imm))>;
// Bits 32-16 set, sign/zero extended.
def : MipsPat<(VT LUiPred:$imm), (LUiOp (HI16 imm:$imm))>;

6
lib/Target/Mips/MipsInstructionSelector.cpp
View File

@ -139,7 +139,8 @@ bool MipsInstructionSelector::materialize32BitImm(Register DestReg, APInt Imm,
assert(Imm.getBitWidth() == 32 && "Unsupported immediate size.");
// Ori zero extends immediate. Used for values with zeros in high 16 bits.
if (Imm.getHiBits(16).isNullValue()) {
MachineInstr *Inst = B.buildInstr(Mips::ORi, {DestReg}, {Register(Mips::ZERO)})
MachineInstr *Inst =
B.buildInstr(Mips::ORi, {DestReg}, {Register(Mips::ZERO)})
.addImm(Imm.getLoBits(16).getLimitedValue());
return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI);
}
@ -151,7 +152,8 @@ bool MipsInstructionSelector::materialize32BitImm(Register DestReg, APInt Imm,
}
// ADDiu sign extends immediate. Used for values with 1s in high 17 bits.
if (Imm.isSignedIntN(16)) {
MachineInstr *Inst = B.buildInstr(Mips::ADDiu, {DestReg}, {Register(Mips::ZERO)})
MachineInstr *Inst =
B.buildInstr(Mips::ADDiu, {DestReg}, {Register(Mips::ZERO)})
.addImm(Imm.getLoBits(16).getLimitedValue());
return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI);
}

17
lib/Target/Mips/MipsSEISelDAGToDAG.cpp
View File

@ -234,8 +234,8 @@ void MipsSEDAGToDAGISel::selectAddE(SDNode *Node, const SDLoc &DL) const {
SDValue OuFlag = CurDAG->getTargetConstant(20, DL, MVT::i32);
SDNode *DSPCtrlField =
CurDAG->getMachineNode(Mips::RDDSP, DL, MVT::i32, MVT::Glue, CstOne, InFlag);
SDNode *DSPCtrlField = CurDAG->getMachineNode(Mips::RDDSP, DL, MVT::i32,
MVT::Glue, CstOne, InFlag);
SDNode *Carry = CurDAG->getMachineNode(
Mips::EXT, DL, MVT::i32, SDValue(DSPCtrlField, 0), OuFlag, CstOne);
@ -253,7 +253,8 @@ void MipsSEDAGToDAGISel::selectAddE(SDNode *Node, const SDLoc &DL) const {
SDValue Zero = CurDAG->getRegister(Mips::ZERO, MVT::i32);
SDValue InsOps[4] = {Zero, OuFlag, CstOne, SDValue(DSPCFWithCarry, 0)};
SDNode *DSPCtrlFinal = CurDAG->getMachineNode(Mips::INS, DL, MVT::i32, InsOps);
SDNode *DSPCtrlFinal =
CurDAG->getMachineNode(Mips::INS, DL, MVT::i32, InsOps);
SDNode *WrDSP = CurDAG->getMachineNode(Mips::WRDSP, DL, MVT::Glue,
SDValue(DSPCtrlFinal, 0), CstOne);
@ -1074,7 +1075,8 @@ bool MipsSEDAGToDAGISel::trySelect(SDNode *Node) {
Hi ? SDValue(Res, 0) : ZeroVal, LoVal);
assert((Hi || Lo) && "Zero case reached 32 bit case splat synthesis!");
Res = CurDAG->getMachineNode(Mips::FILL_W, DL, MVT::v4i32, SDValue(Res, 0));
Res =
CurDAG->getMachineNode(Mips::FILL_W, DL, MVT::v4i32, SDValue(Res, 0));
} else if (SplatValue.isSignedIntN(32) && SplatBitSize == 64 &&
(ABI.IsN32() || ABI.IsN64())) {
@ -1117,8 +1119,8 @@ bool MipsSEDAGToDAGISel::trySelect(SDNode *Node) {
// $res4 = insert.w $res3[1], $res fill.d $res
// splat.d $res4, 0
//
// The ability to use dinsu is guaranteed as MSA requires MIPSR5. This saves
// having to materialize the value by shifts and ors.
// The ability to use dinsu is guaranteed as MSA requires MIPSR5.
// This saves having to materialize the value by shifts and ors.
//
// FIXME: Implement the preferred sequence for MIPS64R6:
//
@ -1239,7 +1241,8 @@ bool MipsSEDAGToDAGISel::trySelect(SDNode *Node) {
llvm_unreachable(
"Zero splat value handled by non-zero 64bit splat synthesis!");
Res = CurDAG->getMachineNode(Mips::FILL_D, DL, MVT::v2i64, SDValue(Res, 0));
Res = CurDAG->getMachineNode(Mips::FILL_D, DL, MVT::v2i64,
SDValue(Res, 0));
} else
llvm_unreachable("Unknown ABI in MipsISelDAGToDAG!");