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[WebAssembly] Codegen for extmul SIMD instructions
Replace the clang builtins and LLVM intrinsics for the SIMD extmul instructions with normal codegen patterns. Differential Revision: https://reviews.llvm.org/D106724
This commit is contained in:
Thomas Lively
parent
2b967460b4
commit
bb4e957ebf
@ -162,23 +162,6 @@ def int_wasm_q15mulr_sat_signed :
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[llvm_v8i16_ty, llvm_v8i16_ty],
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[IntrNoMem, IntrSpeculatable]>;
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def int_wasm_extmul_low_signed :
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Intrinsic<[llvm_anyvector_ty],
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[LLVMSubdivide2VectorType<0>, LLVMSubdivide2VectorType<0>],
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[IntrNoMem, IntrSpeculatable]>;
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def int_wasm_extmul_high_signed :
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Intrinsic<[llvm_anyvector_ty],
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[LLVMSubdivide2VectorType<0>, LLVMSubdivide2VectorType<0>],
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[IntrNoMem, IntrSpeculatable]>;
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def int_wasm_extmul_low_unsigned :
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Intrinsic<[llvm_anyvector_ty],
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[LLVMSubdivide2VectorType<0>, LLVMSubdivide2VectorType<0>],
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[IntrNoMem, IntrSpeculatable]>;
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def int_wasm_extmul_high_unsigned :
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Intrinsic<[llvm_anyvector_ty],
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[LLVMSubdivide2VectorType<0>, LLVMSubdivide2VectorType<0>],
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[IntrNoMem, IntrSpeculatable]>;
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def int_wasm_extadd_pairwise_signed :
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Intrinsic<[llvm_anyvector_ty],
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[LLVMSubdivide2VectorType<0>],
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@ -1028,7 +1028,14 @@ defm DOT : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs), (outs), (ins),
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186>;
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// Extending multiplication: extmul_{low,high}_P, extmul_high
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multiclass SIMDExtBinary<Vec vec, Intrinsic node, string name, bits<32> simdop> {
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def extend_t : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>]>;
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def extend_low_s : SDNode<"WebAssemblyISD::EXTEND_LOW_S", extend_t>;
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def extend_high_s : SDNode<"WebAssemblyISD::EXTEND_HIGH_S", extend_t>;
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def extend_low_u : SDNode<"WebAssemblyISD::EXTEND_LOW_U", extend_t>;
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def extend_high_u : SDNode<"WebAssemblyISD::EXTEND_HIGH_U", extend_t>;
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multiclass SIMDExtBinary<Vec vec, SDPatternOperator node, string name,
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bits<32> simdop> {
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defm _#vec : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs),
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(outs), (ins),
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[(set (vec.vt V128:$dst), (node
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@ -1037,32 +1044,41 @@ multiclass SIMDExtBinary<Vec vec, Intrinsic node, string name, bits<32> simdop>
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vec.prefix#"."#name, simdop>;
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}
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defm EXTMUL_LOW_S :
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SIMDExtBinary<I16x8, int_wasm_extmul_low_signed, "extmul_low_i8x16_s", 0x9c>;
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defm EXTMUL_HIGH_S :
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SIMDExtBinary<I16x8, int_wasm_extmul_high_signed, "extmul_high_i8x16_s", 0x9d>;
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defm EXTMUL_LOW_U :
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SIMDExtBinary<I16x8, int_wasm_extmul_low_unsigned, "extmul_low_i8x16_u", 0x9e>;
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defm EXTMUL_HIGH_U :
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SIMDExtBinary<I16x8, int_wasm_extmul_high_unsigned, "extmul_high_i8x16_u", 0x9f>;
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class ExtMulPat<SDNode extend> :
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PatFrag<(ops node:$lhs, node:$rhs),
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(mul (extend $lhs), (extend $rhs))> {}
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def extmul_low_s : ExtMulPat<extend_low_s>;
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def extmul_high_s : ExtMulPat<extend_high_s>;
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def extmul_low_u : ExtMulPat<extend_low_u>;
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def extmul_high_u : ExtMulPat<extend_high_u>;
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defm EXTMUL_LOW_S :
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SIMDExtBinary<I32x4, int_wasm_extmul_low_signed, "extmul_low_i16x8_s", 0xbc>;
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SIMDExtBinary<I16x8, extmul_low_s, "extmul_low_i8x16_s", 0x9c>;
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defm EXTMUL_HIGH_S :
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SIMDExtBinary<I32x4, int_wasm_extmul_high_signed, "extmul_high_i16x8_s", 0xbd>;
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SIMDExtBinary<I16x8, extmul_high_s, "extmul_high_i8x16_s", 0x9d>;
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defm EXTMUL_LOW_U :
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SIMDExtBinary<I32x4, int_wasm_extmul_low_unsigned, "extmul_low_i16x8_u", 0xbe>;
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SIMDExtBinary<I16x8, extmul_low_u, "extmul_low_i8x16_u", 0x9e>;
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defm EXTMUL_HIGH_U :
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SIMDExtBinary<I32x4, int_wasm_extmul_high_unsigned, "extmul_high_i16x8_u", 0xbf>;
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SIMDExtBinary<I16x8, extmul_high_u, "extmul_high_i8x16_u", 0x9f>;
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defm EXTMUL_LOW_S :
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SIMDExtBinary<I64x2, int_wasm_extmul_low_signed, "extmul_low_i32x4_s", 0xdc>;
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SIMDExtBinary<I32x4, extmul_low_s, "extmul_low_i16x8_s", 0xbc>;
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defm EXTMUL_HIGH_S :
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SIMDExtBinary<I64x2, int_wasm_extmul_high_signed, "extmul_high_i32x4_s", 0xdd>;
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SIMDExtBinary<I32x4, extmul_high_s, "extmul_high_i16x8_s", 0xbd>;
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defm EXTMUL_LOW_U :
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SIMDExtBinary<I64x2, int_wasm_extmul_low_unsigned, "extmul_low_i32x4_u", 0xde>;
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SIMDExtBinary<I32x4, extmul_low_u, "extmul_low_i16x8_u", 0xbe>;
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defm EXTMUL_HIGH_U :
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SIMDExtBinary<I64x2, int_wasm_extmul_high_unsigned, "extmul_high_i32x4_u", 0xdf>;
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SIMDExtBinary<I32x4, extmul_high_u, "extmul_high_i16x8_u", 0xbf>;
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defm EXTMUL_LOW_S :
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SIMDExtBinary<I64x2, extmul_low_s, "extmul_low_i32x4_s", 0xdc>;
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defm EXTMUL_HIGH_S :
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SIMDExtBinary<I64x2, extmul_high_s, "extmul_high_i32x4_s", 0xdd>;
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defm EXTMUL_LOW_U :
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SIMDExtBinary<I64x2, extmul_low_u, "extmul_low_i32x4_u", 0xde>;
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defm EXTMUL_HIGH_U :
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SIMDExtBinary<I64x2, extmul_high_u, "extmul_high_i32x4_u", 0xdf>;
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//===----------------------------------------------------------------------===//
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// Floating-point unary arithmetic
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@ -1191,12 +1207,6 @@ defm "" : SIMDConvert<F64x2, I32x4, convert_low_s, "convert_low_i32x4_s", 0xfe>;
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defm "" : SIMDConvert<F64x2, I32x4, convert_low_u, "convert_low_i32x4_u", 0xff>;
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// Extending operations
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def extend_t : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>]>;
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def extend_low_s : SDNode<"WebAssemblyISD::EXTEND_LOW_S", extend_t>;
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def extend_high_s : SDNode<"WebAssemblyISD::EXTEND_HIGH_S", extend_t>;
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def extend_low_u : SDNode<"WebAssemblyISD::EXTEND_LOW_U", extend_t>;
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def extend_high_u : SDNode<"WebAssemblyISD::EXTEND_HIGH_U", extend_t>;
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// TODO: refactor this to be uniform for i64x2 if the numbering is not changed.
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multiclass SIMDExtend<Vec vec, bits<32> baseInst> {
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defm "" : SIMDConvert<vec, vec.split, extend_low_s,
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@ -659,6 +659,70 @@ define <8 x i16> @bitselect_v8i16(<8 x i16> %c, <8 x i16> %v1, <8 x i16> %v2) {
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ret <8 x i16> %a
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}
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; CHECK-LABEL: extmul_low_s_v8i16:
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; NO-SIMD128-NOT: i16x8
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; SIMD128-NEXT: .functype extmul_low_s_v8i16 (v128, v128) -> (v128){{$}}
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; SIMD128-SLOW-NEXT: i16x8.extmul_low_i8x16_s $push[[R:[0-9]+]]=, $0, $1{{$}}
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; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}}
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define <8 x i16> @extmul_low_s_v8i16(<16 x i8> %v1, <16 x i8> %v2) {
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%low1 = shufflevector <16 x i8> %v1, <16 x i8> undef,
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<8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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%low2 = shufflevector <16 x i8> %v2, <16 x i8> undef,
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<8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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%extended1 = sext <8 x i8> %low1 to <8 x i16>
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%extended2 = sext <8 x i8> %low2 to <8 x i16>
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%a = mul <8 x i16> %extended1, %extended2
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ret <8 x i16> %a
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}
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; CHECK-LABEL: extmul_high_s_v8i16:
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; NO-SIMD128-NOT: i16x8
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; SIMD128-NEXT: .functype extmul_high_s_v8i16 (v128, v128) -> (v128){{$}}
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; SIMD128-SLOW-NEXT: i16x8.extmul_high_i8x16_s $push[[R:[0-9]+]]=, $0, $1{{$}}
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; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}}
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define <8 x i16> @extmul_high_s_v8i16(<16 x i8> %v1, <16 x i8> %v2) {
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%high1 = shufflevector <16 x i8> %v1, <16 x i8> undef,
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<8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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%high2 = shufflevector <16 x i8> %v2, <16 x i8> undef,
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<8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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%extended1 = sext <8 x i8> %high1 to <8 x i16>
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%extended2 = sext <8 x i8> %high2 to <8 x i16>
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%a = mul <8 x i16> %extended1, %extended2
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ret <8 x i16> %a
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}
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; CHECK-LABEL: extmul_low_u_v8i16:
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; NO-SIMD128-NOT: i16x8
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; SIMD128-NEXT: .functype extmul_low_u_v8i16 (v128, v128) -> (v128){{$}}
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; SIMD128-SLOW-NEXT: i16x8.extmul_low_i8x16_u $push[[R:[0-9]+]]=, $0, $1{{$}}
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; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}}
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define <8 x i16> @extmul_low_u_v8i16(<16 x i8> %v1, <16 x i8> %v2) {
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%low1 = shufflevector <16 x i8> %v1, <16 x i8> undef,
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<8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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%low2 = shufflevector <16 x i8> %v2, <16 x i8> undef,
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<8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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%extended1 = zext <8 x i8> %low1 to <8 x i16>
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%extended2 = zext <8 x i8> %low2 to <8 x i16>
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%a = mul <8 x i16> %extended1, %extended2
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ret <8 x i16> %a
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}
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; CHECK-LABEL: extmul_high_u_v8i16:
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; NO-SIMD128-NOT: i16x8
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; SIMD128-NEXT: .functype extmul_high_u_v8i16 (v128, v128) -> (v128){{$}}
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; SIMD128-SLOW-NEXT: i16x8.extmul_high_i8x16_u $push[[R:[0-9]+]]=, $0, $1{{$}}
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; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}}
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define <8 x i16> @extmul_high_u_v8i16(<16 x i8> %v1, <16 x i8> %v2) {
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%high1 = shufflevector <16 x i8> %v1, <16 x i8> undef,
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<8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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%high2 = shufflevector <16 x i8> %v2, <16 x i8> undef,
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<8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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%extended1 = zext <8 x i8> %high1 to <8 x i16>
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%extended2 = zext <8 x i8> %high2 to <8 x i16>
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%a = mul <8 x i16> %extended1, %extended2
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ret <8 x i16> %a
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}
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; ==============================================================================
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; 4 x i32
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; ==============================================================================
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@ -934,6 +998,70 @@ define <4 x i32> @bitselect_v4i32(<4 x i32> %c, <4 x i32> %v1, <4 x i32> %v2) {
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ret <4 x i32> %a
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}
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; CHECK-LABEL: extmul_low_s_v4i32:
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; NO-SIMD128-NOT: i32x4
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; SIMD128-NEXT: .functype extmul_low_s_v4i32 (v128, v128) -> (v128){{$}}
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; SIMD128-SLOW-NEXT: i32x4.extmul_low_i16x8_s $push[[R:[0-9]+]]=, $0, $1{{$}}
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; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}}
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define <4 x i32> @extmul_low_s_v4i32(<8 x i16> %v1, <8 x i16> %v2) {
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%low1 = shufflevector <8 x i16> %v1, <8 x i16> undef,
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<4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%low2 = shufflevector <8 x i16> %v2, <8 x i16> undef,
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<4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%extended1 = sext <4 x i16> %low1 to <4 x i32>
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%extended2 = sext <4 x i16> %low2 to <4 x i32>
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%a = mul <4 x i32> %extended1, %extended2
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ret <4 x i32> %a
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}
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; CHECK-LABEL: extmul_high_s_v4i32:
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; NO-SIMD128-NOT: i32x4
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; SIMD128-NEXT: .functype extmul_high_s_v4i32 (v128, v128) -> (v128){{$}}
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; SIMD128-SLOW-NEXT: i32x4.extmul_high_i16x8_s $push[[R:[0-9]+]]=, $0, $1{{$}}
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; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}}
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define <4 x i32> @extmul_high_s_v4i32(<8 x i16> %v1, <8 x i16> %v2) {
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%high1 = shufflevector <8 x i16> %v1, <8 x i16> undef,
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<4 x i32> <i32 4, i32 5, i32 6, i32 7>
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%high2 = shufflevector <8 x i16> %v2, <8 x i16> undef,
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<4 x i32> <i32 4, i32 5, i32 6, i32 7>
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%extended1 = sext <4 x i16> %high1 to <4 x i32>
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%extended2 = sext <4 x i16> %high2 to <4 x i32>
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%a = mul <4 x i32> %extended1, %extended2
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ret <4 x i32> %a
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}
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; CHECK-LABEL: extmul_low_u_v4i32:
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; NO-SIMD128-NOT: i32x4
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; SIMD128-NEXT: .functype extmul_low_u_v4i32 (v128, v128) -> (v128){{$}}
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; SIMD128-SLOW-NEXT: i32x4.extmul_low_i16x8_u $push[[R:[0-9]+]]=, $0, $1{{$}}
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; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}}
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define <4 x i32> @extmul_low_u_v4i32(<8 x i16> %v1, <8 x i16> %v2) {
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%low1 = shufflevector <8 x i16> %v1, <8 x i16> undef,
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<4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%low2 = shufflevector <8 x i16> %v2, <8 x i16> undef,
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<4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%extended1 = zext <4 x i16> %low1 to <4 x i32>
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%extended2 = zext <4 x i16> %low2 to <4 x i32>
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%a = mul <4 x i32> %extended1, %extended2
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ret <4 x i32> %a
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}
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; CHECK-LABEL: extmul_high_u_v4i32:
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; NO-SIMD128-NOT: i32x4
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; SIMD128-NEXT: .functype extmul_high_u_v4i32 (v128, v128) -> (v128){{$}}
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; SIMD128-SLOW-NEXT: i32x4.extmul_high_i16x8_u $push[[R:[0-9]+]]=, $0, $1{{$}}
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; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}}
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define <4 x i32> @extmul_high_u_v4i32(<8 x i16> %v1, <8 x i16> %v2) {
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%high1 = shufflevector <8 x i16> %v1, <8 x i16> undef,
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<4 x i32> <i32 4, i32 5, i32 6, i32 7>
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%high2 = shufflevector <8 x i16> %v2, <8 x i16> undef,
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<4 x i32> <i32 4, i32 5, i32 6, i32 7>
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%extended1 = zext <4 x i16> %high1 to <4 x i32>
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%extended2 = zext <4 x i16> %high2 to <4 x i32>
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%a = mul <4 x i32> %extended1, %extended2
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ret <4 x i32> %a
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}
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; ==============================================================================
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; 2 x i64
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; ==============================================================================
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@ -1262,6 +1390,62 @@ define <2 x i64> @bitselect_v2i64(<2 x i64> %c, <2 x i64> %v1, <2 x i64> %v2) {
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ret <2 x i64> %a
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}
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; CHECK-LABEL: extmul_low_s_v2i64:
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; NO-SIMD128-NOT: i64x2
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; SIMD128-NEXT: .functype extmul_low_s_v2i64 (v128, v128) -> (v128){{$}}
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; SIMD128-SLOW-NEXT: i64x2.extmul_low_i32x4_s $push[[R:[0-9]+]]=, $0, $1{{$}}
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; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}}
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define <2 x i64> @extmul_low_s_v2i64(<4 x i32> %v1, <4 x i32> %v2) {
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%low1 = shufflevector <4 x i32> %v1, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
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%low2 = shufflevector <4 x i32> %v2, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
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%extended1 = sext <2 x i32> %low1 to <2 x i64>
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%extended2 = sext <2 x i32> %low2 to <2 x i64>
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%a = mul <2 x i64> %extended1, %extended2
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ret <2 x i64> %a
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}
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; CHECK-LABEL: extmul_high_s_v2i64:
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; NO-SIMD128-NOT: i64x2
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; SIMD128-NEXT: .functype extmul_high_s_v2i64 (v128, v128) -> (v128){{$}}
|
||||
; SIMD128-SLOW-NEXT: i64x2.extmul_high_i32x4_s $push[[R:[0-9]+]]=, $0, $1{{$}}
|
||||
; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}}
|
||||
define <2 x i64> @extmul_high_s_v2i64(<4 x i32> %v1, <4 x i32> %v2) {
|
||||
%high1 = shufflevector <4 x i32> %v1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
|
||||
%high2 = shufflevector <4 x i32> %v2, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
|
||||
%extended1 = sext <2 x i32> %high1 to <2 x i64>
|
||||
%extended2 = sext <2 x i32> %high2 to <2 x i64>
|
||||
%a = mul <2 x i64> %extended1, %extended2
|
||||
ret <2 x i64> %a
|
||||
}
|
||||
|
||||
; CHECK-LABEL: extmul_low_u_v2i64:
|
||||
; NO-SIMD128-NOT: i64x2
|
||||
; SIMD128-NEXT: .functype extmul_low_u_v2i64 (v128, v128) -> (v128){{$}}
|
||||
; SIMD128-SLOW-NEXT: i64x2.extmul_low_i32x4_u $push[[R:[0-9]+]]=, $0, $1{{$}}
|
||||
; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}}
|
||||
define <2 x i64> @extmul_low_u_v2i64(<4 x i32> %v1, <4 x i32> %v2) {
|
||||
%low1 = shufflevector <4 x i32> %v1, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
|
||||
%low2 = shufflevector <4 x i32> %v2, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
|
||||
%extended1 = zext <2 x i32> %low1 to <2 x i64>
|
||||
%extended2 = zext <2 x i32> %low2 to <2 x i64>
|
||||
%a = mul <2 x i64> %extended1, %extended2
|
||||
ret <2 x i64> %a
|
||||
}
|
||||
|
||||
; CHECK-LABEL: extmul_high_u_v2i64:
|
||||
; NO-SIMD128-NOT: i64x2
|
||||
; SIMD128-NEXT: .functype extmul_high_u_v2i64 (v128, v128) -> (v128){{$}}
|
||||
; SIMD128-SLOW-NEXT: i64x2.extmul_high_i32x4_u $push[[R:[0-9]+]]=, $0, $1{{$}}
|
||||
; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}}
|
||||
define <2 x i64> @extmul_high_u_v2i64(<4 x i32> %v1, <4 x i32> %v2) {
|
||||
%high1 = shufflevector <4 x i32> %v1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
|
||||
%high2 = shufflevector <4 x i32> %v2, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
|
||||
%extended1 = zext <2 x i32> %high1 to <2 x i64>
|
||||
%extended2 = zext <2 x i32> %high2 to <2 x i64>
|
||||
%a = mul <2 x i64> %extended1, %extended2
|
||||
ret <2 x i64> %a
|
||||
}
|
||||
|
||||
; ==============================================================================
|
||||
; 4 x float
|
||||
; ==============================================================================
|
||||
|
||||
@ -248,54 +248,6 @@ define <8 x i16> @q15mulr_sat_s_v8i16(<8 x i16> %x, <8 x i16> %y) {
|
||||
ret <8 x i16> %a
|
||||
}
|
||||
|
||||
; CHECK-LABEL: extmul_low_s_v8i16:
|
||||
; CHECK-NEXT: .functype extmul_low_s_v8i16 (v128, v128) -> (v128){{$}}
|
||||
; CHECK-NEXT: i16x8.extmul_low_i8x16_s $push[[R:[0-9]+]]=, $0, $1{{$}}
|
||||
; CHECK-NEXT: return $pop[[R]]{{$}}
|
||||
declare <8 x i16> @llvm.wasm.extmul.low.signed.v8i16(<16 x i8>, <16 x i8>)
|
||||
define <8 x i16> @extmul_low_s_v8i16(<16 x i8> %x, <16 x i8> %y) {
|
||||
%a = call <8 x i16> @llvm.wasm.extmul.low.signed.v8i16(
|
||||
<16 x i8> %x, <16 x i8> %y
|
||||
)
|
||||
ret <8 x i16> %a
|
||||
}
|
||||
|
||||
; CHECK-LABEL: extmul_high_s_v8i16:
|
||||
; CHECK-NEXT: .functype extmul_high_s_v8i16 (v128, v128) -> (v128){{$}}
|
||||
; CHECK-NEXT: i16x8.extmul_high_i8x16_s $push[[R:[0-9]+]]=, $0, $1{{$}}
|
||||
; CHECK-NEXT: return $pop[[R]]{{$}}
|
||||
declare <8 x i16> @llvm.wasm.extmul.high.signed.v8i16(<16 x i8>, <16 x i8>)
|
||||
define <8 x i16> @extmul_high_s_v8i16(<16 x i8> %x, <16 x i8> %y) {
|
||||
%a = call <8 x i16> @llvm.wasm.extmul.high.signed.v8i16(
|
||||
<16 x i8> %x, <16 x i8> %y
|
||||
)
|
||||
ret <8 x i16> %a
|
||||
}
|
||||
|
||||
; CHECK-LABEL: extmul_low_u_v8i16:
|
||||
; CHECK-NEXT: .functype extmul_low_u_v8i16 (v128, v128) -> (v128){{$}}
|
||||
; CHECK-NEXT: i16x8.extmul_low_i8x16_u $push[[R:[0-9]+]]=, $0, $1{{$}}
|
||||
; CHECK-NEXT: return $pop[[R]]{{$}}
|
||||
declare <8 x i16> @llvm.wasm.extmul.low.unsigned.v8i16(<16 x i8>, <16 x i8>)
|
||||
define <8 x i16> @extmul_low_u_v8i16(<16 x i8> %x, <16 x i8> %y) {
|
||||
%a = call <8 x i16> @llvm.wasm.extmul.low.unsigned.v8i16(
|
||||
<16 x i8> %x, <16 x i8> %y
|
||||
)
|
||||
ret <8 x i16> %a
|
||||
}
|
||||
|
||||
; CHECK-LABEL: extmul_high_u_v8i16:
|
||||
; CHECK-NEXT: .functype extmul_high_u_v8i16 (v128, v128) -> (v128){{$}}
|
||||
; CHECK-NEXT: i16x8.extmul_high_i8x16_u $push[[R:[0-9]+]]=, $0, $1{{$}}
|
||||
; CHECK-NEXT: return $pop[[R]]{{$}}
|
||||
declare <8 x i16> @llvm.wasm.extmul.high.unsigned.v8i16(<16 x i8>, <16 x i8>)
|
||||
define <8 x i16> @extmul_high_u_v8i16(<16 x i8> %x, <16 x i8> %y) {
|
||||
%a = call <8 x i16> @llvm.wasm.extmul.high.unsigned.v8i16(
|
||||
<16 x i8> %x, <16 x i8> %y
|
||||
)
|
||||
ret <8 x i16> %a
|
||||
}
|
||||
|
||||
; CHECK-LABEL: extadd_pairwise_s_v8i16:
|
||||
; CHECK-NEXT: .functype extadd_pairwise_s_v8i16 (v128) -> (v128){{$}}
|
||||
; CHECK-NEXT: i16x8.extadd_pairwise_i8x16_s $push[[R:[0-9]+]]=, $0{{$}}
|
||||
@ -395,55 +347,6 @@ define <4 x i32> @dot(<8 x i16> %x, <8 x i16> %y) {
|
||||
ret <4 x i32> %a
|
||||
}
|
||||
|
||||
|
||||
; CHECK-LABEL: extmul_low_s_v4i32:
|
||||
; CHECK-NEXT: .functype extmul_low_s_v4i32 (v128, v128) -> (v128){{$}}
|
||||
; CHECK-NEXT: i32x4.extmul_low_i16x8_s $push[[R:[0-9]+]]=, $0, $1{{$}}
|
||||
; CHECK-NEXT: return $pop[[R]]{{$}}
|
||||
declare <4 x i32> @llvm.wasm.extmul.low.signed.v4i32(<8 x i16>, <8 x i16>)
|
||||
define <4 x i32> @extmul_low_s_v4i32(<8 x i16> %x, <8 x i16> %y) {
|
||||
%a = call <4 x i32> @llvm.wasm.extmul.low.signed.v4i32(
|
||||
<8 x i16> %x, <8 x i16> %y
|
||||
)
|
||||
ret <4 x i32> %a
|
||||
}
|
||||
|
||||
; CHECK-LABEL: extmul_high_s_v4i32:
|
||||
; CHECK-NEXT: .functype extmul_high_s_v4i32 (v128, v128) -> (v128){{$}}
|
||||
; CHECK-NEXT: i32x4.extmul_high_i16x8_s $push[[R:[0-9]+]]=, $0, $1{{$}}
|
||||
; CHECK-NEXT: return $pop[[R]]{{$}}
|
||||
declare <4 x i32> @llvm.wasm.extmul.high.signed.v4i32(<8 x i16>, <8 x i16>)
|
||||
define <4 x i32> @extmul_high_s_v4i32(<8 x i16> %x, <8 x i16> %y) {
|
||||
%a = call <4 x i32> @llvm.wasm.extmul.high.signed.v4i32(
|
||||
<8 x i16> %x, <8 x i16> %y
|
||||
)
|
||||
ret <4 x i32> %a
|
||||
}
|
||||
|
||||
; CHECK-LABEL: extmul_low_u_v4i32:
|
||||
; CHECK-NEXT: .functype extmul_low_u_v4i32 (v128, v128) -> (v128){{$}}
|
||||
; CHECK-NEXT: i32x4.extmul_low_i16x8_u $push[[R:[0-9]+]]=, $0, $1{{$}}
|
||||
; CHECK-NEXT: return $pop[[R]]{{$}}
|
||||
declare <4 x i32> @llvm.wasm.extmul.low.unsigned.v4i32(<8 x i16>, <8 x i16>)
|
||||
define <4 x i32> @extmul_low_u_v4i32(<8 x i16> %x, <8 x i16> %y) {
|
||||
%a = call <4 x i32> @llvm.wasm.extmul.low.unsigned.v4i32(
|
||||
<8 x i16> %x, <8 x i16> %y
|
||||
)
|
||||
ret <4 x i32> %a
|
||||
}
|
||||
|
||||
; CHECK-LABEL: extmul_high_u_v4i32:
|
||||
; CHECK-NEXT: .functype extmul_high_u_v4i32 (v128, v128) -> (v128){{$}}
|
||||
; CHECK-NEXT: i32x4.extmul_high_i16x8_u $push[[R:[0-9]+]]=, $0, $1{{$}}
|
||||
; CHECK-NEXT: return $pop[[R]]{{$}}
|
||||
declare <4 x i32> @llvm.wasm.extmul.high.unsigned.v4i32(<8 x i16>, <8 x i16>)
|
||||
define <4 x i32> @extmul_high_u_v4i32(<8 x i16> %x, <8 x i16> %y) {
|
||||
%a = call <4 x i32> @llvm.wasm.extmul.high.unsigned.v4i32(
|
||||
<8 x i16> %x, <8 x i16> %y
|
||||
)
|
||||
ret <4 x i32> %a
|
||||
}
|
||||
|
||||
; CHECK-LABEL: extadd_pairwise_s_v4i32:
|
||||
; CHECK-NEXT: .functype extadd_pairwise_s_v4i32 (v128) -> (v128){{$}}
|
||||
; CHECK-NEXT: i32x4.extadd_pairwise_i16x8_s $push[[R:[0-9]+]]=, $0{{$}}
|
||||
@ -580,54 +483,6 @@ define <4 x i32> @trunc_sat_zero_u_v4i32_2(<2 x double> %x) {
|
||||
; ==============================================================================
|
||||
; 2 x i64
|
||||
; ==============================================================================
|
||||
; CHECK-LABEL: extmul_low_s_v2i64:
|
||||
; CHECK-NEXT: .functype extmul_low_s_v2i64 (v128, v128) -> (v128){{$}}
|
||||
; CHECK-NEXT: i64x2.extmul_low_i32x4_s $push[[R:[0-9]+]]=, $0, $1{{$}}
|
||||
; CHECK-NEXT: return $pop[[R]]{{$}}
|
||||
declare <2 x i64> @llvm.wasm.extmul.low.signed.v2i64(<4 x i32>, <4 x i32>)
|
||||
define <2 x i64> @extmul_low_s_v2i64(<4 x i32> %x, <4 x i32> %y) {
|
||||
%a = call <2 x i64> @llvm.wasm.extmul.low.signed.v2i64(
|
||||
<4 x i32> %x, <4 x i32> %y
|
||||
)
|
||||
ret <2 x i64> %a
|
||||
}
|
||||
|
||||
; CHECK-LABEL: extmul_high_s_v2i64:
|
||||
; CHECK-NEXT: .functype extmul_high_s_v2i64 (v128, v128) -> (v128){{$}}
|
||||
; CHECK-NEXT: i64x2.extmul_high_i32x4_s $push[[R:[0-9]+]]=, $0, $1{{$}}
|
||||
; CHECK-NEXT: return $pop[[R]]{{$}}
|
||||
declare <2 x i64> @llvm.wasm.extmul.high.signed.v2i64(<4 x i32>, <4 x i32>)
|
||||
define <2 x i64> @extmul_high_s_v2i64(<4 x i32> %x, <4 x i32> %y) {
|
||||
%a = call <2 x i64> @llvm.wasm.extmul.high.signed.v2i64(
|
||||
<4 x i32> %x, <4 x i32> %y
|
||||
)
|
||||
ret <2 x i64> %a
|
||||
}
|
||||
|
||||
; CHECK-LABEL: extmul_low_u_v2i64:
|
||||
; CHECK-NEXT: .functype extmul_low_u_v2i64 (v128, v128) -> (v128){{$}}
|
||||
; CHECK-NEXT: i64x2.extmul_low_i32x4_u $push[[R:[0-9]+]]=, $0, $1{{$}}
|
||||
; CHECK-NEXT: return $pop[[R]]{{$}}
|
||||
declare <2 x i64> @llvm.wasm.extmul.low.unsigned.v2i64(<4 x i32>, <4 x i32>)
|
||||
define <2 x i64> @extmul_low_u_v2i64(<4 x i32> %x, <4 x i32> %y) {
|
||||
%a = call <2 x i64> @llvm.wasm.extmul.low.unsigned.v2i64(
|
||||
<4 x i32> %x, <4 x i32> %y
|
||||
)
|
||||
ret <2 x i64> %a
|
||||
}
|
||||
|
||||
; CHECK-LABEL: extmul_high_u_v2i64:
|
||||
; CHECK-NEXT: .functype extmul_high_u_v2i64 (v128, v128) -> (v128){{$}}
|
||||
; CHECK-NEXT: i64x2.extmul_high_i32x4_u $push[[R:[0-9]+]]=, $0, $1{{$}}
|
||||
; CHECK-NEXT: return $pop[[R]]{{$}}
|
||||
declare <2 x i64> @llvm.wasm.extmul.high.unsigned.v2i64(<4 x i32>, <4 x i32>)
|
||||
define <2 x i64> @extmul_high_u_v2i64(<4 x i32> %x, <4 x i32> %y) {
|
||||
%a = call <2 x i64> @llvm.wasm.extmul.high.unsigned.v2i64(
|
||||
<4 x i32> %x, <4 x i32> %y
|
||||
)
|
||||
ret <2 x i64> %a
|
||||
}
|
||||
|
||||
; CHECK-LABEL: any_v2i64:
|
||||
; CHECK-NEXT: .functype any_v2i64 (v128) -> (i32){{$}}
|
||||
; CHECK-NEXT: v128.any_true $push[[R:[0-9]+]]=, $0{{$}}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user