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test: clean up some of the RISCV tests (NFC)

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This addresses some post-commit comments from jrtc27 to make the tests
easier to process.
This commit is contained in:
Saleem Abdulrasool 2021-06-17 16:48:51 +00:00 committed by Saleem Abdulrasool
parent e76e730b8f
commit bb616e9e7a
2 changed files with 15 additions and 17 deletions
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22
test/CodeGen/RISCV/fixups-diff.ll
View File

@ -22,18 +22,18 @@ entry:
ret i32 0
}
; CHECK: Section {{.*}} .rela.debug_info {
; CHECK: 0x22 R_RISCV_ADD32 - 0x0
; CHECK-NEXT: 0x22 R_RISCV_SUB32 - 0x0
; CHECK: 0x2B R_RISCV_ADD32 - 0x0
; CHECK-NEXT: 0x2B R_RISCV_SUB32 - 0x0
; CHECK: }
; CHECK: Section {{.*}} .rela.debug_info {
; CHECK: 0x22 R_RISCV_ADD32 - 0x0
; CHECK-NEXT: 0x22 R_RISCV_SUB32 - 0x0
; CHECK: 0x2B R_RISCV_ADD32 - 0x0
; CHECK-NEXT: 0x2B R_RISCV_SUB32 - 0x0
; CHECK: }
; CHECK: Section {{.*}} .rela.eh_frame {
; CHECK: 0x1C R_RISCV_32_PCREL - 0x0
; CHECK: 0x20 R_RISCV_ADD32 - 0x0
; CHECK-NEXT: 0x20 R_RISCV_SUB32 - 0x0
; CHECK: }
; CHECK: Section {{.*}} .rela.eh_frame {
; CHECK: 0x1C R_RISCV_32_PCREL - 0x0
; CHECK: 0x20 R_RISCV_ADD32 - 0x0
; CHECK-NEXT: 0x20 R_RISCV_SUB32 - 0x0
; CHECK: }
!llvm.dbg.cu = !{!0}
!llvm.module.flags = !{!3, !4, !5}

10
test/CodeGen/RISCV/fixups-relax-diff.ll
View File

@ -1,7 +1,5 @@
; RUN: llc -filetype=obj -mtriple=riscv32 -mattr=+relax %s -o - \
; RUN: | llvm-readobj -r - | FileCheck -check-prefix=RELAX %s
; RUN: llc -filetype=obj -mtriple=riscv32 -mattr=-relax %s -o - \
; RUN: | llvm-readobj -r - | FileCheck -check-prefix=RELAX %s
; RUN: llc -filetype=obj -mtriple=riscv32 -mattr=+relax %s -o - | llvm-readobj -r - | FileCheck %s
; RUN: llc -filetype=obj -mtriple=riscv32 -mattr=-relax %s -o - | llvm-readobj -r - | FileCheck %s
; This test checks that a diff inserted via inline assembly always causes
; relocations. This isn't an assembly test as the assembler takes a different
@ -11,8 +9,8 @@ define i32 @main() nounwind {
entry:
%retval = alloca i32, align 4
store i32 0, i32* %retval, align 4
; RELAX: R_RISCV_ADD64 b
; RELAX: R_RISCV_SUB64 a
; CHECK: R_RISCV_ADD64 b
; CHECK-NEXT: R_RISCV_SUB64 a
call void asm sideeffect "a:\0Ab:\0A.dword b-a", ""()
ret i32 0
}