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[MSP430] Optimize 'shl x, 8[+ N] -> swpb(zext(x)) [<< N]' for i16

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Perform additional simplification to reduce shift amount.

Patch by Kristina Bessonova!

Differential Revision: https://reviews.llvm.org/D56016

llvm-svn: 350712
This commit is contained in:
Anton Korobeynikov 2019-01-09 13:03:01 +00:00
parent 8e2314675c
commit bb91cffa5a
2 changed files with 29 additions and 7 deletions
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25
lib/Target/MSP430/MSP430ISelLowering.cpp
View File

@ -954,15 +954,26 @@ SDValue MSP430TargetLowering::LowerShifts(SDValue Op,
// Expand the stuff into sequence of shifts.
SDValue Victim = N->getOperand(0);
if ((Opc == ISD::SRA || Opc == ISD::SRL) && ShiftAmount >= 8) {
// foo >> (8 + N) => sxt(swpb(foo)) >> N
if (ShiftAmount >= 8) {
assert(VT == MVT::i16 && "Can not shift i8 by 8 and more");
Victim = DAG.getNode(ISD::BSWAP, dl, VT, Victim);
if (Opc == ISD::SRA)
Victim = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT, Victim,
DAG.getValueType(MVT::i8));
else
switch(Opc) {
default:
llvm_unreachable("Unknown shift");
case ISD::SHL:
// foo << (8 + N) => swpb(zext(foo)) << N
Victim = DAG.getZeroExtendInReg(Victim, dl, MVT::i8);
Victim = DAG.getNode(ISD::BSWAP, dl, VT, Victim);
break;
case ISD::SRA:
case ISD::SRL:
// foo >> (8 + N) => sxt(swpb(foo)) >> N
Victim = DAG.getNode(ISD::BSWAP, dl, VT, Victim);
Victim = (Opc == ISD::SRA)
? DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT, Victim,
DAG.getValueType(MVT::i8))
: DAG.getZeroExtendInReg(Victim, dl, MVT::i8);
break;
}
ShiftAmount -= 8;
}

11
test/CodeGen/MSP430/shifts.ll
View File

@ -74,3 +74,14 @@ entry:
%shr = lshr i16 %a, 10
ret i16 %shr
}
define i16 @lshl10_i16(i16 %a) #0 {
entry:
; CHECK-LABEL: lshl10_i16:
; CHECK: mov.b r12, r12
; CHECK-NEXT: swpb r12
; CHECK-NEXT: add r12, r12
; CHECK-NEXT: add r12, r12
%shl = shl i16 %a, 10
ret i16 %shl
}