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https://github.com/RPCS3/llvm-mirror.git
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[MCA] Further refactor the bottleneck analysis view. NFCI.
llvm-svn: 362933
This commit is contained in:
Andrea Di Biagio
parent
5ce0272690
commit
bb92764db4
@ -198,7 +198,8 @@ InstRef Scheduler::select() {
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Strategy->compare(IR, ReadySet[QueueIndex])) {
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Instruction &IS = *IR.getInstruction();
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uint64_t BusyResourceMask = Resources->checkAvailability(IS.getDesc());
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IS.setCriticalResourceMask(BusyResourceMask);
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if (BusyResourceMask)
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IS.setCriticalResourceMask(BusyResourceMask);
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BusyResourceUnits |= BusyResourceMask;
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if (!BusyResourceMask)
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QueueIndex = I;
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@ -13,6 +13,7 @@
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//===----------------------------------------------------------------------===//
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#include "Views/BottleneckAnalysis.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MCA/Support.h"
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#include "llvm/Support/Format.h"
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@ -40,43 +41,38 @@ PressureTracker::PressureTracker(const MCSchedModel &Model)
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}
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ResourceUsers.resize(NextResourceUsersIdx);
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std::fill(ResourceUsers.begin(), ResourceUsers.end(), ~0U);
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std::fill(ResourceUsers.begin(), ResourceUsers.end(),
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std::make_pair<unsigned, unsigned>(~0U, 0U));
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}
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void PressureTracker::getUniqueUsers(
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uint64_t ResourceMask, SmallVectorImpl<unsigned> &UniqueUsers) const {
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void PressureTracker::getResourceUsers(uint64_t ResourceMask,
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SmallVectorImpl<User> &Users) const {
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unsigned Index = getResourceStateIndex(ResourceMask);
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unsigned ProcResID = ResIdx2ProcResID[Index];
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const MCProcResourceDesc &PRDesc = *SM.getProcResource(ProcResID);
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for (unsigned I = 0, E = PRDesc.NumUnits; I < E; ++I) {
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unsigned From = getResourceUser(ProcResID, I);
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if (find(UniqueUsers, From) == UniqueUsers.end())
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UniqueUsers.emplace_back(From);
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const User U = getResourceUser(ProcResID, I);
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if (U.second && IPI.find(U.first) != IPI.end())
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Users.emplace_back(U);
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}
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}
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void PressureTracker::handleInstructionEvent(const HWInstructionEvent &Event) {
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void PressureTracker::onInstructionDispatched(unsigned IID) {
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IPI.insert(std::make_pair(IID, InstructionPressureInfo()));
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}
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void PressureTracker::onInstructionExecuted(unsigned IID) { IPI.erase(IID); }
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void PressureTracker::handleInstructionIssuedEvent(
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const HWInstructionIssuedEvent &Event) {
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unsigned IID = Event.IR.getSourceIndex();
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switch (Event.Type) {
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default:
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break;
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case HWInstructionEvent::Dispatched:
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IPI.insert(std::make_pair(IID, InstructionPressureInfo()));
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break;
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case HWInstructionEvent::Executed:
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IPI.erase(IID);
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break;
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case HWInstructionEvent::Issued: {
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const auto &IIE = static_cast<const HWInstructionIssuedEvent &>(Event);
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using ResourceRef = HWInstructionIssuedEvent::ResourceRef;
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using ResourceUse = std::pair<ResourceRef, ResourceCycles>;
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for (const ResourceUse &Use : IIE.UsedResources) {
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const ResourceRef &RR = Use.first;
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unsigned Index = ProcResID2ResourceUsersIndex[RR.first];
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Index += countTrailingZeros(RR.second);
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ResourceUsers[Index] = IID;
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}
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}
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using ResourceRef = HWInstructionIssuedEvent::ResourceRef;
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using ResourceUse = std::pair<ResourceRef, ResourceCycles>;
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for (const ResourceUse &Use : Event.UsedResources) {
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const ResourceRef &RR = Use.first;
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unsigned Index = ProcResID2ResourceUsersIndex[RR.first];
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Index += countTrailingZeros(RR.second);
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ResourceUsers[Index] = std::make_pair(IID, Use.second.getNumerator());
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}
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}
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@ -125,7 +121,8 @@ void PressureTracker::handlePressureEvent(const HWPressureEvent &Event) {
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if (!BusyResources)
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continue;
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IPI[IR.getSourceIndex()].ResourcePressureCycles++;
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unsigned IID = IR.getSourceIndex();
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IPI[IID].ResourcePressureCycles++;
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}
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break;
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}
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@ -146,51 +143,59 @@ void PressureTracker::handlePressureEvent(const HWPressureEvent &Event) {
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}
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#ifndef NDEBUG
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void DependencyGraph::dumpRegDeps(raw_ostream &OS, MCInstPrinter &MCIP) const {
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void DependencyGraph::dumpDependencyEdge(raw_ostream &OS, unsigned FromIID,
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const DependencyEdge &DE,
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MCInstPrinter &MCIP) const {
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bool LoopCarried = FromIID >= DE.IID;
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OS << " FROM: " << FromIID << " TO: " << DE.IID
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<< (LoopCarried ? " (loop carried)" : " ");
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if (DE.Type == DT_REGISTER) {
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OS << " - REGISTER: ";
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MCIP.printRegName(OS, DE.ResourceOrRegID);
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} else if (DE.Type == DT_MEMORY) {
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OS << " - MEMORY";
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} else {
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assert(DE.Type == DT_RESOURCE && "Unexpected unsupported dependency type!");
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OS << " - RESOURCE MASK: " << DE.ResourceOrRegID;
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}
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OS << " - CYCLES: " << DE.Cycles << '\n';
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}
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void DependencyGraph::dump(raw_ostream &OS, MCInstPrinter &MCIP) const {
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OS << "\nREG DEPS\n";
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for (unsigned I = 0, E = Nodes.size(); I < E; ++I) {
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const DGNode &Node = Nodes[I];
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for (const DependencyEdge &DE : Node.RegDeps) {
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bool LoopCarried = I >= DE.IID;
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OS << " FROM: " << I << " TO: " << DE.IID
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<< (LoopCarried ? " (loop carried)" : " ")
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<< " - REGISTER: ";
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MCIP.printRegName(OS, DE.ResourceOrRegID);
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OS << " - CYCLES: " << DE.Cycles << '\n';
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for (const DependencyEdge &DE : Node.OutgoingEdges) {
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if (DE.Type == DT_REGISTER)
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dumpDependencyEdge(OS, I, DE, MCIP);
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}
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}
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}
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void DependencyGraph::dumpMemDeps(raw_ostream &OS) const {
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OS << "\nMEM DEPS\n";
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for (unsigned I = 0, E = Nodes.size(); I < E; ++I) {
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const DGNode &Node = Nodes[I];
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for (const DependencyEdge &DE : Node.MemDeps) {
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bool LoopCarried = I >= DE.IID;
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OS << " FROM: " << I << " TO: " << DE.IID
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<< (LoopCarried ? " (loop carried)" : " ")
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<< " - MEMORY - CYCLES: " << DE.Cycles << '\n';
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for (const DependencyEdge &DE : Node.OutgoingEdges) {
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if (DE.Type == DT_MEMORY)
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dumpDependencyEdge(OS, I, DE, MCIP);
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}
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}
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}
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void DependencyGraph::dumpResDeps(raw_ostream &OS) const {
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OS << "\nRESOURCE DEPS\n";
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for (unsigned I = 0, E = Nodes.size(); I < E; ++I) {
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const DGNode &Node = Nodes[I];
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for (const DependencyEdge &DE : Node.ResDeps) {
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bool LoopCarried = I >= DE.IID;
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OS << " FROM: " << I << " TO: " << DE.IID
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<< (LoopCarried ? "(loop carried)" : " ")
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<< " - RESOURCE MASK: " << DE.ResourceOrRegID;
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OS << " - CYCLES: " << DE.Cycles << '\n';
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for (const DependencyEdge &DE : Node.OutgoingEdges) {
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if (DE.Type == DT_RESOURCE)
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dumpDependencyEdge(OS, I, DE, MCIP);
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}
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}
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}
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#endif // NDEBUG
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void DependencyGraph::addDepImpl(SmallVectorImpl<DependencyEdge> &Vec,
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DependencyEdge &&Dep) {
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void DependencyGraph::addDependency(unsigned From, DependencyEdge &&Dep) {
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DGNode &NodeFrom = Nodes[From];
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DGNode &NodeTo = Nodes[Dep.IID];
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SmallVectorImpl<DependencyEdge> &Vec = NodeFrom.OutgoingEdges;
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auto It = find_if(Vec, [Dep](DependencyEdge &DE) {
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return DE.IID == Dep.IID && DE.ResourceOrRegID == Dep.ResourceOrRegID;
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});
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@ -201,38 +206,102 @@ void DependencyGraph::addDepImpl(SmallVectorImpl<DependencyEdge> &Vec,
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}
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Vec.emplace_back(Dep);
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Nodes[Dep.IID].NumPredecessors++;
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NodeTo.NumPredecessors++;
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}
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BottleneckAnalysis::BottleneckAnalysis(const MCSubtargetInfo &sti,
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ArrayRef<MCInst> Sequence)
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: STI(sti), Tracker(STI.getSchedModel()), DG(Sequence.size()),
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Source(Sequence), TotalCycles(0),
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PressureIncreasedBecauseOfResources(false),
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MCInstPrinter &Printer,
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ArrayRef<MCInst> S)
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: STI(sti), MCIP(Printer), Tracker(STI.getSchedModel()), DG(S.size() * 3),
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Source(S), TotalCycles(0), PressureIncreasedBecauseOfResources(false),
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PressureIncreasedBecauseOfRegisterDependencies(false),
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PressureIncreasedBecauseOfMemoryDependencies(false),
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SeenStallCycles(false), BPI() {}
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void BottleneckAnalysis::addRegisterDep(unsigned From, unsigned To,
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unsigned RegID, unsigned Cy) {
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bool IsLoopCarried = From >= To;
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unsigned SourceSize = Source.size();
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if (IsLoopCarried) {
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DG.addRegisterDep(From, To + SourceSize, RegID, Cy);
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DG.addRegisterDep(From + SourceSize, To + (SourceSize * 2), RegID, Cy);
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return;
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}
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DG.addRegisterDep(From + SourceSize, To + SourceSize, RegID, Cy);
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}
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void BottleneckAnalysis::addMemoryDep(unsigned From, unsigned To, unsigned Cy) {
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bool IsLoopCarried = From >= To;
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unsigned SourceSize = Source.size();
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if (IsLoopCarried) {
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DG.addMemoryDep(From, To + SourceSize, Cy);
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DG.addMemoryDep(From + SourceSize, To + (SourceSize * 2), Cy);
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return;
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}
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DG.addMemoryDep(From + SourceSize, To + SourceSize, Cy);
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}
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void BottleneckAnalysis::addResourceDep(unsigned From, unsigned To,
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uint64_t Mask, unsigned Cy) {
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bool IsLoopCarried = From >= To;
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unsigned SourceSize = Source.size();
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if (IsLoopCarried) {
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DG.addResourceDep(From, To + SourceSize, Mask, Cy);
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DG.addResourceDep(From + SourceSize, To + (SourceSize * 2), Mask, Cy);
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return;
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}
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DG.addResourceDep(From + SourceSize, To + SourceSize, Mask, Cy);
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}
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void BottleneckAnalysis::onEvent(const HWInstructionEvent &Event) {
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Tracker.handleInstructionEvent(Event);
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const unsigned IID = Event.IR.getSourceIndex();
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if (Event.Type == HWInstructionEvent::Dispatched) {
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Tracker.onInstructionDispatched(IID);
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return;
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}
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if (Event.Type == HWInstructionEvent::Executed) {
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Tracker.onInstructionExecuted(IID);
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return;
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}
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if (Event.Type != HWInstructionEvent::Issued)
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return;
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const unsigned IID = Event.IR.getSourceIndex();
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const Instruction &IS = *Event.IR.getInstruction();
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unsigned Cycles = Tracker.getRegisterPressureCycles(IID);
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unsigned To = IID % Source.size();
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unsigned Cycles = Tracker.getResourcePressureCycles(IID);
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if (Cycles) {
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uint64_t ResourceMask = IS.getCriticalResourceMask();
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SmallVector<std::pair<unsigned, unsigned>, 4> Users;
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while (ResourceMask) {
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uint64_t Current = ResourceMask & (-ResourceMask);
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Tracker.getResourceUsers(Current, Users);
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for (const std::pair<unsigned, unsigned> &U : Users) {
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unsigned Cost = std::min(U.second, Cycles);
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addResourceDep(U.first % Source.size(), To, Current, Cost);
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}
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Users.clear();
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ResourceMask ^= Current;
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}
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}
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Cycles = Tracker.getRegisterPressureCycles(IID);
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if (Cycles) {
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const CriticalDependency &RegDep = IS.getCriticalRegDep();
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unsigned From = RegDep.IID % Source.size();
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DG.addRegDep(From, To, RegDep.RegID, Cycles);
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addRegisterDep(From, To, RegDep.RegID, Cycles);
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}
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Cycles = Tracker.getMemoryPressureCycles(IID);
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if (Cycles) {
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const CriticalDependency &MemDep = IS.getCriticalMemDep();
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unsigned From = MemDep.IID % Source.size();
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DG.addMemDep(From, To, Cycles);
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addMemoryDep(From, To, Cycles);
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}
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Tracker.handleInstructionIssuedEvent(
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static_cast<const HWInstructionIssuedEvent &>(Event));
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}
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void BottleneckAnalysis::onEvent(const HWPressureEvent &Event) {
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@ -245,28 +314,9 @@ void BottleneckAnalysis::onEvent(const HWPressureEvent &Event) {
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default:
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break;
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case HWPressureEvent::RESOURCES: {
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case HWPressureEvent::RESOURCES:
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PressureIncreasedBecauseOfResources = true;
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SmallVector<unsigned, 4> UniqueUsers;
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for (const InstRef &IR : Event.AffectedInstructions) {
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const Instruction &IS = *IR.getInstruction();
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unsigned To = IR.getSourceIndex() % Source.size();
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unsigned BusyResources =
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IS.getCriticalResourceMask() & Event.ResourceMask;
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while (BusyResources) {
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uint64_t Current = BusyResources & (-BusyResources);
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Tracker.getUniqueUsers(Current, UniqueUsers);
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for (unsigned User : UniqueUsers)
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DG.addResourceDep(User % Source.size(), To, Current, 1);
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BusyResources ^= Current;
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}
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UniqueUsers.clear();
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}
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break;
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}
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case HWPressureEvent::REGISTER_DEPS:
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PressureIncreasedBecauseOfRegisterDependencies = true;
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break;
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@ -63,7 +63,8 @@ class PressureTracker {
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// There is one entry for every processor resource unit declared by the
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// processor model. An all_ones value is treated like an invalid instruction
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// identifier.
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SmallVector<unsigned, 4> ResourceUsers;
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using User = std::pair<unsigned, unsigned>;
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SmallVector<User, 4> ResourceUsers;
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struct InstructionPressureInfo {
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unsigned RegisterPressureCycles;
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@ -74,7 +75,7 @@ class PressureTracker {
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void updateResourcePressureDistribution(uint64_t CumulativeMask);
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unsigned getResourceUser(unsigned ProcResID, unsigned UnitID) const {
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User getResourceUser(unsigned ProcResID, unsigned UnitID) const {
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unsigned Index = ProcResID2ResourceUsersIndex[ProcResID];
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return ResourceUsers[Index + UnitID];
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}
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@ -86,8 +87,8 @@ public:
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return ResourcePressureDistribution;
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}
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void getUniqueUsers(uint64_t ResourceMask,
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SmallVectorImpl<unsigned> &Users) const;
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void getResourceUsers(uint64_t ResourceMask,
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SmallVectorImpl<User> &Users) const;
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unsigned getRegisterPressureCycles(unsigned IID) const {
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assert(IPI.find(IID) != IPI.end() && "Instruction is not tracked!");
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@ -107,12 +108,18 @@ public:
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return Info.ResourcePressureCycles;
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}
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void onInstructionDispatched(unsigned IID);
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void onInstructionExecuted(unsigned IID);
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void handlePressureEvent(const HWPressureEvent &Event);
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void handleInstructionEvent(const HWInstructionEvent &Event);
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void handleInstructionIssuedEvent(const HWInstructionIssuedEvent &Event);
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};
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class DependencyGraph {
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enum DependencyType { DT_REGISTER, DT_MEMORY, DT_RESOURCE };
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struct DependencyEdge {
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DependencyType Type;
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unsigned IID;
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uint64_t ResourceOrRegID;
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uint64_t Cycles;
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@ -120,46 +127,44 @@ class DependencyGraph {
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struct DGNode {
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unsigned NumPredecessors;
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SmallVector<DependencyEdge, 8> RegDeps;
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SmallVector<DependencyEdge, 8> MemDeps;
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SmallVector<DependencyEdge, 8> ResDeps;
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SmallVector<DependencyEdge, 8> OutgoingEdges;
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};
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SmallVector<DGNode, 16> Nodes;
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void addDepImpl(SmallVectorImpl<DependencyEdge> &Vec, DependencyEdge &&DE);
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DependencyGraph(const DependencyGraph &) = delete;
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DependencyGraph &operator=(const DependencyGraph &) = delete;
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public:
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DependencyGraph(unsigned NumNodes) : Nodes(NumNodes, DGNode()) {}
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void addDependency(unsigned From, DependencyEdge &&DE);
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void addRegDep(unsigned From, unsigned To, unsigned RegID, unsigned Cy) {
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addDepImpl(Nodes[From].RegDeps, {To, RegID, Cy});
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#ifndef NDEBUG
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void dumpDependencyEdge(raw_ostream &OS, unsigned FromIID,
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const DependencyEdge &DE, MCInstPrinter &MCIP) const;
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#endif
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public:
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DependencyGraph(unsigned Size) : Nodes(Size) {}
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void addRegisterDep(unsigned From, unsigned To, unsigned RegID, unsigned Cy) {
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addDependency(From, {DT_REGISTER, To, RegID, Cy});
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}
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void addMemDep(unsigned From, unsigned To, unsigned Cy) {
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addDepImpl(Nodes[From].MemDeps, {To, /* unused */ 0, Cy});
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void addMemoryDep(unsigned From, unsigned To, unsigned Cy) {
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addDependency(From, {DT_MEMORY, To, /* unused */ 0, Cy});
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}
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void addResourceDep(unsigned From, unsigned To, uint64_t Mask, unsigned Cy) {
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addDepImpl(Nodes[From].ResDeps, {To, Mask, Cy});
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addDependency(From, {DT_RESOURCE, To, Mask, Cy});
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}
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#ifndef NDEBUG
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void dumpRegDeps(raw_ostream &OS, MCInstPrinter &MCIP) const;
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void dumpMemDeps(raw_ostream &OS) const;
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void dumpResDeps(raw_ostream &OS) const;
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void dump(raw_ostream &OS, MCInstPrinter &MCIP) const {
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dumpRegDeps(OS, MCIP);
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dumpMemDeps(OS);
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dumpResDeps(OS);
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}
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void dump(raw_ostream &OS, MCInstPrinter &MCIP) const;
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#endif
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};
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/// A view that collects and prints a few performance numbers.
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class BottleneckAnalysis : public View {
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const MCSubtargetInfo &STI;
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MCInstPrinter &MCIP;
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PressureTracker Tracker;
|
||||
DependencyGraph DG;
|
||||
|
||||
@ -189,8 +194,14 @@ class BottleneckAnalysis : public View {
|
||||
// Prints a bottleneck message to OS.
|
||||
void printBottleneckHints(raw_ostream &OS) const;
|
||||
|
||||
// Used to populate the dependency graph DG.
|
||||
void addRegisterDep(unsigned From, unsigned To, unsigned RegID, unsigned Cy);
|
||||
void addMemoryDep(unsigned From, unsigned To, unsigned Cy);
|
||||
void addResourceDep(unsigned From, unsigned To, uint64_t Mask, unsigned Cy);
|
||||
|
||||
public:
|
||||
BottleneckAnalysis(const MCSubtargetInfo &STI, ArrayRef<MCInst> Sequence);
|
||||
BottleneckAnalysis(const MCSubtargetInfo &STI, MCInstPrinter &MCIP,
|
||||
ArrayRef<MCInst> Sequence);
|
||||
|
||||
void onCycleEnd() override;
|
||||
void onEvent(const HWStallEvent &Event) override { SeenStallCycles = true; }
|
||||
@ -200,7 +211,7 @@ public:
|
||||
void printView(raw_ostream &OS) const override;
|
||||
|
||||
#ifndef NDEBUG
|
||||
void dump(raw_ostream &OS, MCInstPrinter &MCIP) const { DG.dump(OS, MCIP); }
|
||||
void dump(raw_ostream &OS) const { DG.dump(OS, MCIP); }
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
@ -487,7 +487,7 @@ int main(int argc, char **argv) {
|
||||
llvm::make_unique<mca::SummaryView>(SM, Insts, DispatchWidth));
|
||||
|
||||
if (EnableBottleneckAnalysis)
|
||||
Printer.addView(llvm::make_unique<mca::BottleneckAnalysis>(*STI, Insts));
|
||||
Printer.addView(llvm::make_unique<mca::BottleneckAnalysis>(*STI, *IP, Insts));
|
||||
|
||||
if (PrintInstructionInfoView)
|
||||
Printer.addView(
|
||||
|
||||
Loading…
Reference in New Issue
Block a user