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AMDGPU: Whitespace fixes

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llvm-svn: 285659
This commit is contained in:
Matt Arsenault 2016-11-01 00:55:14 +00:00
parent 7a48d04de0
commit bb971d2e8b
8 changed files with 38 additions and 40 deletions
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18
lib/Target/AMDGPU/AMDGPU.td
View File

@ -338,44 +338,44 @@ class SubtargetFeatureISAVersion <int Major, int Minor, int Stepping,
Implies
>;
def FeatureISAVersion7_0_0 : SubtargetFeatureISAVersion <7,0,0,
def FeatureISAVersion7_0_0 : SubtargetFeatureISAVersion <7,0,0,
[FeatureSeaIslands,
FeatureLDSBankCount32]>;
def FeatureISAVersion7_0_1 : SubtargetFeatureISAVersion <7,0,1,
[FeatureSeaIslands,
HalfRate64Ops,
FeatureLDSBankCount32,
FeatureFastFMAF32]>;
def FeatureISAVersion7_0_2 : SubtargetFeatureISAVersion <7,0,2,
[FeatureSeaIslands,
FeatureLDSBankCount16,
FeatureXNACK]>;
def FeatureISAVersion8_0_0 : SubtargetFeatureISAVersion <8,0,0,
[FeatureVolcanicIslands,
FeatureLDSBankCount32,
FeatureSGPRInitBug]>;
def FeatureISAVersion8_0_1 : SubtargetFeatureISAVersion <8,0,1,
[FeatureVolcanicIslands,
FeatureLDSBankCount32,
FeatureXNACK]>;
def FeatureISAVersion8_0_2 : SubtargetFeatureISAVersion <8,0,2,
[FeatureVolcanicIslands,
FeatureLDSBankCount32,
FeatureSGPRInitBug]>;
def FeatureISAVersion8_0_3 : SubtargetFeatureISAVersion <8,0,3,
[FeatureVolcanicIslands,
FeatureLDSBankCount32]>;
def FeatureISAVersion8_0_4 : SubtargetFeatureISAVersion <8,0,4,
[FeatureVolcanicIslands,
FeatureLDSBankCount32]>;
def FeatureISAVersion8_1_0 : SubtargetFeatureISAVersion <8,1,0,
[FeatureVolcanicIslands,
FeatureLDSBankCount16,

16
lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
View File

@ -216,11 +216,11 @@ public:
bool isImmTy(ImmTy ImmT) const {
return isImm() && Imm.Type == ImmT;
}
bool isImmModifier() const {
return isImm() && Imm.Type != ImmTyNone;
}
bool isClampSI() const { return isImmTy(ImmTyClampSI); }
bool isOModSI() const { return isImmTy(ImmTyOModSI); }
bool isDMask() const { return isImmTy(ImmTyDMask); }
@ -245,7 +245,7 @@ public:
bool isSDWASrc0Sel() const { return isImmTy(ImmTySdwaSrc0Sel); }
bool isSDWASrc1Sel() const { return isImmTy(ImmTySdwaSrc1Sel); }
bool isSDWADstUnused() const { return isImmTy(ImmTySdwaDstUnused); }
bool isMod() const {
return isClampSI() || isOModSI();
}
@ -297,7 +297,7 @@ public:
bool isVCSrcB64() const {
return isRegClass(AMDGPU::VS_64RegClassID) || isInlinableImm(MVT::i64);
}
bool isVCSrcF32() const {
return isRegClass(AMDGPU::VS_32RegClassID) || isInlinableImm(MVT::f32);
}
@ -401,7 +401,7 @@ public:
bool hasModifiers() const {
return getModifiers().hasModifiers();
}
bool hasFPModifiers() const {
return getModifiers().hasFPModifiers();
}
@ -1345,7 +1345,7 @@ AMDGPUAsmParser::parseRegOrImmWithIntInputMods(OperandVector &Operands) {
Parser.Lex();
Mods.Sext = true;
}
if (Mods.hasIntModifiers()) {
AMDGPUOperand &Op = static_cast<AMDGPUOperand &>(*Operands.back());
Op.setModifiers(Mods);
@ -3013,7 +3013,7 @@ void AMDGPUAsmParser::cvtSDWA(MCInst &Inst, const OperandVector &Operands,
}
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI, 0);
if (Inst.getOpcode() != AMDGPU::V_NOP_sdwa) {
// V_NOP_sdwa has no optional sdwa arguments
switch (BasicInstType) {
@ -3039,7 +3039,7 @@ void AMDGPUAsmParser::cvtSDWA(MCInst &Inst, const OperandVector &Operands,
llvm_unreachable("Invalid instruction type. Only VOP1, VOP2 and VOPC allowed");
}
}
// special case v_mac_f32:
// it has src2 register operand that is tied to dst operand
if (Inst.getOpcode() == AMDGPU::V_MAC_F32_sdwa) {

8
lib/Target/AMDGPU/BUFInstructions.td
View File

@ -130,8 +130,7 @@ class MTBUF_Load_Pseudo <string opName, RegisterClass regClass> : MTBUF_Pseudo <
i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr, SReg_128:$srsrc,
i1imm:$slc, i1imm:$tfe, SCSrc_b32:$soffset),
" $dst, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"#
" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset"
> {
" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset"> {
let mayLoad = 1;
let mayStore = 0;
}
@ -142,8 +141,7 @@ class MTBUF_Store_Pseudo <string opName, RegisterClass regClass> : MTBUF_Pseudo
i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr,
SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SCSrc_b32:$soffset),
" $vdata, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"#
" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset"
> {
" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset"> {
let mayLoad = 0;
let mayStore = 1;
}
@ -277,7 +275,7 @@ class getMUBUFAsmOps<int addrKind> {
string ret = Pfx # "$offset";
}
class MUBUF_SetupAddr<int addrKind> {
class MUBUF_SetupAddr<int addrKind> {
bits<1> offen = !if(!eq(addrKind, BUFAddrKind.OffEn), 1,
!if(!eq(addrKind, BUFAddrKind.BothEn), 1 , 0));

14
lib/Target/AMDGPU/DSInstructions.td
View File

@ -100,7 +100,7 @@ class DS_1A_Off8_NORET<string opName> : DS_Pseudo<opName,
let AsmMatchConverter = "cvtDSOffset01";
}
class DS_1A2D_NORET<string opName, RegisterClass rc = VGPR_32>
class DS_1A2D_NORET<string opName, RegisterClass rc = VGPR_32>
: DS_Pseudo<opName,
(outs),
(ins VGPR_32:$addr, rc:$data0, rc:$data1, offset:$offset, gds:$gds),
@ -133,7 +133,7 @@ class DS_1A1D_RET <string opName, RegisterClass rc = VGPR_32>
}
class DS_1A2D_RET<string opName,
RegisterClass rc = VGPR_32,
RegisterClass rc = VGPR_32,
RegisterClass src = rc>
: DS_Pseudo<opName,
(outs rc:$vdst),
@ -146,7 +146,7 @@ class DS_1A2D_RET<string opName,
class DS_1A_RET<string opName, RegisterClass rc = VGPR_32>
: DS_Pseudo<opName,
(outs rc:$vdst),
(ins VGPR_32:$addr, offset:$offset, gds:$gds),
(ins VGPR_32:$addr, offset:$offset, gds:$gds),
"$vdst, $addr$offset$gds"> {
let has_data0 = 0;
@ -207,14 +207,14 @@ class DS_1A_GDS <string opName> : DS_Pseudo<opName,
(ins VGPR_32:$addr),
"$addr gds"> {
let has_vdst = 0;
let has_data0 = 0;
let has_vdst = 0;
let has_data0 = 0;
let has_data1 = 0;
let has_offset = 0;
let has_offset0 = 0;
let has_offset1 = 0;
let has_gds = 0;
let has_gds = 0;
let gdsValue = 1;
}
@ -749,7 +749,7 @@ class DS_Real_vi <bits<8> op, DS_Pseudo ds> :
let AssemblerPredicates = [isVI];
let DecoderNamespace="VI";
// encoding
// encoding
let Inst{7-0} = !if(ds.has_offset0, offset0, 0);
let Inst{15-8} = !if(ds.has_offset1, offset1, 0);
let Inst{16} = !if(ds.has_gds, gds, ds.gdsValue);

6
lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
View File

@ -58,7 +58,7 @@ static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm,
if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2))
return MCDisassembler::Success;
return addOperand(Inst, MCOperand::createImm(Imm));
return addOperand(Inst, MCOperand::createImm(Imm));
}
#define DECODE_OPERAND2(RegClass, DecName) \
@ -447,7 +447,7 @@ MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const {
//===----------------------------------------------------------------------===//
// AMDGPUSymbolizer
//===----------------------------------------------------------------------===//
// Try to find symbol name for specified label
bool AMDGPUSymbolizer::tryAddingSymbolicOperand(MCInst &Inst,
raw_ostream &/*cStream*/, int64_t Value,
@ -482,7 +482,7 @@ bool AMDGPUSymbolizer::tryAddingSymbolicOperand(MCInst &Inst,
static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/,
LLVMOpInfoCallback /*GetOpInfo*/,
LLVMSymbolLookupCallback /*SymbolLookUp*/,
void *DisInfo,
void *DisInfo,
MCContext *Ctx,
std::unique_ptr<MCRelocationInfo> &&RelInfo) {
return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo);

2
lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
View File

@ -104,7 +104,7 @@ private:
public:
AMDGPUSymbolizer(MCContext &Ctx, std::unique_ptr<MCRelocationInfo> &&RelInfo,
void *disInfo)
void *disInfo)
: MCSymbolizer(Ctx, std::move(RelInfo)), DisInfo(disInfo) {}
bool tryAddingSymbolicOperand(MCInst &Inst, raw_ostream &cStream,

4
lib/Target/AMDGPU/GCNSchedStrategy.cpp
View File

@ -65,7 +65,7 @@ void GCNMaxOccupancySchedStrategy::initCandidate(SchedCandidate &Cand, SUnit *SU
// and can be retrieved by DAG->getPressureDif(SU).
TempTracker.getUpwardPressure(SU->getInstr(), Pressure, MaxPressure);
}
int NewSGPRPressure = Pressure[SRI->getSGPRPressureSet()];
int NewVGPRPressure = Pressure[SRI->getVGPRPressureSet()];
@ -235,7 +235,7 @@ SUnit *GCNMaxOccupancySchedStrategy::pickNodeBidirectional(bool &IsTopNode) {
TopCand.Reason = NoCand;
GenericScheduler::tryCandidate(Cand, TopCand, nullptr);
if (TopCand.Reason != NoCand) {
Cand.setBest(TopCand);
Cand.setBest(TopCand);
} else {
TopCand.Reason = TopReason;
}

10
lib/Target/AMDGPU/SIRegisterInfo.td
View File

@ -365,17 +365,17 @@ class RegImmMatcher<string name> : AsmOperandClass {
multiclass SIRegOperand <string rc, string MatchName, string opType> {
let OperandNamespace = "AMDGPU" in {
def _b32 : RegisterOperand<!cast<RegisterClass>(rc#"_32")> {
let OperandType = opType#"_INT";
let ParserMatchClass = RegImmMatcher<MatchName#"B32">;
}
def _f32 : RegisterOperand<!cast<RegisterClass>(rc#"_32")> {
let OperandType = opType#"_FP";
let ParserMatchClass = RegImmMatcher<MatchName#"F32">;
}
def _b64 : RegisterOperand<!cast<RegisterClass>(rc#"_64")> {
let OperandType = opType#"_INT";
let ParserMatchClass = RegImmMatcher<MatchName#"B64">;
@ -388,10 +388,10 @@ multiclass SIRegOperand <string rc, string MatchName, string opType> {
}
}
multiclass RegImmOperand <string rc, string MatchName>
multiclass RegImmOperand <string rc, string MatchName>
: SIRegOperand<rc, MatchName, "OPERAND_REG_IMM32">;
multiclass RegInlineOperand <string rc, string MatchName>
multiclass RegInlineOperand <string rc, string MatchName>
: SIRegOperand<rc, MatchName, "OPERAND_REG_INLINE_C">;
//===----------------------------------------------------------------------===//