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[X86][SSE] Canonicalize scalar fp arithmetic shuffle patterns
As discussed on PR38197, this canonicalizes MOVS*(N0, OP(N0, N1)) --> MOVS*(N0, SCALAR_TO_VECTOR(OP(N0[0], N1[0]))) This returns the scalar-fp codegen lost by rL336971. Additionally it handles the OP(N1, N0)) case for commutable (FADD/FMUL) ops. Differential Revision: https://reviews.llvm.org/D49474 llvm-svn: 337419
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@ -30698,8 +30698,37 @@ static SDValue combineTargetShuffle(SDValue N, SelectionDAG &DAG,
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}
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case X86ISD::MOVSD:
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case X86ISD::MOVSS: {
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SDValue V0 = peekThroughBitcasts(N->getOperand(0));
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SDValue V1 = peekThroughBitcasts(N->getOperand(1));
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SDValue N0 = N.getOperand(0);
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SDValue N1 = N.getOperand(1);
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// Canonicalize scalar FPOps:
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// MOVS*(N0, OP(N0, N1)) --> MOVS*(N0, SCALAR_TO_VECTOR(OP(N0[0], N1[0])))
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// If commutable, allow OP(N1[0], N0[0]).
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unsigned Opcode1 = N1.getOpcode();
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if (Opcode1 == ISD::FADD || Opcode1 == ISD::FMUL || Opcode1 == ISD::FSUB ||
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Opcode1 == ISD::FDIV) {
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SDValue N10 = N1.getOperand(0);
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SDValue N11 = N1.getOperand(1);
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if (N10 == N0 ||
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(N11 == N0 && (Opcode1 == ISD::FADD || Opcode1 == ISD::FMUL))) {
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if (N10 != N0)
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std::swap(N10, N11);
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MVT SVT = VT.getVectorElementType();
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SDValue ZeroIdx = DAG.getIntPtrConstant(0, DL);
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N10 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, SVT, N10, ZeroIdx);
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N11 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, SVT, N11, ZeroIdx);
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SDValue Scl = DAG.getNode(Opcode1, DL, SVT, N10, N11);
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SDValue SclVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VT, Scl);
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DCI.AddToWorklist(N10.getNode());
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DCI.AddToWorklist(N11.getNode());
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DCI.AddToWorklist(Scl.getNode());
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DCI.AddToWorklist(SclVec.getNode());
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return DAG.getNode(Opcode, DL, VT, N0, SclVec);
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}
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}
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SDValue V0 = peekThroughBitcasts(N0);
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SDValue V1 = peekThroughBitcasts(N1);
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bool isZero0 = ISD::isBuildVectorAllZeros(V0.getNode());
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bool isZero1 = ISD::isBuildVectorAllZeros(V1.getNode());
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if (isZero0 && isZero1)
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