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[DAGCombiner] reduce code duplication; NFC

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llvm-svn: 360462
This commit is contained in:
Sanjay Patel 2019-05-10 20:02:30 +00:00
parent 71b6ff5204
commit bbfa642e0c
1 changed files with 8 additions and 10 deletions
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18
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@ -17573,9 +17573,9 @@ SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode *N) {
// Combine an extract of an extract into a single extract_subvector. // Combine an extract of an extract into a single extract_subvector.
// ext (ext X, C), 0 --> ext X, C // ext (ext X, C), 0 --> ext X, C
if (isNullConstant(N->getOperand(1)) && SDValue Index = N->getOperand(1);
V.getOpcode() == ISD::EXTRACT_SUBVECTOR && V.hasOneUse() && if (isNullConstant(Index) && V.getOpcode() == ISD::EXTRACT_SUBVECTOR &&
isa<ConstantSDNode>(V.getOperand(1))) { V.hasOneUse() && isa<ConstantSDNode>(V.getOperand(1))) {
if (TLI.isExtractSubvectorCheap(NVT, V.getOperand(0).getValueType(), if (TLI.isExtractSubvectorCheap(NVT, V.getOperand(0).getValueType(),
V.getConstantOperandVal(1)) && V.getConstantOperandVal(1)) &&
TLI.isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, NVT)) { TLI.isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, NVT)) {
@ -17590,8 +17590,7 @@ SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode *N) {
// Vi if possible // Vi if possible
// Only operand 0 is checked as 'concat' assumes all inputs of the same // Only operand 0 is checked as 'concat' assumes all inputs of the same
// type. // type.
if (V.getOpcode() == ISD::CONCAT_VECTORS && if (V.getOpcode() == ISD::CONCAT_VECTORS && isa<ConstantSDNode>(Index) &&
isa<ConstantSDNode>(N->getOperand(1)) &&
V.getOperand(0).getValueType() == NVT) { V.getOperand(0).getValueType() == NVT) {
unsigned Idx = N->getConstantOperandVal(1); unsigned Idx = N->getConstantOperandVal(1);
unsigned NumElems = NVT.getVectorNumElements(); unsigned NumElems = NVT.getVectorNumElements();
@ -17604,7 +17603,7 @@ SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode *N) {
// If the input is a build vector. Try to make a smaller build vector. // If the input is a build vector. Try to make a smaller build vector.
if (V.getOpcode() == ISD::BUILD_VECTOR) { if (V.getOpcode() == ISD::BUILD_VECTOR) {
if (auto *Idx = dyn_cast<ConstantSDNode>(N->getOperand(1))) { if (auto *IdxC = dyn_cast<ConstantSDNode>(Index)) {
EVT InVT = V.getValueType(); EVT InVT = V.getValueType();
unsigned ExtractSize = NVT.getSizeInBits(); unsigned ExtractSize = NVT.getSizeInBits();
unsigned EltSize = InVT.getScalarSizeInBits(); unsigned EltSize = InVT.getScalarSizeInBits();
@ -17619,7 +17618,7 @@ SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode *N) {
(NumElems == 1 || (NumElems == 1 ||
TLI.isOperationLegal(ISD::BUILD_VECTOR, ExtractVT))) && TLI.isOperationLegal(ISD::BUILD_VECTOR, ExtractVT))) &&
(!LegalTypes || TLI.isTypeLegal(ExtractVT))) { (!LegalTypes || TLI.isTypeLegal(ExtractVT))) {
unsigned IdxVal = Idx->getZExtValue(); unsigned IdxVal = IdxC->getZExtValue();
IdxVal *= NVT.getScalarSizeInBits(); IdxVal *= NVT.getScalarSizeInBits();
IdxVal /= EltSize; IdxVal /= EltSize;
@ -17647,9 +17646,8 @@ SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode *N) {
return SDValue(); return SDValue();
// Only handle cases where both indexes are constants. // Only handle cases where both indexes are constants.
auto *ExtIdx = dyn_cast<ConstantSDNode>(N->getOperand(1)); auto *ExtIdx = dyn_cast<ConstantSDNode>(Index);
auto *InsIdx = dyn_cast<ConstantSDNode>(V.getOperand(2)); auto *InsIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
if (InsIdx && ExtIdx) { if (InsIdx && ExtIdx) {
// Combine: // Combine:
// (extract_subvec (insert_subvec V1, V2, InsIdx), ExtIdx) // (extract_subvec (insert_subvec V1, V2, InsIdx), ExtIdx)
@ -17662,7 +17660,7 @@ SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode *N) {
return DAG.getNode( return DAG.getNode(
ISD::EXTRACT_SUBVECTOR, SDLoc(N), NVT, ISD::EXTRACT_SUBVECTOR, SDLoc(N), NVT,
DAG.getBitcast(N->getOperand(0).getValueType(), V.getOperand(0)), DAG.getBitcast(N->getOperand(0).getValueType(), V.getOperand(0)),
N->getOperand(1)); Index);
} }
} }