mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-24 19:52:54 +01:00
Add lower argument and return of device function
llvm-svn: 116805
This commit is contained in:
Che-Liang Chiou
parent
f937f0ed59
commit
bc4f00f42d
@ -32,6 +32,8 @@ namespace {
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virtual void EmitInstruction(const MachineInstr *MI);
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void printOperand(const MachineInstr *MI, int opNum, raw_ostream &OS);
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// autogen'd.
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void printInstruction(const MachineInstr *MI, raw_ostream &OS);
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static const char *getRegisterName(unsigned RegNo);
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@ -40,10 +42,27 @@ namespace {
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void PTXAsmPrinter::EmitInstruction(const MachineInstr *MI) {
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SmallString<128> str;
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raw_svector_ostream os(str);
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printInstruction(MI, os);
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os << ';';
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OutStreamer.EmitRawText(os.str());
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raw_svector_ostream OS(str);
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printInstruction(MI, OS);
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OS << ';';
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OutStreamer.EmitRawText(OS.str());
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}
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void PTXAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
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raw_ostream &OS) {
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const MachineOperand &MO = MI->getOperand(opNum);
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switch (MO.getType()) {
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default:
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llvm_unreachable("<unknown operand type>");
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break;
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case MachineOperand::MO_Register:
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OS << getRegisterName(MO.getReg());
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break;
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case MachineOperand::MO_Immediate:
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OS << (int) MO.getImm();
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break;
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}
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}
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#include "PTXGenAsmWriter.inc"
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@ -11,9 +11,12 @@
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//
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//===----------------------------------------------------------------------===//
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#include "PTX.h"
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#include "PTXISelLowering.h"
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#include "PTXRegisterInfo.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
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@ -23,6 +26,7 @@ PTXTargetLowering::PTXTargetLowering(TargetMachine &TM)
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: TargetLowering(TM, new TargetLoweringObjectFileELF()) {
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// Set up the register classes.
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addRegisterClass(MVT::i1, PTX::PredsRegisterClass);
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addRegisterClass(MVT::i32, PTX::RRegs32RegisterClass);
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// Compute derived properties from the register classes
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computeRegisterProperties();
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@ -40,6 +44,57 @@ const char *PTXTargetLowering::getTargetNodeName(unsigned Opcode) const {
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// Calling Convention Implementation
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//===----------------------------------------------------------------------===//
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static struct argmap_entry {
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MVT::SimpleValueType VT;
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TargetRegisterClass *RC;
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TargetRegisterClass::iterator loc;
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argmap_entry(MVT::SimpleValueType _VT, TargetRegisterClass *_RC)
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: VT(_VT), RC(_RC), loc(_RC->begin()) {}
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void reset(void) { loc = RC->begin(); }
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bool operator==(MVT::SimpleValueType _VT) { return VT == _VT; }
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} argmap[] = {
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argmap_entry(MVT::i1, PTX::PredsRegisterClass),
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argmap_entry(MVT::i32, PTX::RRegs32RegisterClass)
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};
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static SDValue lower_kernel_argument(int i,
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SDValue Chain,
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DebugLoc dl,
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MVT::SimpleValueType VT,
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argmap_entry *entry,
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SelectionDAG &DAG,
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unsigned *argreg) {
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// TODO
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llvm_unreachable("Not implemented yet");
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}
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static SDValue lower_device_argument(int i,
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SDValue Chain,
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DebugLoc dl,
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MVT::SimpleValueType VT,
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argmap_entry *entry,
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SelectionDAG &DAG,
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unsigned *argreg) {
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MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
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unsigned preg = *++(entry->loc); // allocate start from register 1
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unsigned vreg = RegInfo.createVirtualRegister(entry->RC);
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RegInfo.addLiveIn(preg, vreg);
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*argreg = preg;
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return DAG.getCopyFromReg(Chain, dl, vreg, VT);
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}
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typedef SDValue (*lower_argument_func)(int i,
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SDValue Chain,
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DebugLoc dl,
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MVT::SimpleValueType VT,
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argmap_entry *entry,
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SelectionDAG &DAG,
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unsigned *argreg);
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SDValue PTXTargetLowering::
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LowerFormalArguments(SDValue Chain,
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CallingConv::ID CallConv,
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@ -48,6 +103,40 @@ SDValue PTXTargetLowering::
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DebugLoc dl,
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SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const {
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if (isVarArg) llvm_unreachable("PTX does not support varargs");
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lower_argument_func lower_argument;
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switch (CallConv) {
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default:
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llvm_unreachable("Unsupported calling convention");
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break;
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case CallingConv::PTX_Kernel:
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lower_argument = lower_kernel_argument;
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break;
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case CallingConv::PTX_Device:
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lower_argument = lower_device_argument;
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break;
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}
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// Reset argmap before allocation
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for (struct argmap_entry *i = argmap, *e = argmap + array_lengthof(argmap);
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i != e; ++ i)
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i->reset();
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for (int i = 0, e = Ins.size(); i != e; ++ i) {
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MVT::SimpleValueType VT = Ins[i].VT.getSimpleVT().SimpleTy;
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struct argmap_entry *entry = std::find(argmap,
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argmap + array_lengthof(argmap), VT);
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if (entry == argmap + array_lengthof(argmap))
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llvm_unreachable("Type of argument is not supported");
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unsigned reg;
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SDValue arg = lower_argument(i, Chain, dl, VT, entry, DAG, ®);
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InVals.push_back(arg);
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}
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return Chain;
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}
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@ -59,7 +148,7 @@ SDValue PTXTargetLowering::
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const SmallVectorImpl<SDValue> &OutVals,
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DebugLoc dl,
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SelectionDAG &DAG) const {
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assert(!isVarArg && "PTX does not support var args.");
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if (isVarArg) llvm_unreachable("PTX does not support varargs");
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switch (CallConv) {
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default:
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@ -74,10 +163,26 @@ SDValue PTXTargetLowering::
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// PTX_Device
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// return void
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if (Outs.size() == 0)
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return DAG.getNode(PTXISD::RET, dl, MVT::Other, Chain);
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// TODO: allocate return register
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assert(Outs[0].VT == MVT::i32 && "Can return only basic types");
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SDValue Flag;
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unsigned reg = PTX::R0;
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// If this is the first return lowered for this function, add the regs to the
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// liveout set for the function
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if (DAG.getMachineFunction().getRegInfo().liveout_empty())
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DAG.getMachineFunction().getRegInfo().addLiveOut(reg);
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// Copy the result values into the output registers
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Chain = DAG.getCopyToReg(Chain, dl, reg, OutVals[0], Flag);
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// Guarantee that all emitted copies are stuck together,
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// avoiding something bad
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Flag = Chain.getValue(1);
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return DAG.getNode(PTXISD::RET, dl, MVT::Other, Chain, Flag);
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}
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@ -11,7 +11,9 @@
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//
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//===----------------------------------------------------------------------===//
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#include "PTX.h"
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#include "PTXInstrInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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using namespace llvm;
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@ -20,3 +22,66 @@ using namespace llvm;
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PTXInstrInfo::PTXInstrInfo(PTXTargetMachine &_TM)
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: TargetInstrInfoImpl(PTXInsts, array_lengthof(PTXInsts)),
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RI(_TM, *this), TM(_TM) {}
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static const struct map_entry {
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const TargetRegisterClass *cls;
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const int opcode;
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} map[] = {
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{ &PTX::RRegs32RegClass, PTX::MOVrr },
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{ &PTX::PredsRegClass, PTX::MOVpp }
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};
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void PTXInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, DebugLoc DL,
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unsigned DstReg, unsigned SrcReg,
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bool KillSrc) const {
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for (int i = 0, e = sizeof(map)/sizeof(map[0]); i != e; ++ i)
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if (PTX::RRegs32RegClass.contains(DstReg, SrcReg)) {
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BuildMI(MBB, I, DL,
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get(PTX::MOVrr), DstReg).addReg(SrcReg, getKillRegState(KillSrc));
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return;
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}
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llvm_unreachable("Impossible reg-to-reg copy");
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}
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bool PTXInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned DstReg, unsigned SrcReg,
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const TargetRegisterClass *DstRC,
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const TargetRegisterClass *SrcRC,
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DebugLoc DL) const {
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if (DstRC != SrcRC)
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return false;
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for (int i = 0, e = sizeof(map)/sizeof(map[0]); i != e; ++ i)
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if (DstRC == map[i].cls) {
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MachineInstr *MI = BuildMI(MBB, I, DL, get(map[i].opcode),
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DstReg).addReg(SrcReg);
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if (MI->findFirstPredOperandIdx() == -1) {
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MI->addOperand(MachineOperand::CreateReg(0, false));
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MI->addOperand(MachineOperand::CreateImm(/*IsInv=*/0));
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}
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return true;
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}
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return false;
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}
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bool PTXInstrInfo::isMoveInstr(const MachineInstr& MI,
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unsigned &SrcReg, unsigned &DstReg,
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unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
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switch (MI.getOpcode()) {
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default:
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return false;
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case PTX::MOVpp:
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case PTX::MOVrr:
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assert(MI.getNumOperands() >= 2 &&
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MI.getOperand(0).isReg() && MI.getOperand(1).isReg() &&
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"Invalid register-register move instruction");
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SrcSubIdx = DstSubIdx = 0; // No sub-registers
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DstReg = MI.getOperand(0).getReg();
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SrcReg = MI.getOperand(1).getReg();
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return true;
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}
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}
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@ -29,6 +29,22 @@ class PTXInstrInfo : public TargetInstrInfoImpl {
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explicit PTXInstrInfo(PTXTargetMachine &_TM);
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virtual const PTXRegisterInfo &getRegisterInfo() const { return RI; }
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virtual void copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, DebugLoc DL,
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unsigned DstReg, unsigned SrcReg,
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bool KillSrc) const;
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virtual bool copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned DstReg, unsigned SrcReg,
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const TargetRegisterClass *DstRC,
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const TargetRegisterClass *SrcRC,
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DebugLoc DL) const;
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virtual bool isMoveInstr(const MachineInstr& MI,
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unsigned &SrcReg, unsigned &DstReg,
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unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
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}; // class PTXInstrInfo
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} // namespace llvm
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@ -30,6 +30,27 @@ def PTXret
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// Instructions
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//===----------------------------------------------------------------------===//
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///===- Data Movement and Conversion Instructions -------------------------===//
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let neverHasSideEffects = 1 in {
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// rely on isMoveInstr to separate MOVpp, MOVrr, etc.
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def MOVpp
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: InstPTX<(outs Preds:$d), (ins Preds:$a), "mov.pred\t$d, $a", []>;
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def MOVrr
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: InstPTX<(outs RRegs32:$d), (ins RRegs32:$a), "mov.s32\t$d, $a", []>;
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}
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let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
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def MOVpi
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: InstPTX<(outs Preds:$d), (ins i1imm:$a), "mov.pred\t$d, $a",
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[(set Preds:$d, imm:$a)]>;
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def MOVri
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: InstPTX<(outs RRegs32:$d), (ins i32imm:$a), "mov.s32\t$d, $a",
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[(set RRegs32:$d, imm:$a)]>;
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}
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///===- Control Flow Instructions -----------------------------------------===//
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let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
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def EXIT : InstPTX<(outs), (ins), "exit", [(PTXexit)]>;
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def RET : InstPTX<(outs), (ins), "ret", [(PTXret)]>;
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@ -40,10 +40,11 @@ struct PTXRegisterInfo : public PTXGenRegisterInfo {
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virtual bool hasFP(const MachineFunction &MF) const { return false; }
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// FIXME: Given that PTX does not support stack frame, what should we do here?
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virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
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int SPAdj,
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RegScavenger *RS = NULL) const {}
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RegScavenger *RS = NULL) const {
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llvm_unreachable("PTX does not support general function call");
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}
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virtual void emitPrologue(MachineFunction &MF) const {}
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virtual void emitEpilogue(MachineFunction &MF,
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@ -52,6 +52,39 @@ def P29 : PTXReg<"p29">;
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def P30 : PTXReg<"p30">;
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def P31 : PTXReg<"p31">;
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def R0 : PTXReg<"r0">;
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def R1 : PTXReg<"r1">;
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def R2 : PTXReg<"r2">;
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def R3 : PTXReg<"r3">;
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def R4 : PTXReg<"r4">;
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def R5 : PTXReg<"r5">;
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def R6 : PTXReg<"r6">;
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def R7 : PTXReg<"r7">;
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def R8 : PTXReg<"r8">;
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def R9 : PTXReg<"r9">;
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def R10 : PTXReg<"r10">;
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def R11 : PTXReg<"r11">;
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def R12 : PTXReg<"r12">;
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def R13 : PTXReg<"r13">;
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def R14 : PTXReg<"r14">;
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def R15 : PTXReg<"r15">;
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def R16 : PTXReg<"r16">;
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def R17 : PTXReg<"r17">;
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def R18 : PTXReg<"r18">;
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def R19 : PTXReg<"r19">;
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def R20 : PTXReg<"r20">;
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def R21 : PTXReg<"r21">;
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def R22 : PTXReg<"r22">;
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def R23 : PTXReg<"r23">;
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def R24 : PTXReg<"r24">;
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def R25 : PTXReg<"r25">;
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def R26 : PTXReg<"r26">;
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def R27 : PTXReg<"r27">;
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def R28 : PTXReg<"r28">;
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def R29 : PTXReg<"r29">;
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def R30 : PTXReg<"r30">;
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def R31 : PTXReg<"r31">;
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//===----------------------------------------------------------------------===//
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// Register classes
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//===----------------------------------------------------------------------===//
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@ -61,3 +94,9 @@ def Preds : RegisterClass<"PTX", [i1], 8,
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P8, P9, P10, P11, P12, P13, P14, P15,
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P16, P17, P18, P19, P20, P21, P22, P23,
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P24, P25, P26, P27, P28, P29, P30, P31]>;
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def RRegs32 : RegisterClass<"PTX", [i32], 32,
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[R0, R1, R2, R3, R4, R5, R6, R7,
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R8, R9, R10, R11, R12, R13, R14, R15,
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R16, R17, R18, R19, R20, R21, R22, R23,
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R24, R25, R26, R27, R28, R29, R30, R31]>;
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