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Fix spelling compliment->complement. Mostly refering to 2s complement. NFC

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llvm-svn: 299970
This commit is contained in:
Craig Topper 2017-04-11 18:47:58 +00:00
parent e3e490fb9f
commit bc67402813
5 changed files with 7 additions and 7 deletions
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2
include/llvm/Transforms/IPO/FunctionAttrs.h
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@ -56,7 +56,7 @@ Pass *createPostOrderFunctionAttrsLegacyPass();
/// This pass provides a general RPO or "top down" propagation of
/// function attributes. For a few (rare) cases, we can deduce significantly
/// more about function attributes by working in RPO, so this pass
/// provides the compliment to the post-order pass above where the majority of
/// provides the complement to the post-order pass above where the majority of
/// deduction is performed.
// FIXME: Currently there is no RPO CGSCC pass structure to slide into and so
// this is a boring module pass, but eventually it should be an RPO CGSCC pass

4
lib/Target/AVR/AVRInstrInfo.td
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@ -694,7 +694,7 @@ Defs = [SREG] in
}
//===----------------------------------------------------------------------===//
// One's/Two's Compliment
// One's/Two's Complement
//===----------------------------------------------------------------------===//
let Constraints = "$src = $rd",
Defs = [SREG] in
@ -1718,7 +1718,7 @@ Defs = [SREG] in
(implicit SREG)]>;
// CBR Rd, K
// Alias for `ANDI Rd, COM(K)` where COM(K) is the compliment of K.
// Alias for `ANDI Rd, COM(K)` where COM(K) is the complement of K.
// FIXME: This uses the 'complement' encoder. We need it to also use the
// imm_ldi8 encoder. This will cause no fixups to be created on this instruction.
def CBRRdK : FRdK<0b0111,

2
lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.h
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@ -63,7 +63,7 @@ private:
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
/// Takes the compliment of a number (~0 - val).
/// Takes the complement of a number (~0 - val).
unsigned encodeComplement(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;

2
lib/Target/NVPTX/NVPTXInstrInfo.td
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@ -517,7 +517,7 @@ multiclass ADD_SUB_i1<SDNode OpNode> {
defm ADD_i1 : ADD_SUB_i1<add>;
defm SUB_i1 : ADD_SUB_i1<sub>;
// int16, int32, and int64 signed addition. Since nvptx is 2's compliment, we
// int16, int32, and int64 signed addition. Since nvptx is 2's complement, we
// also use these for unsigned arithmetic.
defm ADD : I3<"add.s", add>;
defm SUB : I3<"sub.s", sub>;

4
lib/Transforms/InstCombine/InstCombineAddSub.cpp
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@ -902,7 +902,7 @@ bool InstCombiner::WillNotOverflowSignedAdd(Value *LHS, Value *RHS,
APInt RHSKnownOne(BitWidth, 0);
computeKnownBits(RHS, RHSKnownZero, RHSKnownOne, 0, &CxtI);
// Addition of two 2's compliment numbers having opposite signs will never
// Addition of two 2's complement numbers having opposite signs will never
// overflow.
if ((LHSKnownOne[BitWidth - 1] && RHSKnownZero[BitWidth - 1]) ||
(LHSKnownZero[BitWidth - 1] && RHSKnownOne[BitWidth - 1]))
@ -939,7 +939,7 @@ bool InstCombiner::WillNotOverflowSignedSub(Value *LHS, Value *RHS,
APInt RHSKnownOne(BitWidth, 0);
computeKnownBits(RHS, RHSKnownZero, RHSKnownOne, 0, &CxtI);
// Subtraction of two 2's compliment numbers having identical signs will
// Subtraction of two 2's complement numbers having identical signs will
// never overflow.
if ((LHSKnownOne[BitWidth - 1] && RHSKnownOne[BitWidth - 1]) ||
(LHSKnownZero[BitWidth - 1] && RHSKnownZero[BitWidth - 1]))