RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-22 10:42:39 +01:00
Code Issues Projects Releases Wiki Activity

[InstCombine] Support vectors in SimplifyAddWithRemainder.

Browse Source 
SimplifyAddWithRemainder currently also matches for vector types, but
tries to create an integer constant, which causes a crash.

By using Constant::getIntegerValue() we can support both the scalar and
vector cases.

The 2 added test cases crash without the fix.

Reviewers: spatel, lebedev.ri

Reviewed By: spatel, lebedev.ri

Differential Revision: https://reviews.llvm.org/D75906
This commit is contained in:
Florian Hahn 2020-03-10 14:22:19 +00:00
parent 6bec78f65f
commit bc7c21fd6c
2 changed files with 34 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
lib/Transforms/InstCombine/InstCombineAddSub.cpp
View File

@ -1044,8 +1044,7 @@ Value *InstCombiner::SimplifyAddWithRemainder(BinaryOperator &I) {
// Match RemOpV = X / C0
if (MatchDiv(RemOpV, DivOpV, DivOpC, IsSigned) && X == DivOpV &&
C0 == DivOpC && !MulWillOverflow(C0, C1, IsSigned)) {
Value *NewDivisor =
ConstantInt::get(X->getType()->getContext(), C0 * C1);
Value *NewDivisor = ConstantInt::get(X->getType(), C0 * C1);
return IsSigned ? Builder.CreateSRem(X, NewDivisor, "srem")
: Builder.CreateURem(X, NewDivisor, "urem");
}

33
test/Transforms/InstCombine/add4.ll
View File

@ -14,6 +14,20 @@ define i64 @match_unsigned(i64 %x) {
ret i64 %t4
}
define <2 x i64> @match_unsigned_vector(<2 x i64> %x) {
; CHECK-LABEL: @match_unsigned_vector(
; CHECK-NEXT: bb:
; CHECK-NEXT: [[UREM:%.*]] = urem <2 x i64> [[X:%.*]], <i64 19136, i64 19136>
; CHECK-NEXT: ret <2 x i64> [[UREM]]
;
bb:
%tmp = urem <2 x i64> %x, <i64 299, i64 299>
%tmp1 = udiv <2 x i64> %x, <i64 299, i64 299>
%tmp2 = urem <2 x i64> %tmp1, <i64 64, i64 64>
%tmp3 = mul <2 x i64> %tmp2, <i64 299, i64 299>
%tmp4 = add <2 x i64> %tmp, %tmp3
ret <2 x i64> %tmp4
}
define i64 @match_andAsRem_lshrAsDiv_shlAsMul(i64 %x) {
; CHECK-LABEL: @match_andAsRem_lshrAsDiv_shlAsMul(
; CHECK-NEXT: [[UREM:%.*]] = urem i64 [[X:%.*]], 576
@ -44,6 +58,25 @@ define i64 @match_signed(i64 %x) {
ret i64 %t8
}
define <2 x i64> @match_signed_vector(<2 x i64> %x) {
; CHECK-LABEL: @match_signed_vector(
; CHECK-NEXT: bb:
; CHECK-NEXT: [[SREM1:%.*]] = srem <2 x i64> [[X:%.*]], <i64 172224, i64 172224>
; CHECK-NEXT: ret <2 x i64> [[SREM1]]
;
bb:
%tmp = srem <2 x i64> %x, <i64 299, i64 299>
%tmp1 = sdiv <2 x i64> %x, <i64 299, i64 299>
%tmp2 = srem <2 x i64> %tmp1, <i64 64, i64 64>
%tmp3 = sdiv <2 x i64> %x, <i64 19136, i64 19136>
%tmp4 = srem <2 x i64> %tmp3, <i64 9, i64 9>
%tmp5 = mul <2 x i64> %tmp2, <i64 299, i64 299>
%tmp6 = add <2 x i64> %tmp, %tmp5
%tmp7 = mul <2 x i64> %tmp4, <i64 19136, i64 19136>
%tmp8 = add <2 x i64> %tmp6, %tmp7
ret <2 x i64> %tmp8
}
define i64 @not_match_inconsistent_signs(i64 %x) {
; CHECK-LABEL: @not_match_inconsistent_signs(
; CHECK-NEXT: [[T:%.*]] = urem i64 [[X:%.*]], 299