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[AArch64] Add preferred alignments for Exynos M1

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Differential Revision: http://reviews.llvm.org/D21203

llvm-svn: 272400
This commit is contained in:
Evandro Menezes 2016-06-10 16:00:18 +00:00
parent e8ab9012c8
commit bcba8613a3
3 changed files with 13 additions and 2 deletions
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4
lib/Target/AArch64/AArch64ISelLowering.cpp
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@ -517,7 +517,11 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
MaskAndBranchFoldingIsLegal = true;
EnableExtLdPromotion = true;
// Set required alignment.
setMinFunctionAlignment(2);
// Set preferred alignments.
setPrefFunctionAlignment(STI.getPrefFunctionAlignment());
setPrefLoopAlignment(STI.getPrefLoopAlignment());
setHasExtractBitsInsn(true);

7
lib/Target/AArch64/AArch64Subtarget.cpp
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@ -63,14 +63,17 @@ void AArch64Subtarget::initializeProperties() {
case CortexA57:
MaxInterleaveFactor = 4;
break;
case ExynosM1:
PrefFunctionAlignment = 4;
PrefLoopAlignment = 3;
break;
case Kryo:
MaxInterleaveFactor = 4;
VectorInsertExtractBaseCost = 2;
break;
case Others: break;
case CortexA35: break;
case CortexA53: break;
case ExynosM1: break;
case Others: break;
}
}

4
lib/Target/AArch64/AArch64Subtarget.h
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@ -86,6 +86,8 @@ protected:
uint16_t PrefetchDistance = 0;
uint16_t MinPrefetchStride = 1;
unsigned MaxPrefetchIterationsAhead = UINT_MAX;
unsigned PrefFunctionAlignment = 0;
unsigned PrefLoopAlignment = 0;
// ReserveX18 - X18 is not available as a general purpose register.
bool ReserveX18;
@ -195,6 +197,8 @@ public:
unsigned getMaxPrefetchIterationsAhead() const {
return MaxPrefetchIterationsAhead;
}
unsigned getPrefFunctionAlignment() const { return PrefFunctionAlignment; }
unsigned getPrefLoopAlignment() const { return PrefLoopAlignment; }
/// CPU has TBI (top byte of addresses is ignored during HW address
/// translation) and OS enables it.