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[AArch64] Add preferred alignments for Exynos M1
Differential Revision: http://reviews.llvm.org/D21203 llvm-svn: 272400
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@ -517,7 +517,11 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
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MaskAndBranchFoldingIsLegal = true;
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EnableExtLdPromotion = true;
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// Set required alignment.
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setMinFunctionAlignment(2);
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// Set preferred alignments.
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setPrefFunctionAlignment(STI.getPrefFunctionAlignment());
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setPrefLoopAlignment(STI.getPrefLoopAlignment());
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setHasExtractBitsInsn(true);
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@ -63,14 +63,17 @@ void AArch64Subtarget::initializeProperties() {
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case CortexA57:
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MaxInterleaveFactor = 4;
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break;
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case ExynosM1:
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PrefFunctionAlignment = 4;
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PrefLoopAlignment = 3;
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break;
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case Kryo:
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MaxInterleaveFactor = 4;
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VectorInsertExtractBaseCost = 2;
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break;
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case Others: break;
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case CortexA35: break;
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case CortexA53: break;
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case ExynosM1: break;
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case Others: break;
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}
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}
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@ -86,6 +86,8 @@ protected:
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uint16_t PrefetchDistance = 0;
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uint16_t MinPrefetchStride = 1;
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unsigned MaxPrefetchIterationsAhead = UINT_MAX;
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unsigned PrefFunctionAlignment = 0;
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unsigned PrefLoopAlignment = 0;
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// ReserveX18 - X18 is not available as a general purpose register.
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bool ReserveX18;
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@ -195,6 +197,8 @@ public:
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unsigned getMaxPrefetchIterationsAhead() const {
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return MaxPrefetchIterationsAhead;
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}
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unsigned getPrefFunctionAlignment() const { return PrefFunctionAlignment; }
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unsigned getPrefLoopAlignment() const { return PrefLoopAlignment; }
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/// CPU has TBI (top byte of addresses is ignored during HW address
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/// translation) and OS enables it.
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