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[ARM] Tighten f64<->f16 conversion requirements

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Fix missing Requires fields.

Patch by Bernard Ogden (bogden)

Reviewers: SjoerdMeijer, javed.absar, t.p.northover	

Reviewed By: t.p.northover

Differential Revision: https://reviews.llvm.org/D51631

llvm-svn: 342061
This commit is contained in:
Diogo N. Sampaio 2018-09-12 16:24:43 +00:00
parent 92e7d4079f
commit bccbb4da14
3 changed files with 37 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
lib/Target/ARM/ARMInstrVFP.td
View File

@ -725,9 +725,11 @@ def VCVTBHD : ADuI<0b11101, 0b11, 0b0010, 0b01, 0,
}
def : FullFP16Pat<(f64 (fpextend HPR:$Sm)),
(VCVTBHD (COPY_TO_REGCLASS HPR:$Sm, SPR))>;
(VCVTBHD (COPY_TO_REGCLASS HPR:$Sm, SPR))>,
Requires<[HasFPARMv8, HasDPVFP]>;
def : FP16Pat<(f64 (f16_to_fp GPR:$a)),
(VCVTBHD (COPY_TO_REGCLASS GPR:$a, SPR))>;
(VCVTBHD (COPY_TO_REGCLASS GPR:$a, SPR))>,
Requires<[HasFPARMv8, HasDPVFP]>;
def VCVTBDH : ADuI<0b11101, 0b11, 0b0011, 0b01, 0,
(outs SPR:$Sd), (ins DPR:$Dm),
@ -746,9 +748,11 @@ def VCVTBDH : ADuI<0b11101, 0b11, 0b0011, 0b01, 0,
}
def : FullFP16Pat<(f16 (fpround DPR:$Dm)),
(COPY_TO_REGCLASS (VCVTBDH DPR:$Dm), HPR)>;
(COPY_TO_REGCLASS (VCVTBDH DPR:$Dm), HPR)>,
Requires<[HasFPARMv8, HasDPVFP]>;
def : FP16Pat<(fp_to_f16 (f64 DPR:$a)),
(i32 (COPY_TO_REGCLASS (VCVTBDH DPR:$a), GPR))>;
(i32 (COPY_TO_REGCLASS (VCVTBDH DPR:$a), GPR))>,
Requires<[HasFPARMv8, HasDPVFP]>;
def VCVTTHD : ADuI<0b11101, 0b11, 0b0010, 0b11, 0,
(outs DPR:$Dd), (ins SPR:$Sm),

22
test/CodeGen/ARM/fpconv.ll
View File

@ -1,9 +1,13 @@
; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o - | FileCheck %s --check-prefix=CHECK-VFP
; RUN: llc -mtriple=arm-apple-darwin %s -o - | FileCheck %s
; RUN: llc -mtriple=armv8r-none-none-eabi %s -o - | FileCheck %s --check-prefix=CHECK-VFP
; RUN: llc -mtriple=armv8r-none-none-eabi -mattr=+fp-only-sp %s -o - | FileCheck %s --check-prefix=CHECK-VFP-SP
define float @f1(double %x) {
;CHECK-VFP-LABEL: f1:
;CHECK-VFP: vcvt.f32.f64
;CHECK-VFP-SP-LABEL: f1:
;CHECK-VFP-SP: bl __aeabi_d2f
;CHECK-LABEL: f1:
;CHECK: truncdfsf2
entry:
@ -14,6 +18,8 @@ entry:
define double @f2(float %x) {
;CHECK-VFP-LABEL: f2:
;CHECK-VFP: vcvt.f64.f32
;CHECK-VFP-SP-LABEL: f2:
;CHECK-VFP-SP: bl __aeabi_f2d
;CHECK-LABEL: f2:
;CHECK: extendsfdf2
entry:
@ -24,6 +30,8 @@ entry:
define i32 @f3(float %x) {
;CHECK-VFP-LABEL: f3:
;CHECK-VFP: vcvt.s32.f32
;CHECK-VFP-SP-LABEL: f3:
;CHECK-VFP-SP: vcvt.s32.f32
;CHECK-LABEL: f3:
;CHECK: fixsfsi
entry:
@ -34,6 +42,8 @@ entry:
define i32 @f4(float %x) {
;CHECK-VFP-LABEL: f4:
;CHECK-VFP: vcvt.u32.f32
;CHECK-VFP-SP-LABEL: f4:
;CHECK-VFP-SP: vcvt.u32.f32
;CHECK-LABEL: f4:
;CHECK: fixunssfsi
entry:
@ -44,6 +54,8 @@ entry:
define i32 @f5(double %x) {
;CHECK-VFP-LABEL: f5:
;CHECK-VFP: vcvt.s32.f64
;CHECK-VFP-SP-LABEL: f5:
;CHECK-VFP-SP: bl __aeabi_d2iz
;CHECK-LABEL: f5:
;CHECK: fixdfsi
entry:
@ -54,6 +66,8 @@ entry:
define i32 @f6(double %x) {
;CHECK-VFP-LABEL: f6:
;CHECK-VFP: vcvt.u32.f64
;CHECK-VFP-SP-LABEL: f6:
;CHECK-VFP-SP: bl __aeabi_d2uiz
;CHECK-LABEL: f6:
;CHECK: fixunsdfsi
entry:
@ -64,6 +78,8 @@ entry:
define float @f7(i32 %a) {
;CHECK-VFP-LABEL: f7:
;CHECK-VFP: vcvt.f32.s32
;CHECK-VFP-SP-LABEL: f7:
;CHECK-VFP-SP: vcvt.f32.s32
;CHECK-LABEL: f7:
;CHECK: floatsisf
entry:
@ -74,6 +90,8 @@ entry:
define double @f8(i32 %a) {
;CHECK-VFP-LABEL: f8:
;CHECK-VFP: vcvt.f64.s32
;CHECK-VFP-SP-LABEL: f8:
;CHECK-VFP-SP: bl __aeabi_i2d
;CHECK-LABEL: f8:
;CHECK: floatsidf
entry:
@ -84,6 +102,8 @@ entry:
define float @f9(i32 %a) {
;CHECK-VFP-LABEL: f9:
;CHECK-VFP: vcvt.f32.u32
;CHECK-VFP-SP-LABEL: f9:
;CHECK-VFP-SP: vcvt.f32.u32
;CHECK-LABEL: f9:
;CHECK: floatunsisf
entry:
@ -94,6 +114,8 @@ entry:
define double @f10(i32 %a) {
;CHECK-VFP-LABEL: f10:
;CHECK-VFP: vcvt.f64.u32
;CHECK-VFP-SP-LABEL: f10:
;CHECK-VFP-SP: bl __aeabi_ui2d
;CHECK-LABEL: f10:
;CHECK: floatunsidf
entry:

7
test/CodeGen/ARM/half.ll
View File

@ -1,6 +1,8 @@
; RUN: llc < %s -mtriple=thumbv7-apple-ios7.0 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-OLD
; RUN: llc < %s -mtriple=thumbv7s-apple-ios7.0 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-F16
; RUN: llc < %s -mtriple=thumbv8-apple-ios7.0 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-V8
; RUN: llc < %s -mtriple=armv8r-none-none-eabi | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-V8
; RUN: llc < %s -mtriple=armv8r-none-none-eabi -mattr=+fp-only-sp | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-V8-SP
define void @test_load_store(half* %in, half* %out) {
; CHECK-LABEL: test_load_store:
@ -33,6 +35,7 @@ define float @test_extend32(half* %addr) {
; CHECK-OLD: b.w ___extendhfsf2
; CHECK-F16: vcvtb.f32.f16
; CHECK-V8: vcvtb.f32.f16
; CHECK-V8-SP: vcvtb.f32.f16
%val16 = load half, half* %addr
%val32 = fpext half %val16 to float
ret float %val32
@ -46,6 +49,8 @@ define double @test_extend64(half* %addr) {
; CHECK-F16: vcvtb.f32.f16
; CHECK-F16: vcvt.f64.f32
; CHECK-V8: vcvtb.f64.f16
; CHECK-V8-SP: vcvtb.f32.f16
; CHECK-V8-SP: bl __aeabi_f2d
%val16 = load half, half* %addr
%val32 = fpext half %val16 to double
ret double %val32
@ -57,6 +62,7 @@ define void @test_trunc32(float %in, half* %addr) {
; CHECK-OLD: bl ___truncsfhf2
; CHECK-F16: vcvtb.f16.f32
; CHECK-V8: vcvtb.f16.f32
; CHECK-V8-SP: vcvtb.f16.f32
%val16 = fptrunc float %in to half
store half %val16, half* %addr
ret void
@ -68,6 +74,7 @@ define void @test_trunc64(double %in, half* %addr) {
; CHECK-OLD: bl ___truncdfhf2
; CHECK-F16: bl ___truncdfhf2
; CHECK-V8: vcvtb.f16.f64
; CHECK-V8-SP: bl __aeabi_d2h
%val16 = fptrunc double %in to half
store half %val16, half* %addr
ret void