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AMDGPU: Fix i64 global cmpxchg
This was using extract_subreg sub0 to extract the low register of the result instead of sub0_sub1, producing an invalid copy. There doesn't seem to be a way to use the compound subreg indices in tablegen since those are generated, so manually select it. llvm-svn: 272344
This commit is contained in:
Matt Arsenault
parent
ce7bee3c77
commit
bcec847408
@ -128,7 +128,7 @@ private:
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SDValue &Offset, SDValue &GLC, SDValue &SLC,
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SDValue &TFE) const;
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bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &Soffset,
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SDValue &Offset, SDValue &GLC) const;
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SDValue &Offset, SDValue &SLC) const;
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bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &Soffset,
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SDValue &Offset) const;
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void SelectMUBUFConstant(SDValue Constant,
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@ -169,6 +169,7 @@ private:
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void SelectS_BFEFromShifts(SDNode *N);
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void SelectS_BFE(SDNode *N);
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void SelectBRCOND(SDNode *N);
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void SelectATOMIC_CMP_SWAP(SDNode *N);
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// Include the pieces autogenerated from the target description.
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#include "AMDGPUGenDAGISel.inc"
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@ -545,6 +546,10 @@ void AMDGPUDAGToDAGISel::Select(SDNode *N) {
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case ISD::BRCOND:
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SelectBRCOND(N);
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return;
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case AMDGPUISD::ATOMIC_CMP_SWAP:
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SelectATOMIC_CMP_SWAP(N);
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return;
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}
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SelectCode(N);
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@ -1014,9 +1019,11 @@ bool AMDGPUDAGToDAGISel::SelectMUBUF(SDValue Addr, SDValue &Ptr,
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}
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if (isLegalMUBUFImmOffset(C1)) {
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Offset = CurDAG->getTargetConstant(C1->getZExtValue(), DL, MVT::i16);
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return true;
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} else if (isUInt<32>(C1->getZExtValue())) {
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Offset = CurDAG->getTargetConstant(C1->getZExtValue(), DL, MVT::i16);
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return true;
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}
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if (isUInt<32>(C1->getZExtValue())) {
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// Illegal offset, store it in soffset.
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Offset = CurDAG->getTargetConstant(0, DL, MVT::i16);
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SOffset = SDValue(CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32,
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@ -1151,8 +1158,8 @@ bool AMDGPUDAGToDAGISel::SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc,
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}
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bool AMDGPUDAGToDAGISel::SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc,
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SDValue &Soffset, SDValue &Offset,
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SDValue &GLC) const {
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SDValue SLC, TFE;
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SDValue &SLC) const {
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SDValue GLC, TFE;
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return SelectMUBUFOffset(Addr, SRsrc, Soffset, Offset, GLC, SLC, TFE);
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}
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@ -1488,6 +1495,68 @@ void AMDGPUDAGToDAGISel::SelectBRCOND(SDNode *N) {
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return;
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}
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// This is here because there isn't a way to use the generated sub0_sub1 as the
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// subreg index to EXTRACT_SUBREG in tablegen.
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void AMDGPUDAGToDAGISel::SelectATOMIC_CMP_SWAP(SDNode *N) {
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MemSDNode *Mem = cast<MemSDNode>(N);
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unsigned AS = Mem->getAddressSpace();
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MVT VT = N->getSimpleValueType(0);
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bool Is32 = (VT == MVT::i32);
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SDLoc SL(N);
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MachineSDNode *CmpSwap = nullptr;
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if (Subtarget->hasAddr64()) {
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SDValue SRsrc, VAddr, SOffset, Offset, GLC, SLC;
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if (SelectMUBUFAddr64(Mem->getBasePtr(), SRsrc, VAddr, SOffset, Offset, SLC)) {
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unsigned Opcode = Is32 ? AMDGPU::BUFFER_ATOMIC_CMPSWAP_RTN_ADDR64 :
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AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_RTN_ADDR64;
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SDValue CmpVal = Mem->getOperand(2);
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// XXX - Do we care about glue operands?
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SDValue Ops[] = {
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CmpVal, VAddr, SRsrc, SOffset, Offset, SLC, Mem->getChain()
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};
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CmpSwap = CurDAG->getMachineNode(Opcode, SL, Mem->getVTList(), Ops);
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}
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}
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if (!CmpSwap) {
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SDValue SRsrc, SOffset, Offset, SLC;
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if (SelectMUBUFOffset(Mem->getBasePtr(), SRsrc, SOffset, Offset, SLC)) {
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unsigned Opcode = Is32 ? AMDGPU::BUFFER_ATOMIC_CMPSWAP_RTN_OFFSET :
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AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_RTN_OFFSET;
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SDValue CmpVal = Mem->getOperand(2);
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SDValue Ops[] = {
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CmpVal, SRsrc, SOffset, Offset, SLC, Mem->getChain()
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};
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CmpSwap = CurDAG->getMachineNode(Opcode, SL, Mem->getVTList(), Ops);
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}
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}
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if (!CmpSwap) {
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SelectCode(N);
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return;
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}
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MachineSDNode::mmo_iterator MMOs = MF->allocateMemRefsArray(1);
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*MMOs = Mem->getMemOperand();
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CmpSwap->setMemRefs(MMOs, MMOs + 1);
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unsigned SubReg = Is32 ? AMDGPU::sub0 : AMDGPU::sub0_sub1;
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SDValue Extract
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= CurDAG->getTargetExtractSubreg(SubReg, SL, VT, SDValue(CmpSwap, 0));
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ReplaceUses(SDValue(N, 0), Extract);
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ReplaceUses(SDValue(N, 1), SDValue(CmpSwap, 1));
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CurDAG->RemoveDeadNode(N);
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}
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bool AMDGPUDAGToDAGISel::SelectVOP3Mods(SDValue In, SDValue &Src,
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SDValue &SrcMods) const {
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@ -191,6 +191,10 @@ public:
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return FlatForGlobal;
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}
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bool hasAddr64() const {
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return (getGeneration() < VOLCANIC_ISLANDS);
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}
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bool hasBFE() const {
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return (getGeneration() >= EVERGREEN);
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}
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@ -2197,9 +2197,9 @@ SDValue SITargetLowering::LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) co
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SDValue NewOld = DAG.getBuildVector(VecType, DL, {New, Old});
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SDValue Ops[] = { ChainIn, Addr, NewOld };
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SDVTList VTList = DAG.getVTList(VT, MVT::Other);
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return DAG.getMemIntrinsicNode(AMDGPUISD::ATOMIC_CMP_SWAP, DL,
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VTList, Ops, VT, AtomicNode->getMemOperand());
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return DAG.getMemIntrinsicNode(AMDGPUISD::ATOMIC_CMP_SWAP, DL, Op->getVTList(),
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Ops, VT, AtomicNode->getMemOperand());
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}
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//===----------------------------------------------------------------------===//
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@ -3285,37 +3285,6 @@ def : MUBUFScratchStorePat <BUFFER_STORE_DWORD_OFFEN, i32, store_private>;
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def : MUBUFScratchStorePat <BUFFER_STORE_DWORDX2_OFFEN, v2i32, store_private>;
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def : MUBUFScratchStorePat <BUFFER_STORE_DWORDX4_OFFEN, v4i32, store_private>;
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multiclass MUBUFCmpSwapPat <Instruction inst_addr64, Instruction inst_offset,
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SDPatternOperator node, ValueType data_vt,
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ValueType node_vt> {
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let Predicates = [isSI] in {
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def : Pat <
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(node_vt (node (MUBUFAddr64Atomic v4i32:$srsrc, i64:$vaddr, i32:$soffset,
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i16:$offset, i1:$slc), data_vt:$vdata_in)),
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(EXTRACT_SUBREG
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(inst_addr64 $vdata_in, $vaddr, $srsrc, $soffset, $offset, $slc), sub0)
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>;
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}
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def : Pat <
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(node_vt (node (MUBUFOffsetAtomic v4i32:$srsrc, i32:$soffset, i16:$offset,
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i1:$slc), data_vt:$vdata_in)),
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(EXTRACT_SUBREG
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(inst_offset $vdata_in, $srsrc, $soffset, $offset, $slc), sub0)
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>;
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}
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defm : MUBUFCmpSwapPat <BUFFER_ATOMIC_CMPSWAP_RTN_ADDR64,
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BUFFER_ATOMIC_CMPSWAP_RTN_OFFSET,
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atomic_cmp_swap_global, v2i32, i32>;
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defm : MUBUFCmpSwapPat <BUFFER_ATOMIC_CMPSWAP_X2_RTN_ADDR64,
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BUFFER_ATOMIC_CMPSWAP_X2_RTN_OFFSET,
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atomic_cmp_swap_global, v2i64, i64>;
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//===----------------------------------------------------------------------===//
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// MTBUF Patterns
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//===----------------------------------------------------------------------===//
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@ -841,6 +841,113 @@ entry:
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ret void
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}
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; FUNC-LABEL: {{^}}atomic_cmpxchg_i64_offset:
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; GCN: buffer_atomic_cmpswap_x2 v[{{[0-9]+}}:{{[0-9]+}}], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:32{{$}}
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define void @atomic_cmpxchg_i64_offset(i64 addrspace(1)* %out, i64 %in, i64 %old) {
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entry:
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%gep = getelementptr i64, i64 addrspace(1)* %out, i64 4
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%val = cmpxchg volatile i64 addrspace(1)* %gep, i64 %old, i64 %in seq_cst seq_cst
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ret void
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}
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; FUNC-LABEL: {{^}}atomic_cmpxchg_i64_soffset:
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; GCN: s_mov_b32 [[SREG:s[0-9]+]], 0x11940
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; GCN: buffer_atomic_cmpswap_x2 v[{{[0-9]+}}:{{[0-9]+}}], off, s[{{[0-9]+}}:{{[0-9]+}}], [[SREG]]{{$}}
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define void @atomic_cmpxchg_i64_soffset(i64 addrspace(1)* %out, i64 %in, i64 %old) {
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entry:
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%gep = getelementptr i64, i64 addrspace(1)* %out, i64 9000
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%val = cmpxchg volatile i64 addrspace(1)* %gep, i64 %old, i64 %in seq_cst seq_cst
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ret void
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}
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; FUNC-LABEL: {{^}}atomic_cmpxchg_i64_ret_offset:
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; GCN: buffer_atomic_cmpswap_x2 v{{\[}}[[RET:[0-9]+]]{{:[0-9]+}}], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:32 glc{{$}}
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; GCN: buffer_store_dwordx2 v{{\[}}[[RET]]:
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define void @atomic_cmpxchg_i64_ret_offset(i64 addrspace(1)* %out, i64 addrspace(1)* %out2, i64 %in, i64 %old) {
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entry:
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%gep = getelementptr i64, i64 addrspace(1)* %out, i64 4
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%val = cmpxchg volatile i64 addrspace(1)* %gep, i64 %old, i64 %in seq_cst seq_cst
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%extract0 = extractvalue { i64, i1 } %val, 0
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store i64 %extract0, i64 addrspace(1)* %out2
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ret void
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}
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; FUNC-LABEL: {{^}}atomic_cmpxchg_i64_addr64_offset:
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; CI: buffer_atomic_cmpswap_x2 v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:32{{$}}
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; VI: flat_atomic_cmpswap_x2 v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
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define void @atomic_cmpxchg_i64_addr64_offset(i64 addrspace(1)* %out, i64 %in, i64 %index, i64 %old) {
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entry:
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%ptr = getelementptr i64, i64 addrspace(1)* %out, i64 %index
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%gep = getelementptr i64, i64 addrspace(1)* %ptr, i64 4
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%val = cmpxchg volatile i64 addrspace(1)* %gep, i64 %old, i64 %in seq_cst seq_cst
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ret void
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}
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; FUNC-LABEL: {{^}}atomic_cmpxchg_i64_ret_addr64_offset:
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; CI: buffer_atomic_cmpswap_x2 v{{\[}}[[RET:[0-9]+]]:{{[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:32 glc{{$}}
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; VI: flat_atomic_cmpswap_x2 v{{\[}}[[RET:[0-9]+]]:{{[0-9]+\]}}, v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] glc{{$}}
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; GCN: buffer_store_dwordx2 v{{\[}}[[RET]]:
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define void @atomic_cmpxchg_i64_ret_addr64_offset(i64 addrspace(1)* %out, i64 addrspace(1)* %out2, i64 %in, i64 %index, i64 %old) {
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entry:
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%ptr = getelementptr i64, i64 addrspace(1)* %out, i64 %index
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%gep = getelementptr i64, i64 addrspace(1)* %ptr, i64 4
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%val = cmpxchg volatile i64 addrspace(1)* %gep, i64 %old, i64 %in seq_cst seq_cst
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%extract0 = extractvalue { i64, i1 } %val, 0
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store i64 %extract0, i64 addrspace(1)* %out2
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ret void
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}
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; FUNC-LABEL: {{^}}atomic_cmpxchg_i64:
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; GCN: buffer_atomic_cmpswap_x2 v[{{[0-9]+:[0-9]+}}], off, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}}
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define void @atomic_cmpxchg_i64(i64 addrspace(1)* %out, i64 %in, i64 %old) {
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entry:
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%val = cmpxchg volatile i64 addrspace(1)* %out, i64 %old, i64 %in seq_cst seq_cst
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ret void
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}
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; FUNC-LABEL: {{^}}atomic_cmpxchg_i64_ret:
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; GCN: buffer_atomic_cmpswap_x2 v{{\[}}[[RET:[0-9]+]]:{{[0-9]+}}], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 glc
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; GCN: buffer_store_dwordx2 v{{\[}}[[RET]]:
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define void @atomic_cmpxchg_i64_ret(i64 addrspace(1)* %out, i64 addrspace(1)* %out2, i64 %in, i64 %old) {
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entry:
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%val = cmpxchg volatile i64 addrspace(1)* %out, i64 %old, i64 %in seq_cst seq_cst
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%extract0 = extractvalue { i64, i1 } %val, 0
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store i64 %extract0, i64 addrspace(1)* %out2
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ret void
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}
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; FUNC-LABEL: {{^}}atomic_cmpxchg_i64_addr64:
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; CI: buffer_atomic_cmpswap_x2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}}
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; VI: flat_atomic_cmpswap_x2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]{{$}}
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define void @atomic_cmpxchg_i64_addr64(i64 addrspace(1)* %out, i64 %in, i64 %index, i64 %old) {
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entry:
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%ptr = getelementptr i64, i64 addrspace(1)* %out, i64 %index
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%val = cmpxchg volatile i64 addrspace(1)* %ptr, i64 %old, i64 %in seq_cst seq_cst
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ret void
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}
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; FUNC-LABEL: {{^}}atomic_cmpxchg_i64_ret_addr64:
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; CI: buffer_atomic_cmpswap_x2 v{{\[}}[[RET:[0-9]+]]:{{[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}}
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; VI: flat_atomic_cmpswap_x2 v{{\[}}[[RET:[0-9]+]]:{{[0-9]+\]}}, v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] glc{{$}}
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; GCN: buffer_store_dwordx2 v{{\[}}[[RET]]:
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define void @atomic_cmpxchg_i64_ret_addr64(i64 addrspace(1)* %out, i64 addrspace(1)* %out2, i64 %in, i64 %index, i64 %old) {
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entry:
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%ptr = getelementptr i64, i64 addrspace(1)* %out, i64 %index
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%val = cmpxchg volatile i64 addrspace(1)* %ptr, i64 %old, i64 %in seq_cst seq_cst
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%extract0 = extractvalue { i64, i1 } %val, 0
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store i64 %extract0, i64 addrspace(1)* %out2
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ret void
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}
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; FUNC-LABEL: {{^}}atomic_load_i64_offset:
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; CI: buffer_load_dwordx2 [[RET:v\[[0-9]+:[0-9]+\]]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:32 glc{{$}}
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; VI: flat_load_dwordx2 [[RET:v\[[0-9]+:[0-9]\]]], v[{{[0-9]+}}:{{[0-9]+}}] glc{{$}}
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@ -928,99 +1035,3 @@ entry:
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store atomic i64 %in, i64 addrspace(1)* %ptr seq_cst, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}atomic_cmpxchg_i64_offset:
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; GCN: buffer_atomic_cmpswapx2 v[{{[0-9]+}}:{{[0-9]+}}], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}}
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define void @atomic_cmpxchg_i64_offset(i64 addrspace(1)* %out, i64 %in, i64 %old) {
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entry:
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%gep = getelementptr i64, i64 addrspace(1)* %out, i64 4
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%val = cmpxchg volatile i64 addrspace(1)* %gep, i64 %old, i64 %in seq_cst seq_cst
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ret void
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}
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; FUNC-LABEL: {{^}}atomic_cmpxchg_i64_ret_offset:
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; GCN: buffer_atomic_cmpswapx2 v{{\[}}[[RET:[0-9]+]]{{:[0-9]+}}], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc{{$}}
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; GCN: buffer_store_dwordx2 v[[RET]]
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define void @atomic_cmpxchg_i64_ret_offset(i64 addrspace(1)* %out, i64 addrspace(1)* %out2, i64 %in, i64 %old) {
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entry:
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%gep = getelementptr i64, i64 addrspace(1)* %out, i64 4
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%val = cmpxchg volatile i64 addrspace(1)* %gep, i64 %old, i64 %in seq_cst seq_cst
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%extract0 = extractvalue { i64, i1 } %val, 0
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store i64 %extract0, i64 addrspace(1)* %out2
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ret void
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}
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; FUNC-LABEL: {{^}}atomic_cmpxchg_i64_addr64_offset:
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||||
; SI: buffer_atomic_cmpswapx2 v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16{{$}}
|
||||
|
||||
; VI: flat_atomic_cmpswapx2 v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
|
||||
define void @atomic_cmpxchg_i64_addr64_offset(i64 addrspace(1)* %out, i64 %in, i64 %index, i64 %old) {
|
||||
entry:
|
||||
%ptr = getelementptr i64, i64 addrspace(1)* %out, i64 %index
|
||||
%gep = getelementptr i64, i64 addrspace(1)* %ptr, i64 4
|
||||
%val = cmpxchg volatile i64 addrspace(1)* %gep, i64 %old, i64 %in seq_cst seq_cst
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}atomic_cmpxchg_i64_ret_addr64_offset:
|
||||
; SI: buffer_atomic_cmpswapx2 v{{\[}}[[RET:[0-9]+]]:{{[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16 glc{{$}}
|
||||
; VI: flat_atomic_cmpswapx2 v[[RET:[0-9]+]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] glc{{$}}
|
||||
; GCN: buffer_store_dword v[[RET]]
|
||||
define void @atomic_cmpxchg_i64_ret_addr64_offset(i64 addrspace(1)* %out, i64 addrspace(1)* %out2, i64 %in, i64 %index, i64 %old) {
|
||||
entry:
|
||||
%ptr = getelementptr i64, i64 addrspace(1)* %out, i64 %index
|
||||
%gep = getelementptr i64, i64 addrspace(1)* %ptr, i64 4
|
||||
%val = cmpxchg volatile i64 addrspace(1)* %gep, i64 %old, i64 %in seq_cst seq_cst
|
||||
%extract0 = extractvalue { i64, i1 } %val, 0
|
||||
store i64 %extract0, i64 addrspace(1)* %out2
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}atomic_cmpxchg_i64:
|
||||
; GCN: buffer_atomic_cmpswap v[{{[0-9]+:[0-9]+}}], off, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}}
|
||||
define void @atomic_cmpxchg_i64(i64 addrspace(1)* %out, i64 %in, i64 %old) {
|
||||
entry:
|
||||
%val = cmpxchg volatile i64 addrspace(1)* %out, i64 %old, i64 %in seq_cst seq_cst
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}atomic_cmpxchg_i64_ret:
|
||||
; GCN: buffer_atomic_cmpswap v{{\[}}[[RET:[0-9]+]]:{{[0-9]+}}], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 glc
|
||||
; GCN: buffer_store_dword v[[RET]]
|
||||
define void @atomic_cmpxchg_i64_ret(i64 addrspace(1)* %out, i64 addrspace(1)* %out2, i64 %in, i64 %old) {
|
||||
entry:
|
||||
%val = cmpxchg volatile i64 addrspace(1)* %out, i64 %old, i64 %in seq_cst seq_cst
|
||||
%extract0 = extractvalue { i64, i1 } %val, 0
|
||||
store i64 %extract0, i64 addrspace(1)* %out2
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}atomic_cmpxchg_i64_addr64:
|
||||
; SI: buffer_atomic_cmpswap v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}}
|
||||
; VI: flat_atomic_cmpswap v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]{{$}}
|
||||
define void @atomic_cmpxchg_i64_addr64(i64 addrspace(1)* %out, i64 %in, i64 %index, i64 %old) {
|
||||
entry:
|
||||
%ptr = getelementptr i64, i64 addrspace(1)* %out, i64 %index
|
||||
%val = cmpxchg volatile i64 addrspace(1)* %ptr, i64 %old, i64 %in seq_cst seq_cst
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}atomic_cmpxchg_i64_ret_addr64:
|
||||
; SI: buffer_atomic_cmpswap v{{\[}}[[RET:[0-9]+]]:{{[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}}
|
||||
; VI: flat_atomic_cmpswap v[[RET:[0-9]+]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] glc{{$}}
|
||||
; GCN: buffer_store_dword v[[RET]]
|
||||
define void @atomic_cmpxchg_i64_ret_addr64(i64 addrspace(1)* %out, i64 addrspace(1)* %out2, i64 %in, i64 %index, i64 %old) {
|
||||
entry:
|
||||
%ptr = getelementptr i64, i64 addrspace(1)* %out, i64 %index
|
||||
%val = cmpxchg volatile i64 addrspace(1)* %ptr, i64 %old, i64 %in seq_cst seq_cst
|
||||
%extract0 = extractvalue { i64, i1 } %val, 0
|
||||
store i64 %extract0, i64 addrspace(1)* %out2
|
||||
ret void
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user