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[SystemZ] Utilize Test Data Class instructions.
This adds a new SystemZ-specific intrinsic, llvm.s390.tdc.f(32|64|128), which maps straight to the test data class instructions. A new IR pass is added to recognize instructions that can be converted to TDC and perform the necessary replacements. Differential Revision: http://reviews.llvm.org/D21949 llvm-svn: 275016
This commit is contained in:
Marcin Koscielnicki
parent
7e66859260
commit
bd07f66851
@ -374,3 +374,14 @@ let TargetPrefix = "s390" in {
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[llvm_v2f64_ty, llvm_i32_ty, llvm_i32_ty],
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[IntrNoMem]>;
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}
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//===----------------------------------------------------------------------===//
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//
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// Misc intrinsics
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//
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//===----------------------------------------------------------------------===//
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let TargetPrefix = "s390" in {
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def int_s390_tdc : Intrinsic<[llvm_i32_ty], [llvm_anyfloat_ty, llvm_i64_ty],
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[IntrNoMem]>;
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}
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@ -30,6 +30,7 @@ add_llvm_target(SystemZCodeGen
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SystemZSubtarget.cpp
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SystemZTargetMachine.cpp
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SystemZTargetTransformInfo.cpp
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SystemZTDC.cpp
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)
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add_subdirectory(AsmParser)
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@ -36,10 +36,6 @@ We don't use the BRANCH ON INDEX instructions.
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--
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We don't use the TEST DATA CLASS instructions.
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--
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We only use MVC, XC and CLC for constant-length block operations.
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We could extend them to variable-length operations too,
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using EXECUTE RELATIVE LONG.
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@ -87,6 +87,11 @@ const unsigned CCMASK_VCMP_MIXED = CCMASK_1;
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const unsigned CCMASK_VCMP_NONE = CCMASK_3;
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const unsigned CCMASK_VCMP = CCMASK_0 | CCMASK_1 | CCMASK_3;
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// Condition-code mask assignments for Test Data Class.
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const unsigned CCMASK_TDC_NOMATCH = CCMASK_0;
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const unsigned CCMASK_TDC_MATCH = CCMASK_1;
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const unsigned CCMASK_TDC = CCMASK_TDC_NOMATCH | CCMASK_TDC_MATCH;
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// The position of the low CC bit in an IPM result.
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const unsigned IPM_CC = 28;
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@ -94,6 +99,41 @@ const unsigned IPM_CC = 28;
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const unsigned PFD_READ = 1;
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const unsigned PFD_WRITE = 2;
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// Mask assignments for TDC
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const unsigned TDCMASK_ZERO_PLUS = 0x800;
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const unsigned TDCMASK_ZERO_MINUS = 0x400;
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const unsigned TDCMASK_NORMAL_PLUS = 0x200;
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const unsigned TDCMASK_NORMAL_MINUS = 0x100;
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const unsigned TDCMASK_SUBNORMAL_PLUS = 0x080;
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const unsigned TDCMASK_SUBNORMAL_MINUS = 0x040;
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const unsigned TDCMASK_INFINITY_PLUS = 0x020;
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const unsigned TDCMASK_INFINITY_MINUS = 0x010;
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const unsigned TDCMASK_QNAN_PLUS = 0x008;
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const unsigned TDCMASK_QNAN_MINUS = 0x004;
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const unsigned TDCMASK_SNAN_PLUS = 0x002;
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const unsigned TDCMASK_SNAN_MINUS = 0x001;
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const unsigned TDCMASK_ZERO = TDCMASK_ZERO_PLUS | TDCMASK_ZERO_MINUS;
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const unsigned TDCMASK_POSITIVE = TDCMASK_NORMAL_PLUS |
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TDCMASK_SUBNORMAL_PLUS |
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TDCMASK_INFINITY_PLUS;
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const unsigned TDCMASK_NEGATIVE = TDCMASK_NORMAL_MINUS |
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TDCMASK_SUBNORMAL_MINUS |
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TDCMASK_INFINITY_MINUS;
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const unsigned TDCMASK_NAN = TDCMASK_QNAN_PLUS |
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TDCMASK_QNAN_MINUS |
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TDCMASK_SNAN_PLUS |
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TDCMASK_SNAN_MINUS;
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const unsigned TDCMASK_PLUS = TDCMASK_POSITIVE |
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TDCMASK_ZERO_PLUS |
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TDCMASK_QNAN_PLUS |
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TDCMASK_SNAN_PLUS;
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const unsigned TDCMASK_MINUS = TDCMASK_NEGATIVE |
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TDCMASK_ZERO_MINUS |
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TDCMASK_QNAN_MINUS |
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TDCMASK_SNAN_MINUS;
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const unsigned TDCMASK_ALL = TDCMASK_PLUS | TDCMASK_MINUS;
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// Number of bits in a vector register.
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const unsigned VectorBits = 128;
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@ -138,6 +178,7 @@ FunctionPass *createSystemZElimComparePass(SystemZTargetMachine &TM);
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FunctionPass *createSystemZShortenInstPass(SystemZTargetMachine &TM);
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FunctionPass *createSystemZLongBranchPass(SystemZTargetMachine &TM);
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FunctionPass *createSystemZLDCleanupPass(SystemZTargetMachine &TM);
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FunctionPass *createSystemZTDCPass();
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} // end namespace llvm
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#endif
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@ -1444,6 +1444,11 @@ static bool isIntrinsicWithCC(SDValue Op, unsigned &Opcode, unsigned &CCValid) {
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CCValid = SystemZ::CCMASK_VCMP;
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return true;
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case Intrinsic::s390_tdc:
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Opcode = SystemZISD::TDC;
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CCValid = SystemZ::CCMASK_TDC;
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return true;
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default:
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return false;
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}
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382
lib/Target/SystemZ/SystemZTDC.cpp
Normal file
382
lib/Target/SystemZ/SystemZTDC.cpp
Normal file
@ -0,0 +1,382 @@
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//===-- SystemZTDC.cpp - Utilize Test Data Class instruction --------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass looks for instructions that can be replaced by a Test Data Class
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// instruction, and replaces them when profitable.
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//
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// Roughly, the following rules are recognized:
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//
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// 1: fcmp pred X, 0 -> tdc X, mask
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// 2: fcmp pred X, +-inf -> tdc X, mask
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// 3: fcmp pred X, +-minnorm -> tdc X, mask
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// 4: tdc (fabs X), mask -> tdc X, newmask
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// 5: icmp slt (bitcast float X to int), 0 -> tdc X, mask [ie. signbit]
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// 6: icmp sgt (bitcast float X to int), -1 -> tdc X, mask
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// 7: icmp ne/eq (call @llvm.s390.tdc.*(X, mask)) -> tdc X, mask/~mask
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// 8: and i1 (tdc X, M1), (tdc X, M2) -> tdc X, (M1 & M2)
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// 9: or i1 (tdc X, M1), (tdc X, M2) -> tdc X, (M1 | M2)
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// 10: xor i1 (tdc X, M1), (tdc X, M2) -> tdc X, (M1 ^ M2)
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//
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// The pass works in 4 steps:
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//
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// 1. All fcmp and icmp instructions in a function are checked for a match
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// with rules 1-3 and 5-7. Their TDC equivalents are stored in
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// the ConvertedInsts mapping. If the operand of a fcmp instruction is
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// a fabs, it's also folded according to rule 4.
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// 2. All and/or/xor i1 instructions whose both operands have been already
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// mapped are mapped according to rules 8-10. LogicOpsWorklist is used
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// as a queue of instructions to check.
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// 3. All mapped instructions that are considered worthy of conversion (ie.
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// replacing them will actually simplify the final code) are replaced
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// with a call to the s390.tdc intrinsic.
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// 4. All intermediate results of replaced instructions are removed if unused.
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//
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// Instructions that match rules 1-3 are considered unworthy of conversion
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// on their own (since a comparison instruction is superior), but are mapped
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// in the hopes of folding the result using rules 4 and 8-10 (likely removing
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// the original comparison in the process).
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//
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//===----------------------------------------------------------------------===//
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#include "SystemZ.h"
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#include "llvm/ADT/MapVector.h"
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#include "llvm/IR/Constants.h"
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#include "llvm/IR/Instructions.h"
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#include "llvm/IR/InstIterator.h"
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#include "llvm/IR/IntrinsicInst.h"
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#include "llvm/IR/IRBuilder.h"
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#include "llvm/IR/LegacyPassManager.h"
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#include "llvm/IR/Module.h"
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#include <deque>
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#include <set>
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using namespace llvm;
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namespace llvm {
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void initializeSystemZTDCPassPass(PassRegistry&);
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}
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namespace {
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class SystemZTDCPass : public FunctionPass {
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public:
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static char ID;
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SystemZTDCPass() : FunctionPass(ID) {
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initializeSystemZTDCPassPass(*PassRegistry::getPassRegistry());
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}
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bool runOnFunction(Function &F) override;
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private:
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// Maps seen instructions that can be mapped to a TDC, values are
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// (TDC operand, TDC mask, worthy flag) triples.
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MapVector<Instruction *, std::tuple<Value *, int, bool>> ConvertedInsts;
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// The queue of and/or/xor i1 instructions to be potentially folded.
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std::vector<BinaryOperator *> LogicOpsWorklist;
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// Instructions matched while folding, to be removed at the end if unused.
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std::set<Instruction *> PossibleJunk;
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// Tries to convert a fcmp instruction.
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void convertFCmp(CmpInst &I);
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// Tries to convert an icmp instruction.
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void convertICmp(CmpInst &I);
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// Tries to convert an i1 and/or/xor instruction, whose both operands
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// have been already converted.
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void convertLogicOp(BinaryOperator &I);
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// Marks an instruction as converted - adds it to ConvertedInsts and adds
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// any and/or/xor i1 users to the queue.
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void converted(Instruction *I, Value *V, int Mask, bool Worthy) {
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ConvertedInsts[I] = std::make_tuple(V, Mask, Worthy);
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auto &M = *I->getFunction()->getParent();
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auto &Ctx = M.getContext();
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for (auto *U : I->users()) {
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auto *LI = dyn_cast<BinaryOperator>(U);
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if (LI && LI->getType() == Type::getInt1Ty(Ctx) &&
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(LI->getOpcode() == Instruction::And ||
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LI->getOpcode() == Instruction::Or ||
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LI->getOpcode() == Instruction::Xor)) {
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LogicOpsWorklist.push_back(LI);
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}
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}
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}
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};
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} // end anonymous namespace
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char SystemZTDCPass::ID = 0;
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INITIALIZE_PASS(SystemZTDCPass, "systemz-tdc",
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"SystemZ Test Data Class optimization", false, false)
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FunctionPass *llvm::createSystemZTDCPass() {
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return new SystemZTDCPass();
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}
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void SystemZTDCPass::convertFCmp(CmpInst &I) {
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Value *Op0 = I.getOperand(0);
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auto *Const = dyn_cast<ConstantFP>(I.getOperand(1));
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auto Pred = I.getPredicate();
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// Only comparisons with consts are interesting.
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if (!Const)
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return;
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// Compute the smallest normal number (and its negation).
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auto &Sem = Op0->getType()->getFltSemantics();
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APFloat Smallest = APFloat::getSmallestNormalized(Sem);
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APFloat NegSmallest = Smallest;
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NegSmallest.changeSign();
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// Check if Const is one of our recognized consts.
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int WhichConst;
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if (Const->isZero()) {
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// All comparisons with 0 can be converted.
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WhichConst = 0;
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} else if (Const->isInfinity()) {
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// Likewise for infinities.
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WhichConst = Const->isNegative() ? 2 : 1;
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} else if (Const->isExactlyValue(Smallest)) {
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// For Smallest, we cannot do EQ separately from GT.
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if ((Pred & CmpInst::FCMP_OGE) != CmpInst::FCMP_OGE &&
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(Pred & CmpInst::FCMP_OGE) != 0)
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return;
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WhichConst = 3;
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} else if (Const->isExactlyValue(NegSmallest)) {
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// Likewise for NegSmallest, we cannot do EQ separately from LT.
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if ((Pred & CmpInst::FCMP_OLE) != CmpInst::FCMP_OLE &&
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(Pred & CmpInst::FCMP_OLE) != 0)
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return;
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WhichConst = 4;
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} else {
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// Not one of our special constants.
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return;
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}
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// Partial masks to use for EQ, GT, LT, UN comparisons, respectively.
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static const int Masks[][4] = {
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{ // 0
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SystemZ::TDCMASK_ZERO, // eq
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SystemZ::TDCMASK_POSITIVE, // gt
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SystemZ::TDCMASK_NEGATIVE, // lt
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SystemZ::TDCMASK_NAN, // un
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},
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{ // inf
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SystemZ::TDCMASK_INFINITY_PLUS, // eq
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0, // gt
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(SystemZ::TDCMASK_ZERO |
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SystemZ::TDCMASK_NEGATIVE |
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SystemZ::TDCMASK_NORMAL_PLUS |
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SystemZ::TDCMASK_SUBNORMAL_PLUS), // lt
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SystemZ::TDCMASK_NAN, // un
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},
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{ // -inf
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SystemZ::TDCMASK_INFINITY_MINUS, // eq
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(SystemZ::TDCMASK_ZERO |
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SystemZ::TDCMASK_POSITIVE |
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SystemZ::TDCMASK_NORMAL_MINUS |
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SystemZ::TDCMASK_SUBNORMAL_MINUS), // gt
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0, // lt
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SystemZ::TDCMASK_NAN, // un
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},
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{ // minnorm
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0, // eq (unsupported)
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(SystemZ::TDCMASK_NORMAL_PLUS |
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SystemZ::TDCMASK_INFINITY_PLUS), // gt (actually ge)
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(SystemZ::TDCMASK_ZERO |
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SystemZ::TDCMASK_NEGATIVE |
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SystemZ::TDCMASK_SUBNORMAL_PLUS), // lt
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SystemZ::TDCMASK_NAN, // un
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},
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{ // -minnorm
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0, // eq (unsupported)
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(SystemZ::TDCMASK_ZERO |
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SystemZ::TDCMASK_POSITIVE |
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SystemZ::TDCMASK_SUBNORMAL_MINUS), // gt
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(SystemZ::TDCMASK_NORMAL_MINUS |
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SystemZ::TDCMASK_INFINITY_MINUS), // lt (actually le)
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SystemZ::TDCMASK_NAN, // un
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}
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};
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// Construct the mask as a combination of the partial masks.
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int Mask = 0;
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if (Pred & CmpInst::FCMP_OEQ)
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Mask |= Masks[WhichConst][0];
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if (Pred & CmpInst::FCMP_OGT)
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Mask |= Masks[WhichConst][1];
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if (Pred & CmpInst::FCMP_OLT)
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Mask |= Masks[WhichConst][2];
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if (Pred & CmpInst::FCMP_UNO)
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Mask |= Masks[WhichConst][3];
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// A lone fcmp is unworthy of tdc conversion on its own, but may become
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// worthy if combined with fabs.
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bool Worthy = false;
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if (CallInst *CI = dyn_cast<CallInst>(Op0)) {
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Function *F = CI->getCalledFunction();
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if (F && F->getIntrinsicID() == Intrinsic::fabs) {
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// Fold with fabs - adjust the mask appropriately.
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Mask &= SystemZ::TDCMASK_PLUS;
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Mask |= Mask >> 1;
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Op0 = CI->getArgOperand(0);
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// A combination of fcmp with fabs is a win, unless the constant
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// involved is 0 (which is handled by later passes).
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Worthy = WhichConst != 0;
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PossibleJunk.insert(CI);
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}
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}
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converted(&I, Op0, Mask, Worthy);
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}
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void SystemZTDCPass::convertICmp(CmpInst &I) {
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Value *Op0 = I.getOperand(0);
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auto *Const = dyn_cast<ConstantInt>(I.getOperand(1));
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auto Pred = I.getPredicate();
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// All our icmp rules involve comparisons with consts.
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if (!Const)
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return;
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if (auto *Cast = dyn_cast<BitCastInst>(Op0)) {
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// Check for icmp+bitcast used for signbit.
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if (!Cast->getSrcTy()->isFloatTy() &&
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!Cast->getSrcTy()->isDoubleTy() &&
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!Cast->getSrcTy()->isFP128Ty())
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return;
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Value *V = Cast->getOperand(0);
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int Mask;
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if (Pred == CmpInst::ICMP_SLT && Const->isZero()) {
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// icmp slt (bitcast X), 0 - set if sign bit true
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Mask = SystemZ::TDCMASK_MINUS;
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} else if (Pred == CmpInst::ICMP_SGT && Const->isMinusOne()) {
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// icmp sgt (bitcast X), -1 - set if sign bit false
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Mask = SystemZ::TDCMASK_PLUS;
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} else {
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// Not a sign bit check.
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return;
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}
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PossibleJunk.insert(Cast);
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converted(&I, V, Mask, true);
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} else if (auto *CI = dyn_cast<CallInst>(Op0)) {
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// Check if this is a pre-existing call of our tdc intrinsic.
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Function *F = CI->getCalledFunction();
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if (!F || F->getIntrinsicID() != Intrinsic::s390_tdc)
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return;
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if (!Const->isZero())
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return;
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Value *V = CI->getArgOperand(0);
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auto *MaskC = dyn_cast<ConstantInt>(CI->getArgOperand(1));
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// Bail if the mask is not a constant.
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if (!MaskC)
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return;
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int Mask = MaskC->getZExtValue();
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Mask &= SystemZ::TDCMASK_ALL;
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if (Pred == CmpInst::ICMP_NE) {
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// icmp ne (call llvm.s390.tdc(...)), 0 -> simple TDC
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} else if (Pred == CmpInst::ICMP_EQ) {
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// icmp eq (call llvm.s390.tdc(...)), 0 -> TDC with inverted mask
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Mask ^= SystemZ::TDCMASK_ALL;
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} else {
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// An unknown comparison - ignore.
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return;
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}
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PossibleJunk.insert(CI);
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converted(&I, V, Mask, false);
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}
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}
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void SystemZTDCPass::convertLogicOp(BinaryOperator &I) {
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Value *Op0, *Op1;
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int Mask0, Mask1;
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bool Worthy0, Worthy1;
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std::tie(Op0, Mask0, Worthy0) = ConvertedInsts[cast<Instruction>(I.getOperand(0))];
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std::tie(Op1, Mask1, Worthy1) = ConvertedInsts[cast<Instruction>(I.getOperand(1))];
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if (Op0 != Op1)
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return;
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int Mask;
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switch (I.getOpcode()) {
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case Instruction::And:
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Mask = Mask0 & Mask1;
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break;
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case Instruction::Or:
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Mask = Mask0 | Mask1;
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break;
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case Instruction::Xor:
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||||
Mask = Mask0 ^ Mask1;
|
||||
break;
|
||||
default:
|
||||
llvm_unreachable("Unknown op in convertLogicOp");
|
||||
}
|
||||
converted(&I, Op0, Mask, true);
|
||||
}
|
||||
|
||||
bool SystemZTDCPass::runOnFunction(Function &F) {
|
||||
ConvertedInsts.clear();
|
||||
LogicOpsWorklist.clear();
|
||||
PossibleJunk.clear();
|
||||
|
||||
// Look for icmp+fcmp instructions.
|
||||
for (auto &I : instructions(F)) {
|
||||
if (I.getOpcode() == Instruction::FCmp)
|
||||
convertFCmp(cast<CmpInst>(I));
|
||||
else if (I.getOpcode() == Instruction::ICmp)
|
||||
convertICmp(cast<CmpInst>(I));
|
||||
}
|
||||
|
||||
// If none found, bail already.
|
||||
if (ConvertedInsts.empty())
|
||||
return false;
|
||||
|
||||
// Process the queue of logic instructions.
|
||||
while (!LogicOpsWorklist.empty()) {
|
||||
BinaryOperator *Op = LogicOpsWorklist.back();
|
||||
LogicOpsWorklist.pop_back();
|
||||
// If both operands mapped, and the instruction itself not yet mapped,
|
||||
// convert it.
|
||||
if (ConvertedInsts.count(dyn_cast<Instruction>(Op->getOperand(0))) &&
|
||||
ConvertedInsts.count(dyn_cast<Instruction>(Op->getOperand(1))) &&
|
||||
!ConvertedInsts.count(Op))
|
||||
convertLogicOp(*Op);
|
||||
}
|
||||
|
||||
// Time to actually replace the instructions. Do it in the reverse order
|
||||
// of finding them, since there's a good chance the earlier ones will be
|
||||
// unused (due to being folded into later ones).
|
||||
Module &M = *F.getParent();
|
||||
auto &Ctx = M.getContext();
|
||||
Value *Zero32 = ConstantInt::get(Type::getInt32Ty(Ctx), 0);
|
||||
bool MadeChange = false;
|
||||
for (auto &It : reverse(ConvertedInsts)) {
|
||||
Instruction *I = It.first;
|
||||
Value *V;
|
||||
int Mask;
|
||||
bool Worthy;
|
||||
std::tie(V, Mask, Worthy) = It.second;
|
||||
if (!I->user_empty()) {
|
||||
// If used and unworthy of conversion, skip it.
|
||||
if (!Worthy)
|
||||
continue;
|
||||
// Call the intrinsic, compare result with 0.
|
||||
Value *TDCFunc = Intrinsic::getDeclaration(&M, Intrinsic::s390_tdc,
|
||||
V->getType());
|
||||
IRBuilder<> IRB(I);
|
||||
Value *MaskVal = ConstantInt::get(Type::getInt64Ty(Ctx), Mask);
|
||||
Instruction *TDC = IRB.CreateCall(TDCFunc, {V, MaskVal});
|
||||
Value *ICmp = IRB.CreateICmp(CmpInst::ICMP_NE, TDC, Zero32);
|
||||
I->replaceAllUsesWith(ICmp);
|
||||
}
|
||||
// If unused, or used and converted, remove it.
|
||||
I->eraseFromParent();
|
||||
MadeChange = true;
|
||||
}
|
||||
|
||||
if (!MadeChange)
|
||||
return false;
|
||||
|
||||
// We've actually done something - now clear misc accumulated junk (fabs,
|
||||
// bitcast).
|
||||
for (auto *I : PossibleJunk)
|
||||
if (I->user_empty())
|
||||
I->eraseFromParent();
|
||||
|
||||
return true;
|
||||
}
|
||||
@ -122,6 +122,9 @@ public:
|
||||
} // end anonymous namespace
|
||||
|
||||
void SystemZPassConfig::addIRPasses() {
|
||||
if (getOptLevel() != CodeGenOpt::None)
|
||||
addPass(createSystemZTDCPass());
|
||||
|
||||
TargetPassConfig::addIRPasses();
|
||||
}
|
||||
|
||||
|
||||
95
test/CodeGen/SystemZ/tdc-01.ll
Normal file
95
test/CodeGen/SystemZ/tdc-01.ll
Normal file
@ -0,0 +1,95 @@
|
||||
; Test the Test Data Class instruction, selected manually via the intrinsic.
|
||||
;
|
||||
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
|
||||
|
||||
declare i32 @llvm.s390.tdc.f32(float, i64)
|
||||
declare i32 @llvm.s390.tdc.f64(double, i64)
|
||||
declare i32 @llvm.s390.tdc.f128(fp128, i64)
|
||||
|
||||
; Check using as i32 - f32
|
||||
define i32 @f1(float %x) {
|
||||
; CHECK-LABEL: f1
|
||||
; CHECK: tceb %f0, 123
|
||||
; CHECK: ipm %r2
|
||||
; CHECK: srl %r2, 28
|
||||
%res = call i32 @llvm.s390.tdc.f32(float %x, i64 123)
|
||||
ret i32 %res
|
||||
}
|
||||
|
||||
; Check using as i32 - f64
|
||||
define i32 @f2(double %x) {
|
||||
; CHECK-LABEL: f2
|
||||
; CHECK: tcdb %f0, 123
|
||||
; CHECK: ipm %r2
|
||||
; CHECK: srl %r2, 28
|
||||
%res = call i32 @llvm.s390.tdc.f64(double %x, i64 123)
|
||||
ret i32 %res
|
||||
}
|
||||
|
||||
; Check using as i32 - f128
|
||||
define i32 @f3(fp128 %x) {
|
||||
; CHECK-LABEL: f3
|
||||
; CHECK: ld %f0, 0(%r2)
|
||||
; CHECK: ld %f2, 8(%r2)
|
||||
; CHECK: tcxb %f0, 123
|
||||
; CHECK: ipm %r2
|
||||
; CHECK: srl %r2, 28
|
||||
%res = call i32 @llvm.s390.tdc.f128(fp128 %x, i64 123)
|
||||
ret i32 %res
|
||||
}
|
||||
|
||||
declare void @g()
|
||||
|
||||
; Check branch
|
||||
define void @f4(float %x) {
|
||||
; CHECK-LABEL: f4
|
||||
; CHECK: tceb %f0, 123
|
||||
; CHECK: jgl g
|
||||
; CHECK: br %r14
|
||||
%res = call i32 @llvm.s390.tdc.f32(float %x, i64 123)
|
||||
%cond = icmp ne i32 %res, 0
|
||||
br i1 %cond, label %call, label %exit
|
||||
|
||||
call:
|
||||
tail call void @g()
|
||||
br label %exit
|
||||
|
||||
exit:
|
||||
ret void
|
||||
}
|
||||
|
||||
; Check branch negated
|
||||
define void @f5(float %x) {
|
||||
; CHECK-LABEL: f5
|
||||
; CHECK: tceb %f0, 123
|
||||
; CHECK: jge g
|
||||
; CHECK: br %r14
|
||||
%res = call i32 @llvm.s390.tdc.f32(float %x, i64 123)
|
||||
%cond = icmp eq i32 %res, 0
|
||||
br i1 %cond, label %call, label %exit
|
||||
|
||||
call:
|
||||
tail call void @g()
|
||||
br label %exit
|
||||
|
||||
exit:
|
||||
ret void
|
||||
}
|
||||
|
||||
; Check non-const mask
|
||||
define void @f6(float %x, i64 %y) {
|
||||
; CHECK-LABEL: f6
|
||||
; CHECK: tceb %f0, 0(%r2)
|
||||
; CHECK: jge g
|
||||
; CHECK: br %r14
|
||||
%res = call i32 @llvm.s390.tdc.f32(float %x, i64 %y)
|
||||
%cond = icmp eq i32 %res, 0
|
||||
br i1 %cond, label %call, label %exit
|
||||
|
||||
call:
|
||||
tail call void @g()
|
||||
br label %exit
|
||||
|
||||
exit:
|
||||
ret void
|
||||
}
|
||||
96
test/CodeGen/SystemZ/tdc-02.ll
Normal file
96
test/CodeGen/SystemZ/tdc-02.ll
Normal file
@ -0,0 +1,96 @@
|
||||
; Test the Test Data Class instruction logic operation folding.
|
||||
;
|
||||
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
|
||||
|
||||
declare i32 @llvm.s390.tdc.f32(float, i64)
|
||||
declare i32 @llvm.s390.tdc.f64(double, i64)
|
||||
declare i32 @llvm.s390.tdc.f128(fp128, i64)
|
||||
|
||||
; Check using or i1
|
||||
define i32 @f1(float %x) {
|
||||
; CHECK-LABEL: f1
|
||||
; CHECK: tceb %f0, 7
|
||||
; CHECK-NEXT: ipm [[REG1:%r[0-9]+]]
|
||||
; CHECK-NEXT: risbg %r2, [[REG1]], 63, 191, 36
|
||||
%a = call i32 @llvm.s390.tdc.f32(float %x, i64 3)
|
||||
%b = call i32 @llvm.s390.tdc.f32(float %x, i64 6)
|
||||
%a1 = icmp ne i32 %a, 0
|
||||
%b1 = icmp ne i32 %b, 0
|
||||
%res = or i1 %a1, %b1
|
||||
%xres = zext i1 %res to i32
|
||||
ret i32 %xres
|
||||
}
|
||||
|
||||
; Check using and i1
|
||||
define i32 @f2(double %x) {
|
||||
; CHECK-LABEL: f2
|
||||
; CHECK: tcdb %f0, 2
|
||||
; CHECK-NEXT: ipm [[REG1:%r[0-9]+]]
|
||||
; CHECK-NEXT: risbg %r2, [[REG1]], 63, 191, 36
|
||||
%a = call i32 @llvm.s390.tdc.f64(double %x, i64 3)
|
||||
%b = call i32 @llvm.s390.tdc.f64(double %x, i64 6)
|
||||
%a1 = icmp ne i32 %a, 0
|
||||
%b1 = icmp ne i32 %b, 0
|
||||
%res = and i1 %a1, %b1
|
||||
%xres = zext i1 %res to i32
|
||||
ret i32 %xres
|
||||
}
|
||||
|
||||
; Check using xor i1
|
||||
define i32 @f3(fp128 %x) {
|
||||
; CHECK-LABEL: f3
|
||||
; CHECK: tcxb %f0, 5
|
||||
; CHECK-NEXT: ipm [[REG1:%r[0-9]+]]
|
||||
; CHECK-NEXT: risbg %r2, [[REG1]], 63, 191, 36
|
||||
%a = call i32 @llvm.s390.tdc.f128(fp128 %x, i64 3)
|
||||
%b = call i32 @llvm.s390.tdc.f128(fp128 %x, i64 6)
|
||||
%a1 = icmp ne i32 %a, 0
|
||||
%b1 = icmp ne i32 %b, 0
|
||||
%res = xor i1 %a1, %b1
|
||||
%xres = zext i1 %res to i32
|
||||
ret i32 %xres
|
||||
}
|
||||
|
||||
; Check using xor i1 - negated test
|
||||
define i32 @f4(fp128 %x) {
|
||||
; CHECK-LABEL: f4
|
||||
; CHECK: tcxb %f0, 4090
|
||||
; CHECK-NEXT: ipm [[REG1:%r[0-9]+]]
|
||||
; CHECK-NEXT: risbg %r2, [[REG1]], 63, 191, 36
|
||||
%a = call i32 @llvm.s390.tdc.f128(fp128 %x, i64 3)
|
||||
%b = call i32 @llvm.s390.tdc.f128(fp128 %x, i64 6)
|
||||
%a1 = icmp ne i32 %a, 0
|
||||
%b1 = icmp eq i32 %b, 0
|
||||
%res = xor i1 %a1, %b1
|
||||
%xres = zext i1 %res to i32
|
||||
ret i32 %xres
|
||||
}
|
||||
|
||||
; Check different first args
|
||||
define i32 @f5(float %x, float %y) {
|
||||
; CHECK-LABEL: f5
|
||||
; CHECK-NOT: tceb {{%f[0-9]+}}, 5
|
||||
; CHECK-DAG: tceb %f0, 3
|
||||
; CHECK-DAG: tceb %f2, 6
|
||||
%a = call i32 @llvm.s390.tdc.f32(float %x, i64 3)
|
||||
%b = call i32 @llvm.s390.tdc.f32(float %y, i64 6)
|
||||
%a1 = icmp ne i32 %a, 0
|
||||
%b1 = icmp ne i32 %b, 0
|
||||
%res = xor i1 %a1, %b1
|
||||
%xres = zext i1 %res to i32
|
||||
ret i32 %xres
|
||||
}
|
||||
|
||||
; Non-const mask (not supported)
|
||||
define i32 @f6(float %x, i64 %y) {
|
||||
; CHECK-LABEL: f6
|
||||
; CHECK-DAG: tceb %f0, 0(%r2)
|
||||
; CHECK-DAG: tceb %f0, 6
|
||||
%a = call i32 @llvm.s390.tdc.f32(float %x, i64 %y)
|
||||
%b = call i32 @llvm.s390.tdc.f32(float %x, i64 6)
|
||||
%a1 = icmp ne i32 %a, 0
|
||||
%b1 = icmp ne i32 %b, 0
|
||||
%res = xor i1 %a1, %b1
|
||||
%xres = zext i1 %res to i32
|
||||
ret i32 %xres
|
||||
}
|
||||
139
test/CodeGen/SystemZ/tdc-03.ll
Normal file
139
test/CodeGen/SystemZ/tdc-03.ll
Normal file
@ -0,0 +1,139 @@
|
||||
; Test the Test Data Class instruction logic operation conversion from
|
||||
; compares.
|
||||
;
|
||||
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
|
||||
|
||||
declare float @llvm.fabs.f32(float)
|
||||
declare double @llvm.fabs.f64(double)
|
||||
declare fp128 @llvm.fabs.f128(fp128)
|
||||
|
||||
; Compare with 0 (unworthy)
|
||||
define i32 @f1(float %x) {
|
||||
; CHECK-LABEL: f1
|
||||
; CHECK-NOT: tceb
|
||||
; CHECK: ltebr {{%f[0-9]+}}, %f0
|
||||
; CHECK-NOT: tceb
|
||||
%res = fcmp ugt float %x, 0.0
|
||||
%xres = zext i1 %res to i32
|
||||
ret i32 %xres
|
||||
}
|
||||
|
||||
; Compare fabs with 0 (unworthy)
|
||||
define i32 @f2(float %x) {
|
||||
; CHECK-LABEL: f2
|
||||
; CHECK-NOT: tceb
|
||||
; CHECK: lpebr {{%f[0-9]+}}, %f0
|
||||
; CHECK-NOT: tceb
|
||||
%y = call float @llvm.fabs.f32(float %x)
|
||||
%res = fcmp ugt float %y, 0.0
|
||||
%xres = zext i1 %res to i32
|
||||
ret i32 %xres
|
||||
}
|
||||
|
||||
; Compare with inf (unworthy)
|
||||
define i32 @f3(float %x) {
|
||||
; CHECK-LABEL: f3
|
||||
; CHECK-NOT: tceb
|
||||
; CHECK: ceb %f0, 0(%r{{[0-9]+}})
|
||||
; CHECK-NOT: tceb
|
||||
%res = fcmp ult float %x, 0x7ff0000000000000
|
||||
%xres = zext i1 %res to i32
|
||||
ret i32 %xres
|
||||
}
|
||||
|
||||
; Compare fabs with inf
|
||||
define i32 @f4(float %x) {
|
||||
; CHECK-LABEL: f4
|
||||
; CHECK: tceb %f0, 4047
|
||||
%y = call float @llvm.fabs.f32(float %x)
|
||||
%res = fcmp ult float %y, 0x7ff0000000000000
|
||||
%xres = zext i1 %res to i32
|
||||
ret i32 %xres
|
||||
}
|
||||
|
||||
; Compare with minnorm (unworthy)
|
||||
define i32 @f5(float %x) {
|
||||
; CHECK-LABEL: f5
|
||||
; CHECK-NOT: tceb
|
||||
; CHECK: ceb %f0, 0(%r{{[0-9]+}})
|
||||
; CHECK-NOT: tceb
|
||||
%res = fcmp ult float %x, 0x3810000000000000
|
||||
%xres = zext i1 %res to i32
|
||||
ret i32 %xres
|
||||
}
|
||||
|
||||
; Compare fabs with minnorm
|
||||
define i32 @f6(float %x) {
|
||||
; CHECK-LABEL: f6
|
||||
; CHECK: tceb %f0, 3279
|
||||
%y = call float @llvm.fabs.f32(float %x)
|
||||
%res = fcmp ult float %y, 0x3810000000000000
|
||||
%xres = zext i1 %res to i32
|
||||
ret i32 %xres
|
||||
}
|
||||
|
||||
; Compare fabs with minnorm, unsupported condition
|
||||
define i32 @f7(float %x) {
|
||||
; CHECK-LABEL: f7
|
||||
; CHECK-NOT: tceb
|
||||
; CHECK: lpdfr [[REG:%f[0-9]+]], %f0
|
||||
; CHECK: ceb [[REG]], 0(%r{{[0-9]+}})
|
||||
; CHECK-NOT: tceb
|
||||
%y = call float @llvm.fabs.f32(float %x)
|
||||
%res = fcmp ugt float %y, 0x3810000000000000
|
||||
%xres = zext i1 %res to i32
|
||||
ret i32 %xres
|
||||
}
|
||||
|
||||
; Compare fabs with unsupported constant
|
||||
define i32 @f8(float %x) {
|
||||
; CHECK-LABEL: f8
|
||||
; CHECK-NOT: tceb
|
||||
; CHECK: lpdfr [[REG:%f[0-9]+]], %f0
|
||||
; CHECK: ceb [[REG]], 0(%r{{[0-9]+}})
|
||||
; CHECK-NOT: tceb
|
||||
%y = call float @llvm.fabs.f32(float %x)
|
||||
%res = fcmp ult float %y, 0x3ff0000000000000
|
||||
%xres = zext i1 %res to i32
|
||||
ret i32 %xres
|
||||
}
|
||||
|
||||
; Compare fabs with minnorm - double
|
||||
define i32 @f9(double %x) {
|
||||
; CHECK-LABEL: f9
|
||||
; CHECK: tcdb %f0, 3279
|
||||
%y = call double @llvm.fabs.f64(double %x)
|
||||
%res = fcmp ult double %y, 0x0010000000000000
|
||||
%xres = zext i1 %res to i32
|
||||
ret i32 %xres
|
||||
}
|
||||
|
||||
; Compare fabs with minnorm - long double
|
||||
define i32 @f10(fp128 %x) {
|
||||
; CHECK-LABEL: f10
|
||||
; CHECK: tcxb %f0, 3279
|
||||
%y = call fp128 @llvm.fabs.f128(fp128 %x)
|
||||
%res = fcmp ult fp128 %y, 0xL00000000000000000001000000000000
|
||||
%xres = zext i1 %res to i32
|
||||
ret i32 %xres
|
||||
}
|
||||
|
||||
; Compare fabs for one with inf - clang's isfinite
|
||||
define i32 @f11(double %x) {
|
||||
; CHECK-LABEL: f11
|
||||
; CHECK: tcdb %f0, 4032
|
||||
%y = call double @llvm.fabs.f64(double %x)
|
||||
%res = fcmp one double %y, 0x7ff0000000000000
|
||||
%xres = zext i1 %res to i32
|
||||
ret i32 %xres
|
||||
}
|
||||
|
||||
; Compare fabs for oeq with inf - clang's isinf
|
||||
define i32 @f12(double %x) {
|
||||
; CHECK-LABEL: f12
|
||||
; CHECK: tcdb %f0, 48
|
||||
%y = call double @llvm.fabs.f64(double %x)
|
||||
%res = fcmp oeq double %y, 0x7ff0000000000000
|
||||
%xres = zext i1 %res to i32
|
||||
ret i32 %xres
|
||||
}
|
||||
85
test/CodeGen/SystemZ/tdc-04.ll
Normal file
85
test/CodeGen/SystemZ/tdc-04.ll
Normal file
@ -0,0 +1,85 @@
|
||||
; Test the Test Data Class instruction logic operation conversion from
|
||||
; signbit extraction.
|
||||
;
|
||||
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
|
||||
;
|
||||
|
||||
; Extract sign bit.
|
||||
define i32 @f1(float %x) {
|
||||
; CHECK-LABEL: f1
|
||||
; CHECK: tceb %f0, 1365
|
||||
%cast = bitcast float %x to i32
|
||||
%res = icmp slt i32 %cast, 0
|
||||
%xres = zext i1 %res to i32
|
||||
ret i32 %xres
|
||||
}
|
||||
|
||||
; Extract negated sign bit.
|
||||
define i32 @f2(float %x) {
|
||||
; CHECK-LABEL: f2
|
||||
; CHECK: tceb %f0, 2730
|
||||
%cast = bitcast float %x to i32
|
||||
%res = icmp sgt i32 %cast, -1
|
||||
%xres = zext i1 %res to i32
|
||||
ret i32 %xres
|
||||
}
|
||||
|
||||
; Extract sign bit.
|
||||
define i32 @f3(double %x) {
|
||||
; CHECK-LABEL: f3
|
||||
; CHECK: tcdb %f0, 1365
|
||||
%cast = bitcast double %x to i64
|
||||
%res = icmp slt i64 %cast, 0
|
||||
%xres = zext i1 %res to i32
|
||||
ret i32 %xres
|
||||
}
|
||||
|
||||
; Extract negated sign bit.
|
||||
define i32 @f4(double %x) {
|
||||
; CHECK-LABEL: f4
|
||||
; CHECK: tcdb %f0, 2730
|
||||
%cast = bitcast double %x to i64
|
||||
%res = icmp sgt i64 %cast, -1
|
||||
%xres = zext i1 %res to i32
|
||||
ret i32 %xres
|
||||
}
|
||||
|
||||
; Extract sign bit.
|
||||
define i32 @f5(fp128 %x) {
|
||||
; CHECK-LABEL: f5
|
||||
; CHECK: tcxb %f0, 1365
|
||||
%cast = bitcast fp128 %x to i128
|
||||
%res = icmp slt i128 %cast, 0
|
||||
%xres = zext i1 %res to i32
|
||||
ret i32 %xres
|
||||
}
|
||||
|
||||
; Extract negated sign bit.
|
||||
define i32 @f6(fp128 %x) {
|
||||
; CHECK-LABEL: f6
|
||||
; CHECK: tcxb %f0, 2730
|
||||
%cast = bitcast fp128 %x to i128
|
||||
%res = icmp sgt i128 %cast, -1
|
||||
%xres = zext i1 %res to i32
|
||||
ret i32 %xres
|
||||
}
|
||||
|
||||
; Wrong const.
|
||||
define i32 @f7(float %x) {
|
||||
; CHECK-LABEL: f7
|
||||
; CHECK-NOT: tceb
|
||||
%cast = bitcast float %x to i32
|
||||
%res = icmp slt i32 %cast, -1
|
||||
%xres = zext i1 %res to i32
|
||||
ret i32 %xres
|
||||
}
|
||||
|
||||
; Wrong pred.
|
||||
define i32 @f8(float %x) {
|
||||
; CHECK-LABEL: f8
|
||||
; CHECK-NOT: tceb
|
||||
%cast = bitcast float %x to i32
|
||||
%res = icmp eq i32 %cast, 0
|
||||
%xres = zext i1 %res to i32
|
||||
ret i32 %xres
|
||||
}
|
||||
97
test/CodeGen/SystemZ/tdc-05.ll
Normal file
97
test/CodeGen/SystemZ/tdc-05.ll
Normal file
@ -0,0 +1,97 @@
|
||||
; Test the Test Data Class instruction logic operation conversion from
|
||||
; compares, combined with signbit or other compares to ensure worthiness.
|
||||
;
|
||||
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
|
||||
;
|
||||
|
||||
declare float @llvm.fabs.f32(float)
|
||||
declare double @llvm.fabs.f64(double)
|
||||
declare fp128 @llvm.fabs.f128(fp128)
|
||||
|
||||
; Compare with 0, extract sign bit
|
||||
define i32 @f1(float %x) {
|
||||
; CHECK-LABEL: f1
|
||||
; CHECK: tceb %f0, 2047
|
||||
%cast = bitcast float %x to i32
|
||||
%sign = icmp slt i32 %cast, 0
|
||||
%fcmp = fcmp ugt float %x, 0.0
|
||||
%res = or i1 %sign, %fcmp
|
||||
%xres = zext i1 %res to i32
|
||||
ret i32 %xres
|
||||
}
|
||||
|
||||
; Compare with inf, extract negated sign bit
|
||||
define i32 @f2(float %x) {
|
||||
; CHECK-LABEL: f2
|
||||
; CHECK: tceb %f0, 2698
|
||||
%cast = bitcast float %x to i32
|
||||
%sign = icmp sgt i32 %cast, -1
|
||||
%fcmp = fcmp ult float %x, 0x7ff0000000000000
|
||||
%res = and i1 %sign, %fcmp
|
||||
%xres = zext i1 %res to i32
|
||||
ret i32 %xres
|
||||
}
|
||||
|
||||
; Compare with minnorm, extract negated sign bit
|
||||
define i32 @f3(float %x) {
|
||||
; CHECK-LABEL: f3
|
||||
; CHECK: tceb %f0, 2176
|
||||
%cast = bitcast float %x to i32
|
||||
%sign = icmp sgt i32 %cast, -1
|
||||
%fcmp = fcmp olt float %x, 0x3810000000000000
|
||||
%res = and i1 %sign, %fcmp
|
||||
%xres = zext i1 %res to i32
|
||||
ret i32 %xres
|
||||
}
|
||||
|
||||
; Test float isnormal, from clang.
|
||||
define i32 @f4(float %x) {
|
||||
; CHECK-LABEL: f4
|
||||
; CHECK: tceb %f0, 768
|
||||
%y = call float @llvm.fabs.f32(float %x)
|
||||
%ord = fcmp ord float %x, 0.0
|
||||
%a = fcmp ult float %y, 0x7ff0000000000000
|
||||
%b = fcmp uge float %y, 0x3810000000000000
|
||||
%c = and i1 %a, %b
|
||||
%res = and i1 %ord, %c
|
||||
%xres = zext i1 %res to i32
|
||||
ret i32 %xres
|
||||
}
|
||||
|
||||
; Check for negative 0.
|
||||
define i32 @f5(float %x) {
|
||||
; CHECK-LABEL: f5
|
||||
; CHECK: tceb %f0, 1024
|
||||
%cast = bitcast float %x to i32
|
||||
%sign = icmp slt i32 %cast, 0
|
||||
%fcmp = fcmp oeq float %x, 0.0
|
||||
%res = and i1 %sign, %fcmp
|
||||
%xres = zext i1 %res to i32
|
||||
ret i32 %xres
|
||||
}
|
||||
|
||||
; Test isnormal, from clang.
|
||||
define i32 @f6(double %x) {
|
||||
; CHECK-LABEL: f6
|
||||
; CHECK: tcdb %f0, 768
|
||||
%y = call double @llvm.fabs.f64(double %x)
|
||||
%ord = fcmp ord double %x, 0.0
|
||||
%a = fcmp ult double %y, 0x7ff0000000000000
|
||||
%b = fcmp uge double %y, 0x0010000000000000
|
||||
%c = and i1 %ord, %a
|
||||
%res = and i1 %b, %c
|
||||
%xres = zext i1 %res to i32
|
||||
ret i32 %xres
|
||||
}
|
||||
|
||||
; Test isinf || isnan, from clang.
|
||||
define i32 @f7(double %x) {
|
||||
; CHECK-LABEL: f7
|
||||
; CHECK: tcdb %f0, 63
|
||||
%y = call double @llvm.fabs.f64(double %x)
|
||||
%a = fcmp oeq double %y, 0x7ff0000000000000
|
||||
%b = fcmp uno double %x, 0.0
|
||||
%res = or i1 %a, %b
|
||||
%xres = zext i1 %res to i32
|
||||
ret i32 %xres
|
||||
}
|
||||
48
test/CodeGen/SystemZ/tdc-06.ll
Normal file
48
test/CodeGen/SystemZ/tdc-06.ll
Normal file
@ -0,0 +1,48 @@
|
||||
; Test the Test Data Class instruction, as used by fpclassify.
|
||||
;
|
||||
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
|
||||
;
|
||||
|
||||
declare float @llvm.fabs.f32(float)
|
||||
declare double @llvm.fabs.f64(double)
|
||||
declare fp128 @llvm.fabs.f128(fp128)
|
||||
|
||||
define i32 @fpc(double %x) {
|
||||
entry:
|
||||
; CHECK-LABEL: fpc
|
||||
; CHECK: lhi %r2, 5
|
||||
; CHECK: ltdbr %f0, %f0
|
||||
; CHECK: je [[RET:.L.*]]
|
||||
%testeq = fcmp oeq double %x, 0.000000e+00
|
||||
br i1 %testeq, label %ret, label %nonzero
|
||||
|
||||
nonzero:
|
||||
; CHECK: lhi %r2, 1
|
||||
; CHECK: cdbr %f0, %f0
|
||||
; CHECK: jo [[RET]]
|
||||
%testnan = fcmp uno double %x, 0.000000e+00
|
||||
br i1 %testnan, label %ret, label %nonzeroord
|
||||
|
||||
nonzeroord:
|
||||
; CHECK: lhi %r2, 2
|
||||
; CHECK: tcdb %f0, 48
|
||||
; CHECK: jl [[RET]]
|
||||
%abs = tail call double @llvm.fabs.f64(double %x)
|
||||
%testinf = fcmp oeq double %abs, 0x7FF0000000000000
|
||||
br i1 %testinf, label %ret, label %finite
|
||||
|
||||
finite:
|
||||
; CHECK: lhi %r2, 3
|
||||
; CHECK: tcdb %f0, 831
|
||||
; CHECK: blr %r14
|
||||
; CHECK: lhi %r2, 4
|
||||
%testnormal = fcmp uge double %abs, 0x10000000000000
|
||||
%finres = select i1 %testnormal, i32 3, i32 4
|
||||
br label %ret
|
||||
|
||||
ret:
|
||||
; CHECK: [[RET]]:
|
||||
; CHECK: br %r14
|
||||
%res = phi i32 [ 5, %entry ], [ 1, %nonzero ], [ 2, %nonzeroord ], [ %finres, %finite ]
|
||||
ret i32 %res
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user